mmc: omap_hsmmc: Cleanup bitmap definitions of Interrupt Register
Define the most frequently used bitmasks of the Interrupt Enable / Interrupt Status register with consistent naming ( with _EN suffix). Use meaningful concatenation of bitfields for INT_EN_MASK, which shows which interrupts are enabled by default. No functional changes. Signed-off-by: Venkatraman S <svenkatr@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -80,29 +80,17 @@
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#define CLKD_SHIFT 6
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#define DTO_MASK 0x000F0000
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#define DTO_SHIFT 16
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#define INT_EN_MASK 0x307F0033
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#define BWR_ENABLE (1 << 4)
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#define BRR_ENABLE (1 << 5)
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#define DTO_ENABLE (1 << 20)
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#define INIT_STREAM (1 << 1)
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#define DP_SELECT (1 << 21)
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#define DDIR (1 << 4)
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#define DMA_EN 0x1
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#define DMAE 0x1
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#define MSBS (1 << 5)
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#define BCE (1 << 1)
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#define FOUR_BIT (1 << 1)
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#define HSPE (1 << 2)
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#define DDR (1 << 19)
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#define DW8 (1 << 5)
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#define CC 0x1
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#define TC 0x02
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#define OD 0x1
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#define ERR (1 << 15)
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#define CMD_TIMEOUT (1 << 16)
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#define DATA_TIMEOUT (1 << 20)
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#define CMD_CRC (1 << 17)
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#define DATA_CRC (1 << 21)
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#define CARD_ERR (1 << 28)
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#define STAT_CLEAR 0xFFFFFFFF
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#define INIT_STREAM_CMD 0x00000000
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#define DUAL_VOLT_OCR_BIT 7
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@ -111,6 +99,26 @@
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#define SOFTRESET (1 << 1)
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#define RESETDONE (1 << 0)
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/* Interrupt masks for IE and ISE register */
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#define CC_EN (1 << 0)
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#define TC_EN (1 << 1)
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#define BWR_EN (1 << 4)
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#define BRR_EN (1 << 5)
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#define ERR_EN (1 << 15)
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#define CTO_EN (1 << 16)
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#define CCRC_EN (1 << 17)
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#define CEB_EN (1 << 18)
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#define CIE_EN (1 << 19)
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#define DTO_EN (1 << 20)
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#define DCRC_EN (1 << 21)
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#define DEB_EN (1 << 22)
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#define CERR_EN (1 << 28)
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#define BADA_EN (1 << 29)
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#define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
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DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
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BRR_EN | BWR_EN | TC_EN | CC_EN)
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#define MMC_AUTOSUSPEND_DELAY 100
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#define MMC_TIMEOUT_MS 20
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#define OMAP_MMC_MIN_CLOCK 400000
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@ -458,13 +466,13 @@ static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
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unsigned int irq_mask;
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if (host->use_dma)
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irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
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irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
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else
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irq_mask = INT_EN_MASK;
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/* Disable timeout for erases */
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if (cmd->opcode == MMC_ERASE)
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irq_mask &= ~DTO_ENABLE;
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irq_mask &= ~DTO_EN;
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OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
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OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
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@ -702,8 +710,8 @@ static void send_init_stream(struct omap_hsmmc_host *host)
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OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
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timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
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while ((reg != CC) && time_before(jiffies, timeout))
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reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
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while ((reg != CC_EN) && time_before(jiffies, timeout))
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reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
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OMAP_HSMMC_WRITE(host->base, CON,
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OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
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@ -794,7 +802,7 @@ omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
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}
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if (host->use_dma)
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cmdreg |= DMA_EN;
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cmdreg |= DMAE;
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host->req_in_progress = 1;
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@ -1018,14 +1026,14 @@ static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
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data = host->data;
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dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
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if (status & ERR) {
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if (status & ERR_EN) {
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omap_hsmmc_dbg_report_irq(host, status);
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if (status & (CMD_TIMEOUT | CMD_CRC))
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if (status & (CTO_EN | CCRC_EN))
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end_cmd = 1;
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if (status & (CMD_TIMEOUT | DATA_TIMEOUT))
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if (status & (CTO_EN | DTO_EN))
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hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
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else if (status & (CMD_CRC | DATA_CRC))
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else if (status & (CCRC_EN | DCRC_EN))
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hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
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if (host->data || host->response_busy) {
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@ -1034,9 +1042,9 @@ static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
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}
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}
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if (end_cmd || ((status & CC) && host->cmd))
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if (end_cmd || ((status & CC_EN) && host->cmd))
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omap_hsmmc_cmd_done(host, host->cmd);
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if ((end_trans || (status & TC)) && host->mrq)
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if ((end_trans || (status & TC_EN)) && host->mrq)
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omap_hsmmc_xfer_done(host, data);
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}
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