drm/nouveau: remove remnants of nouveau_pgraph_engine

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nouveau_channel.c

@@ -406,7 +406,7 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
 	struct nouveau_channel *chan;
 	int ret;
 
-	if (dev_priv->engine.graph.accel_blocked)
+	if (!dev_priv->eng[NVOBJ_ENGINE_GR])
 		return -ENODEV;
 
 	if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)

drivers/gpu/drm/nouveau/nouveau_display.c

@@ -276,7 +276,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 	struct nouveau_fence *fence;
 	int ret;
 
-	if (dev_priv->engine.graph.accel_blocked)
+	if (!dev_priv->channel)
 		return -ENODEV;
 
 	s = kzalloc(sizeof(*s), GFP_KERNEL);

drivers/gpu/drm/nouveau/nouveau_drv.c

@@ -310,7 +310,6 @@ nouveau_pci_resume(struct pci_dev *pdev)
 		if (dev_priv->eng[i])
 			dev_priv->eng[i]->init(dev, i);
 	}
-	engine->graph.init(dev);
 	engine->fifo.init(dev);
 
 	nouveau_irq_postinstall(dev);

drivers/gpu/drm/nouveau/nouveau_drv.h

@@ -241,10 +241,7 @@ struct nouveau_channel {
 	struct nouveau_gpuobj *cache;
 	void *fifo_priv;
 
-	/* PGRAPH context */
+	/* Execution engine contexts */
-	/* XXX may be merge 2 pointers as private data ??? */
-	struct nouveau_gpuobj *ramin_grctx;
-	void *pgraph_ctx;
 	void *engctx[NVOBJ_ENGINE_NR];
 
 	/* NV50 VM */
@@ -372,30 +369,6 @@ struct nouveau_fifo_engine {
 	void (*tlb_flush)(struct drm_device *dev);
 };
 
-struct nouveau_pgraph_engine {
-	bool accel_blocked;
-	bool registered;
-	int grctx_size;
-	void *priv;
-
-	/* NV2x/NV3x context table (0x400780) */
-	struct nouveau_gpuobj *ctx_table;
-
-	int  (*init)(struct drm_device *);
-	void (*takedown)(struct drm_device *);
-
-	void (*fifo_access)(struct drm_device *, bool);
-
-	struct nouveau_channel *(*channel)(struct drm_device *);
-	int  (*create_context)(struct nouveau_channel *);
-	void (*destroy_context)(struct nouveau_channel *);
-	int  (*load_context)(struct nouveau_channel *);
-	int  (*unload_context)(struct drm_device *);
-	int  (*object_new)(struct nouveau_channel *chan, u32 handle, u16 class);
-	void (*tlb_flush)(struct drm_device *dev);
-
-};
-
 struct nouveau_display_engine {
 	void *priv;
 	int (*early_init)(struct drm_device *);
@@ -522,7 +495,6 @@ struct nouveau_engine {
 	struct nouveau_mc_engine      mc;
 	struct nouveau_timer_engine   timer;
 	struct nouveau_fb_engine      fb;
-	struct nouveau_pgraph_engine  graph;
 	struct nouveau_fifo_engine    fifo;
 	struct nouveau_display_engine display;
 	struct nouveau_gpio_engine    gpio;
@@ -1168,8 +1140,6 @@ extern struct nouveau_enum nv50_data_error_names[];
 
 /* nvc0_graph.c */
 extern int  nvc0_graph_create(struct drm_device *);
-extern void nvc0_graph_fifo_access(struct drm_device *, bool);
-extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
 
 /* nv84_crypt.c */
 extern int  nv84_crypt_create(struct drm_device *);

drivers/gpu/drm/nouveau/nouveau_object.c

@@ -620,7 +620,6 @@ int
 nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
 {
 	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
-	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 	struct drm_device *dev = chan->dev;
 	struct nouveau_gpuobj_class *oc;
 	int ret;
@@ -628,37 +627,25 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
 	NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
 
 	list_for_each_entry(oc, &dev_priv->classes, head) {
-		if (oc->id == class)
+		struct nouveau_exec_engine *eng = dev_priv->eng[oc->engine];
-			goto found;
+
+		if (oc->id != class)
+			continue;
+
+		if (oc->engine == NVOBJ_ENGINE_SW)
+			return nouveau_gpuobj_sw_new(chan, handle, class);
+
+		if (!chan->engctx[oc->engine]) {
+			ret = eng->context_new(chan, oc->engine);
+			if (ret)
+				return ret;
+		}
+
+		return eng->object_new(chan, oc->engine, handle, class);
 	}
 
 	NV_ERROR(dev, "illegal object class: 0x%x\n", class);
 	return -EINVAL;
-
-found:
-	if (!dev_priv->eng[oc->engine]) {
-		switch (oc->engine) {
-		case NVOBJ_ENGINE_SW:
-			return nouveau_gpuobj_sw_new(chan, handle, class);
-		case NVOBJ_ENGINE_GR:
-			if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) ||
-			    (dev_priv->card_type  < NV_20 && !chan->pgraph_ctx)) {
-				ret = pgraph->create_context(chan);
-				if (ret)
-					return ret;
-			}
-
-			return pgraph->object_new(chan, handle, class);
-		}
-	}
-
-	if (!chan->engctx[oc->engine]) {
-		ret = dev_priv->eng[oc->engine]->context_new(chan, oc->engine);
-		if (ret)
-			return ret;
-	}
-
-	return dev_priv->eng[oc->engine]->object_new(chan, oc->engine, handle, class);
 }
 
 static int
@@ -676,9 +663,6 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
 	size = 0x2000;
 	base = 0;
 
-	/* PGRAPH context */
-	size += dev_priv->engine.graph.grctx_size;
-
 	if (dev_priv->card_type == NV_50) {
 		/* Various fixed table thingos */
 		size += 0x1400; /* mostly unknown stuff */

drivers/gpu/drm/nouveau/nouveau_state.c

@@ -65,10 +65,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 		engine->timer.takedown		= nv04_timer_takedown;
 		engine->fb.init			= nv04_fb_init;
 		engine->fb.takedown		= nv04_fb_takedown;
-		engine->graph.init		= nouveau_stub_init;
-		engine->graph.takedown		= nouveau_stub_takedown;
-		engine->graph.channel		= nvc0_graph_channel;
-		engine->graph.fifo_access	= nvc0_graph_fifo_access;
 		engine->fifo.channels		= 16;
 		engine->fifo.init		= nv04_fifo_init;
 		engine->fifo.takedown		= nv04_fifo_fini;
@@ -117,10 +113,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 		engine->fb.init_tile_region	= nv10_fb_init_tile_region;
 		engine->fb.set_tile_region	= nv10_fb_set_tile_region;
 		engine->fb.free_tile_region	= nv10_fb_free_tile_region;
-		engine->graph.init		= nouveau_stub_init;
-		engine->graph.takedown		= nouveau_stub_takedown;
-		engine->graph.channel		= nvc0_graph_channel;
-		engine->graph.fifo_access	= nvc0_graph_fifo_access;
 		engine->fifo.channels		= 32;
 		engine->fifo.init		= nv10_fifo_init;
 		engine->fifo.takedown		= nv04_fifo_fini;
@@ -169,10 +161,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 		engine->fb.init_tile_region	= nv10_fb_init_tile_region;
 		engine->fb.set_tile_region	= nv10_fb_set_tile_region;
 		engine->fb.free_tile_region	= nv10_fb_free_tile_region;
-		engine->graph.init		= nouveau_stub_init;
-		engine->graph.takedown		= nouveau_stub_takedown;
-		engine->graph.channel		= nvc0_graph_channel;
-		engine->graph.fifo_access	= nvc0_graph_fifo_access;
 		engine->fifo.channels		= 32;
 		engine->fifo.init		= nv10_fifo_init;
 		engine->fifo.takedown		= nv04_fifo_fini;
@@ -221,10 +209,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 		engine->fb.init_tile_region	= nv30_fb_init_tile_region;
 		engine->fb.set_tile_region	= nv10_fb_set_tile_region;
 		engine->fb.free_tile_region	= nv30_fb_free_tile_region;
-		engine->graph.init		= nouveau_stub_init;
-		engine->graph.takedown		= nouveau_stub_takedown;
-		engine->graph.channel		= nvc0_graph_channel;
-		engine->graph.fifo_access	= nvc0_graph_fifo_access;
 		engine->fifo.channels		= 32;
 		engine->fifo.init		= nv10_fifo_init;
 		engine->fifo.takedown		= nv04_fifo_fini;
@@ -276,10 +260,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 		engine->fb.init_tile_region	= nv30_fb_init_tile_region;
 		engine->fb.set_tile_region	= nv40_fb_set_tile_region;
 		engine->fb.free_tile_region	= nv30_fb_free_tile_region;
-		engine->graph.init		= nouveau_stub_init;
-		engine->graph.takedown		= nouveau_stub_takedown;
-		engine->graph.fifo_access	= nvc0_graph_fifo_access;
-		engine->graph.channel		= nvc0_graph_channel;
 		engine->fifo.channels		= 32;
 		engine->fifo.init		= nv40_fifo_init;
 		engine->fifo.takedown		= nv04_fifo_fini;
@@ -334,10 +314,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 		engine->timer.takedown		= nv04_timer_takedown;
 		engine->fb.init			= nv50_fb_init;
 		engine->fb.takedown		= nv50_fb_takedown;
-		engine->graph.init		= nouveau_stub_init;
-		engine->graph.takedown		= nouveau_stub_takedown;
-		engine->graph.fifo_access	= nvc0_graph_fifo_access;
-		engine->graph.channel		= nvc0_graph_channel;
 		engine->fifo.channels		= 128;
 		engine->fifo.init		= nv50_fifo_init;
 		engine->fifo.takedown		= nv50_fifo_takedown;
@@ -411,8 +387,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
 		engine->timer.takedown		= nv04_timer_takedown;
 		engine->fb.init			= nvc0_fb_init;
 		engine->fb.takedown		= nvc0_fb_takedown;
-		engine->graph.fifo_access	= nvc0_graph_fifo_access;
-		engine->graph.channel		= nvc0_graph_channel;
 		engine->fifo.channels		= 128;
 		engine->fifo.init		= nvc0_fifo_init;
 		engine->fifo.takedown		= nvc0_fifo_takedown;
@@ -624,9 +598,7 @@ nouveau_card_init(struct drm_device *dev)
 		break;
 	}
 
-	if (nouveau_noaccel)
+	if (!nouveau_noaccel) {
-		engine->graph.accel_blocked = true;
-	else {
 		for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 			if (dev_priv->eng[e]) {
 				ret = dev_priv->eng[e]->init(dev, e);
@@ -635,15 +607,10 @@ nouveau_card_init(struct drm_device *dev)
 			}
 		}
 
-		/* PGRAPH */
-		ret = engine->graph.init(dev);
-		if (ret)
-			goto out_engine;
-
 		/* PFIFO */
 		ret = engine->fifo.init(dev);
 		if (ret)
-			goto out_graph;
+			goto out_engine;
 	}
 
 	ret = engine->display.create(dev);
@@ -660,7 +627,7 @@ nouveau_card_init(struct drm_device *dev)
 
 	/* what about PVIDEO/PCRTC/PRAMDAC etc? */
 
-	if (!engine->graph.accel_blocked) {
+	if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 		ret = nouveau_fence_init(dev);
 		if (ret)
 			goto out_irq;
@@ -684,9 +651,6 @@ out_vblank:
 out_fifo:
 	if (!nouveau_noaccel)
 		engine->fifo.takedown(dev);
-out_graph:
-	if (!nouveau_noaccel)
-		engine->graph.takedown(dev);
 out_engine:
 	if (!nouveau_noaccel) {
 		for (e = e - 1; e >= 0; e--) {
@@ -728,14 +692,13 @@ static void nouveau_card_takedown(struct drm_device *dev)
 	struct nouveau_engine *engine = &dev_priv->engine;
 	int e;
 
-	if (!engine->graph.accel_blocked) {
+	if (dev_priv->channel) {
 		nouveau_fence_fini(dev);
 		nouveau_channel_put_unlocked(&dev_priv->channel);
 	}
 
 	if (!nouveau_noaccel) {
 		engine->fifo.takedown(dev);
-		engine->graph.takedown(dev);
 		for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 			if (dev_priv->eng[e]) {
 				dev_priv->eng[e]->fini(dev, e);

drivers/gpu/drm/nouveau/nv20_graph.c

@@ -752,8 +752,7 @@ nv20_graph_create(struct drm_device *dev)
 			pgraph->grctx_user = 0x0000;
 			break;
 		default:
-			NV_ERROR(dev, "unknown nv20, disabling acceleration\n");
+			NV_ERROR(dev, "PGRAPH: unknown chipset\n");
-			dev_priv->engine.graph.accel_blocked = true;
 			return 0;
 		}
 	} else {
@@ -774,8 +773,7 @@ nv20_graph_create(struct drm_device *dev)
 			pgraph->grctx_size = NV35_36_GRCTX_SIZE;
 			break;
 		default:
-			NV_ERROR(dev, "unknown nv30, disabling acceleration\n");
+			NV_ERROR(dev, "PGRAPH: unknown chipset\n");
-			dev_priv->engine.graph.accel_blocked = true;
 			return 0;
 		}
 	}

drivers/gpu/drm/nouveau/nv50_graph.c

@@ -1053,7 +1053,6 @@ nv50_graph_create(struct drm_device *dev)
 	ret = nv50_grctx_init(&ctx);
 	if (ret) {
 		NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");
-		dev_priv->engine.graph.accel_blocked = true;
 		kfree(pgraph);
 		return 0;
 	}

drivers/gpu/drm/nouveau/nvc0_graph.c

@@ -30,17 +30,6 @@
 #include "nouveau_mm.h"
 #include "nvc0_graph.h"
 
-void
-nvc0_graph_fifo_access(struct drm_device *dev, bool enabled)
-{
-}
-
-struct nouveau_channel *
-nvc0_graph_channel(struct drm_device *dev)
-{
-	return NULL;
-}
-
 static int
 nvc0_graph_load_context(struct nouveau_channel *chan)
 {
@@ -508,23 +497,8 @@ nvc0_graph_init_ctxctl(struct drm_device *dev)
 static int
 nvc0_graph_init(struct drm_device *dev, int engine)
 {
-	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	int ret;
 
-	dev_priv->engine.graph.accel_blocked = true;
-
-	switch (dev_priv->chipset) {
-	case 0xc0:
-	case 0xc3:
-	case 0xc4:
-		break;
-	default:
-		NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
-		if (nouveau_noaccel != 0)
-			return 0;
-		break;
-	}
-
 	nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
 	nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
 
@@ -551,8 +525,9 @@ nvc0_graph_init(struct drm_device *dev, int engine)
 	nv_wr32(dev, 0x400054, 0x34ce3464);
 
 	ret = nvc0_graph_init_ctxctl(dev);
-	if (ret == 0)
+	if (ret)
-		dev_priv->engine.graph.accel_blocked = false;
+		return ret;
+
 	return 0;
 }
 
@@ -686,6 +661,16 @@ nvc0_graph_create(struct drm_device *dev)
 	struct nvc0_graph_priv *priv;
 	int ret, gpc, i;
 
+	switch (dev_priv->chipset) {
+	case 0xc0:
+	case 0xc3:
+	case 0xc4:
+		break;
+	default:
+		NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
+		return 0;
+	}
+
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;