ASoC: Intel: cnl: Add cnl dsp functions and registers
This adds Cannonlake specific registers and support for CNL dsp related library functions for programming the registers to power up/down dsp cores, set/unset reset states for each core, enable/disable ipc interrupts and few wrappers to be called from elsewhere. Signed-off-by: Guneshwor Singh <guneshwor.o.singh@intel.com> Acked-By: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Guneshwor Singh
Mark Brown
Родитель
4147a6e59a
Коммит
a838dcc286
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/*
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* cnl-sst-dsp.c - CNL SST library generic function
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*
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* Copyright (C) 2016-17, Intel Corporation.
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* Author: Guneshwor Singh <guneshwor.o.singh@intel.com>
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*
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* Modified from:
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* SKL SST library generic function
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* Copyright (C) 2014-15, Intel Corporation.
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*/
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#include <linux/device.h>
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#include "../common/sst-dsp.h"
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#include "../common/sst-ipc.h"
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#include "../common/sst-dsp-priv.h"
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#include "cnl-sst-dsp.h"
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/* various timeout values */
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#define CNL_DSP_PU_TO 50
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#define CNL_DSP_PD_TO 50
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#define CNL_DSP_RESET_TO 50
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static int
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cnl_dsp_core_set_reset_state(struct sst_dsp *ctx, unsigned int core_mask)
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{
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/* update bits */
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sst_dsp_shim_update_bits_unlocked(ctx,
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CNL_ADSP_REG_ADSPCS, CNL_ADSPCS_CRST(core_mask),
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CNL_ADSPCS_CRST(core_mask));
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/* poll with timeout to check if operation successful */
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return sst_dsp_register_poll(ctx,
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CNL_ADSP_REG_ADSPCS,
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CNL_ADSPCS_CRST(core_mask),
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CNL_ADSPCS_CRST(core_mask),
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CNL_DSP_RESET_TO,
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"Set reset");
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}
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static int
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cnl_dsp_core_unset_reset_state(struct sst_dsp *ctx, unsigned int core_mask)
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{
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/* update bits */
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sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
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CNL_ADSPCS_CRST(core_mask), 0);
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/* poll with timeout to check if operation successful */
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return sst_dsp_register_poll(ctx,
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CNL_ADSP_REG_ADSPCS,
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CNL_ADSPCS_CRST(core_mask),
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0,
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CNL_DSP_RESET_TO,
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"Unset reset");
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}
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static bool is_cnl_dsp_core_enable(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int val;
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bool is_enable;
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val = sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPCS);
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is_enable = (val & CNL_ADSPCS_CPA(core_mask)) &&
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(val & CNL_ADSPCS_SPA(core_mask)) &&
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!(val & CNL_ADSPCS_CRST(core_mask)) &&
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!(val & CNL_ADSPCS_CSTALL(core_mask));
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dev_dbg(ctx->dev, "DSP core(s) enabled? %d: core_mask %#x\n",
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is_enable, core_mask);
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return is_enable;
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}
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static int cnl_dsp_reset_core(struct sst_dsp *ctx, unsigned int core_mask)
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{
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/* stall core */
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sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
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CNL_ADSPCS_CSTALL(core_mask),
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CNL_ADSPCS_CSTALL(core_mask));
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/* set reset state */
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return cnl_dsp_core_set_reset_state(ctx, core_mask);
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}
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static int cnl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int ret;
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/* unset reset state */
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ret = cnl_dsp_core_unset_reset_state(ctx, core_mask);
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if (ret < 0)
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return ret;
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/* run core */
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sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
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CNL_ADSPCS_CSTALL(core_mask), 0);
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if (!is_cnl_dsp_core_enable(ctx, core_mask)) {
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cnl_dsp_reset_core(ctx, core_mask);
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dev_err(ctx->dev, "DSP core mask %#x enable failed\n",
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core_mask);
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ret = -EIO;
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}
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return ret;
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}
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static int cnl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask)
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{
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/* update bits */
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sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
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CNL_ADSPCS_SPA(core_mask),
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CNL_ADSPCS_SPA(core_mask));
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/* poll with timeout to check if operation successful */
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return sst_dsp_register_poll(ctx, CNL_ADSP_REG_ADSPCS,
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CNL_ADSPCS_CPA(core_mask),
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CNL_ADSPCS_CPA(core_mask),
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CNL_DSP_PU_TO,
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"Power up");
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}
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static int cnl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask)
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{
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/* update bits */
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sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS,
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CNL_ADSPCS_SPA(core_mask), 0);
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/* poll with timeout to check if operation successful */
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return sst_dsp_register_poll(ctx,
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CNL_ADSP_REG_ADSPCS,
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CNL_ADSPCS_CPA(core_mask),
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0,
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CNL_DSP_PD_TO,
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"Power down");
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}
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int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int ret;
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/* power up */
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ret = cnl_dsp_core_power_up(ctx, core_mask);
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if (ret < 0) {
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dev_dbg(ctx->dev, "DSP core mask %#x power up failed",
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core_mask);
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return ret;
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}
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return cnl_dsp_start_core(ctx, core_mask);
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}
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int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask)
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{
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int ret;
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ret = cnl_dsp_reset_core(ctx, core_mask);
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if (ret < 0) {
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dev_err(ctx->dev, "DSP core mask %#x reset failed\n",
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core_mask);
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return ret;
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}
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/* power down core*/
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ret = cnl_dsp_core_power_down(ctx, core_mask);
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if (ret < 0) {
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dev_err(ctx->dev, "DSP core mask %#x power down failed\n",
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core_mask);
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return ret;
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}
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if (is_cnl_dsp_core_enable(ctx, core_mask)) {
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dev_err(ctx->dev, "DSP core mask %#x disable failed\n",
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core_mask);
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ret = -EIO;
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}
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return ret;
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}
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irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id)
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{
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struct sst_dsp *ctx = dev_id;
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u32 val;
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irqreturn_t ret = IRQ_NONE;
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spin_lock(&ctx->spinlock);
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val = sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPIS);
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ctx->intr_status = val;
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if (val == 0xffffffff) {
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spin_unlock(&ctx->spinlock);
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return IRQ_NONE;
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}
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if (val & CNL_ADSPIS_IPC) {
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cnl_ipc_int_disable(ctx);
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ret = IRQ_WAKE_THREAD;
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}
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spin_unlock(&ctx->spinlock);
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return ret;
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}
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void cnl_dsp_free(struct sst_dsp *dsp)
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{
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cnl_ipc_int_disable(dsp);
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free_irq(dsp->irq, dsp);
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cnl_ipc_op_int_disable(dsp);
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cnl_dsp_disable_core(dsp, SKL_DSP_CORE0_MASK);
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}
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EXPORT_SYMBOL_GPL(cnl_dsp_free);
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void cnl_ipc_int_enable(struct sst_dsp *ctx)
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{
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sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_ADSPIC,
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CNL_ADSPIC_IPC, CNL_ADSPIC_IPC);
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}
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void cnl_ipc_int_disable(struct sst_dsp *ctx)
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{
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sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPIC,
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CNL_ADSPIC_IPC, 0);
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}
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void cnl_ipc_op_int_enable(struct sst_dsp *ctx)
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{
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/* enable IPC DONE interrupt */
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sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
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CNL_ADSP_REG_HIPCCTL_DONE,
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CNL_ADSP_REG_HIPCCTL_DONE);
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/* enable IPC BUSY interrupt */
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sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
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CNL_ADSP_REG_HIPCCTL_BUSY,
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CNL_ADSP_REG_HIPCCTL_BUSY);
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}
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void cnl_ipc_op_int_disable(struct sst_dsp *ctx)
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{
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/* disable IPC DONE interrupt */
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sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
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CNL_ADSP_REG_HIPCCTL_DONE, 0);
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/* disable IPC BUSY interrupt */
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sst_dsp_shim_update_bits(ctx, CNL_ADSP_REG_HIPCCTL,
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CNL_ADSP_REG_HIPCCTL_BUSY, 0);
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}
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bool cnl_ipc_int_status(struct sst_dsp *ctx)
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{
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return sst_dsp_shim_read_unlocked(ctx, CNL_ADSP_REG_ADSPIS) &
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CNL_ADSPIS_IPC;
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}
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void cnl_ipc_free(struct sst_generic_ipc *ipc)
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{
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cnl_ipc_op_int_disable(ipc->dsp);
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sst_ipc_fini(ipc);
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}
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/*
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* Cannonlake SST DSP Support
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*
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* Copyright (C) 2016-17, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef __CNL_SST_DSP_H__
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#define __CNL_SST_DSP_H__
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struct sst_dsp;
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struct skl_sst;
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struct sst_dsp_device;
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struct sst_generic_ipc;
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/* Intel HD Audio General DSP Registers */
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#define CNL_ADSP_GEN_BASE 0x0
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#define CNL_ADSP_REG_ADSPCS (CNL_ADSP_GEN_BASE + 0x04)
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#define CNL_ADSP_REG_ADSPIC (CNL_ADSP_GEN_BASE + 0x08)
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#define CNL_ADSP_REG_ADSPIS (CNL_ADSP_GEN_BASE + 0x0c)
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/* Intel HD Audio Inter-Processor Communication Registers */
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#define CNL_ADSP_IPC_BASE 0xc0
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#define CNL_ADSP_REG_HIPCTDR (CNL_ADSP_IPC_BASE + 0x00)
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#define CNL_ADSP_REG_HIPCTDA (CNL_ADSP_IPC_BASE + 0x04)
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#define CNL_ADSP_REG_HIPCTDD (CNL_ADSP_IPC_BASE + 0x08)
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#define CNL_ADSP_REG_HIPCIDR (CNL_ADSP_IPC_BASE + 0x10)
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#define CNL_ADSP_REG_HIPCIDA (CNL_ADSP_IPC_BASE + 0x14)
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#define CNL_ADSP_REG_HIPCIDD (CNL_ADSP_IPC_BASE + 0x18)
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#define CNL_ADSP_REG_HIPCCTL (CNL_ADSP_IPC_BASE + 0x28)
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/* HIPCTDR */
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#define CNL_ADSP_REG_HIPCTDR_BUSY BIT(31)
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/* HIPCTDA */
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#define CNL_ADSP_REG_HIPCTDA_DONE BIT(31)
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/* HIPCIDR */
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#define CNL_ADSP_REG_HIPCIDR_BUSY BIT(31)
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/* HIPCIDA */
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#define CNL_ADSP_REG_HIPCIDA_DONE BIT(31)
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/* CNL HIPCCTL */
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#define CNL_ADSP_REG_HIPCCTL_DONE BIT(1)
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#define CNL_ADSP_REG_HIPCCTL_BUSY BIT(0)
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/* CNL HIPCT */
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#define CNL_ADSP_REG_HIPCT_BUSY BIT(31)
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/* Intel HD Audio SRAM Window 1 */
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#define CNL_ADSP_SRAM1_BASE 0xa0000
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#define CNL_ADSP_MMIO_LEN 0x10000
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#define CNL_ADSP_W0_STAT_SZ 0x1000
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#define CNL_ADSP_W0_UP_SZ 0x1000
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#define CNL_ADSP_W1_SZ 0x1000
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#define CNL_FW_STS_MASK 0xf
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#define CNL_ADSPIC_IPC 0x1
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#define CNL_ADSPIS_IPC 0x1
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#define CNL_DSP_CORES 4
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#define CNL_DSP_CORES_MASK ((1 << CNL_DSP_CORES) - 1)
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/* core reset - asserted high */
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#define CNL_ADSPCS_CRST_SHIFT 0
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#define CNL_ADSPCS_CRST(x) (x << CNL_ADSPCS_CRST_SHIFT)
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/* core run/stall - when set to 1 core is stalled */
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#define CNL_ADSPCS_CSTALL_SHIFT 8
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#define CNL_ADSPCS_CSTALL(x) (x << CNL_ADSPCS_CSTALL_SHIFT)
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/* set power active - when set to 1 turn core on */
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#define CNL_ADSPCS_SPA_SHIFT 16
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#define CNL_ADSPCS_SPA(x) (x << CNL_ADSPCS_SPA_SHIFT)
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/* current power active - power status of cores, set by hardware */
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#define CNL_ADSPCS_CPA_SHIFT 24
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#define CNL_ADSPCS_CPA(x) (x << CNL_ADSPCS_CPA_SHIFT)
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int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core);
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int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core);
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irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id);
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void cnl_dsp_free(struct sst_dsp *dsp);
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void cnl_ipc_int_enable(struct sst_dsp *ctx);
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void cnl_ipc_int_disable(struct sst_dsp *ctx);
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void cnl_ipc_op_int_enable(struct sst_dsp *ctx);
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void cnl_ipc_op_int_disable(struct sst_dsp *ctx);
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bool cnl_ipc_int_status(struct sst_dsp *ctx);
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void cnl_ipc_free(struct sst_generic_ipc *ipc);
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#endif /*__CNL_SST_DSP_H__*/
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