ARM: AM33XX: cm: Add bit-field width values
The new common clk framework includes basic definitions for mux and divider clocks. These definitions depend on shift and width values instead of the pre-computed masks that the OMAP/AM33XX clk framework has traditionally used when accessing the register to control the mux or divisor. To ease this transition the masks are left intact and the width field is simply added alongside the shift and mask data. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Mike Turquette <mturquette@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Vaibhav Hiremath
Paul Walmsley
Родитель
f19a302247
Коммит
a86c0b9867
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@ -25,263 +25,328 @@
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* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
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*/
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#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
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#define AM33XX_AUTO_DPLL_MODE_WIDTH 3
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#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
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#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
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#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
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/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
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/* Used by CM_PER_CPSW_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
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/* Used by CM_PER_L4HS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
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/* Used by CM_PER_L4HS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
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#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
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/* Used by CM_PER_L4HS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
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#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
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#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
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/* Used by CM_CEFUSE_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
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#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
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/* Used by CM_L3_AON_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
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/* Used by CM_L3_AON_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
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#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1
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#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
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/* Used by CM_GFX_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
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#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
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/* Used by CM_GFX_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
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#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
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#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
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#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
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#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
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#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
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#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
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#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
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#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
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/* Used by CM_PER_PRUSS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
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#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
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/* Used by CM_PER_PRUSS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
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/* Used by CM_PER_PRUSS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
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#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
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/* Used by CM_PER_L3S_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
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/* Used by CM_L3_AON_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
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/* Used by CM_PER_L4FW_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
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/* Used by CM_PER_L4HS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
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/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
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#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
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/* Used by CM_CEFUSE_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
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/* Used by CM_RTC_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
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#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
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/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
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#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
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/* Used by CM_PER_LCDC_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
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/* Used by CM_PER_LCDC_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
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#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
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#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
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/* Used by CM_PER_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
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/* Used by CM_MPU_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
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#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
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/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
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/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
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#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
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/* Used by CM_RTC_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
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#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
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#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
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#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
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#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
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#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
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#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
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#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
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#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
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#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
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#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
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#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
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#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
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/* Used by CM_PER_L4LS_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
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#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
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#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
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/* Used by CM_WKUP_CLKSTCTRL */
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#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
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#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1
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#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
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/* Used by CLKSEL_GFX_FCLK */
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#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
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#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1
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#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
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/* Used by CM_CLKOUT_CTRL */
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#define AM33XX_CLKOUT2DIV_SHIFT 3
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#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3)
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#define AM33XX_CLKOUT2DIV_WIDTH 3
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#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)
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/* Used by CM_CLKOUT_CTRL */
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#define AM33XX_CLKOUT2EN_SHIFT 7
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#define AM33XX_CLKOUT2EN_WIDTH 1
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#define AM33XX_CLKOUT2EN_MASK (1 << 7)
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/* Used by CM_CLKOUT_CTRL */
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#define AM33XX_CLKOUT2SOURCE_SHIFT 0
|
||||
#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0)
|
||||
#define AM33XX_CLKOUT2SOURCE_WIDTH 3
|
||||
#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
|
||||
|
||||
/*
|
||||
* Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
|
||||
|
|
@ -289,6 +354,7 @@
|
|||
* CLKSEL_TIMER7_CLK
|
||||
*/
|
||||
#define AM33XX_CLKSEL_SHIFT 0
|
||||
#define AM33XX_CLKSEL_WIDTH 1
|
||||
#define AM33XX_CLKSEL_MASK (0x01 << 0)
|
||||
|
||||
/*
|
||||
|
|
@ -296,17 +362,21 @@
|
|||
* CM_CPTS_RFT_CLKSEL
|
||||
*/
|
||||
#define AM33XX_CLKSEL_0_0_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_0_WIDTH 1
|
||||
#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
|
||||
|
||||
#define AM33XX_CLKSEL_0_1_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_1_WIDTH 2
|
||||
#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
|
||||
|
||||
/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
|
||||
#define AM33XX_CLKSEL_0_2_SHIFT 0
|
||||
#define AM33XX_CLKSEL_0_2_WIDTH 3
|
||||
#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
|
||||
|
||||
/* Used by CLKSEL_GFX_FCLK */
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1
|
||||
#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
|
||||
|
||||
/*
|
||||
|
|
@ -318,6 +388,7 @@
|
|||
* CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
|
||||
*/
|
||||
#define AM33XX_CLKTRCTRL_SHIFT 0
|
||||
#define AM33XX_CLKTRCTRL_WIDTH 2
|
||||
#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
|
||||
|
||||
/*
|
||||
|
|
@ -326,34 +397,42 @@
|
|||
* CM_SSC_DELTAMSTEP_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DELTAMSTEP_SHIFT 0
|
||||
#define AM33XX_DELTAMSTEP_MASK (0x19 << 0)
|
||||
#define AM33XX_DELTAMSTEP_WIDTH 20
|
||||
#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0)
|
||||
|
||||
/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1
|
||||
#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0)
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7
|
||||
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
|
||||
|
||||
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
|
||||
|
||||
/*
|
||||
|
|
@ -361,6 +440,7 @@
|
|||
* CM_DIV_M2_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
|
|
@ -368,19 +448,22 @@
|
|||
* CM_CLKSEL_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_DIV_SHIFT 0
|
||||
#define AM33XX_DPLL_DIV_WIDTH 7
|
||||
#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
|
||||
|
||||
#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
|
||||
|
||||
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_DIV_0_7_SHIFT 0
|
||||
#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0)
|
||||
#define AM33XX_DPLL_DIV_0_7_WIDTH 8
|
||||
#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1
|
||||
#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
|
||||
|
||||
/*
|
||||
|
|
@ -388,6 +471,7 @@
|
|||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_EN_SHIFT 0
|
||||
#define AM33XX_DPLL_EN_WIDTH 3
|
||||
#define AM33XX_DPLL_EN_MASK (0x7 << 0)
|
||||
|
||||
/*
|
||||
|
|
@ -395,6 +479,7 @@
|
|||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
|
||||
#define AM33XX_DPLL_LPMODE_EN_WIDTH 1
|
||||
#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
|
||||
|
||||
/*
|
||||
|
|
@ -402,10 +487,12 @@
|
|||
* CM_CLKSEL_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_MULT_SHIFT 8
|
||||
#define AM33XX_DPLL_MULT_WIDTH 11
|
||||
#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
|
||||
|
||||
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
|
||||
#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12
|
||||
#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
|
||||
|
||||
/*
|
||||
|
|
@ -413,17 +500,20 @@
|
|||
* CM_CLKMODE_DPLL_MPU
|
||||
*/
|
||||
#define AM33XX_DPLL_REGM4XEN_SHIFT 11
|
||||
#define AM33XX_DPLL_REGM4XEN_WIDTH 1
|
||||
#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
|
||||
|
||||
/* Used by CM_CLKSEL_DPLL_PERIPH */
|
||||
#define AM33XX_DPLL_SD_DIV_SHIFT 24
|
||||
#define AM33XX_DPLL_SD_DIV_MASK (24, 31)
|
||||
#define AM33XX_DPLL_SD_DIV_WIDTH 8
|
||||
#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24)
|
||||
|
||||
/*
|
||||
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
|
||||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_ACK_SHIFT 13
|
||||
#define AM33XX_DPLL_SSC_ACK_WIDTH 1
|
||||
#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
|
||||
|
||||
/*
|
||||
|
|
@ -431,6 +521,7 @@
|
|||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1
|
||||
#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
|
||||
|
||||
/*
|
||||
|
|
@ -438,54 +529,67 @@
|
|||
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_DPLL_SSC_EN_SHIFT 12
|
||||
#define AM33XX_DPLL_SSC_EN_WIDTH 1
|
||||
#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0)
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1
|
||||
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
|
||||
|
||||
/*
|
||||
|
|
@ -522,11 +626,12 @@
|
|||
* CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_IDLEST_SHIFT 16
|
||||
#define AM33XX_IDLEST_WIDTH 2
|
||||
#define AM33XX_IDLEST_MASK (0x3 << 16)
|
||||
#define AM33XX_IDLEST_VAL 0x3
|
||||
|
||||
/* Used by CM_MAC_CLKSEL */
|
||||
#define AM33XX_MII_CLK_SEL_SHIFT 2
|
||||
#define AM33XX_MII_CLK_SEL_WIDTH 1
|
||||
#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
|
||||
|
||||
/*
|
||||
|
|
@ -535,7 +640,8 @@
|
|||
* CM_SSC_MODFREQDIV_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8)
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3
|
||||
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
|
||||
|
||||
/*
|
||||
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
|
||||
|
|
@ -543,7 +649,8 @@
|
|||
* CM_SSC_MODFREQDIV_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0)
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7
|
||||
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
|
||||
|
||||
/*
|
||||
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
|
||||
|
|
@ -580,42 +687,52 @@
|
|||
* CM_CEFUSE_CEFUSE_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_MODULEMODE_SHIFT 0
|
||||
#define AM33XX_MODULEMODE_WIDTH 2
|
||||
#define AM33XX_MODULEMODE_MASK (0x3 << 0)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1
|
||||
#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
|
||||
|
||||
/* Used by CM_WKUP_GPIO0_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO1_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO2_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO3_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO4_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO5_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_PER_GPIO6_CLKCTRL */
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1
|
||||
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
|
||||
|
||||
/*
|
||||
|
|
@ -627,25 +744,30 @@
|
|||
* CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
|
||||
*/
|
||||
#define AM33XX_STBYST_SHIFT 18
|
||||
#define AM33XX_STBYST_WIDTH 1
|
||||
#define AM33XX_STBYST_MASK (1 << 18)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27)
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
|
||||
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
|
||||
#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22)
|
||||
#define AM33XX_STM_PMD_CLKSEL_WIDTH 2
|
||||
#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)
|
||||
|
||||
/*
|
||||
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
|
||||
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
|
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*/
|
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#define AM33XX_ST_DPLL_CLK_SHIFT 0
|
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#define AM33XX_ST_DPLL_CLK_WIDTH 1
|
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#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
|
||||
|
||||
/* Used by CM_CLKDCOLDO_DPLL_PER */
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#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
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#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1
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#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
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|
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/*
|
||||
|
|
@ -653,18 +775,22 @@
|
|||
* CM_DIV_M2_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
|
||||
#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1
|
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#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
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||||
|
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/* Used by CM_DIV_M4_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
|
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#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M5_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
|
||||
|
||||
/* Used by CM_DIV_M6_DPLL_CORE */
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1
|
||||
#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
|
||||
|
||||
/*
|
||||
|
|
@ -672,16 +798,20 @@
|
|||
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
|
||||
*/
|
||||
#define AM33XX_ST_MN_BYPASS_SHIFT 8
|
||||
#define AM33XX_ST_MN_BYPASS_WIDTH 1
|
||||
#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24)
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
|
||||
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)
|
||||
|
||||
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
|
||||
#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
|
||||
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20)
|
||||
#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
|
||||
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)
|
||||
|
||||
/* Used by CONTROL_SEC_CLK_CTRL */
|
||||
#define AM33XX_TIMER0_CLKSEL_WIDTH 2
|
||||
#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@
|
|||
|
||||
/* AM33XX CONTROL_STATUS bitfields (partial) */
|
||||
#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
|
||||
#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
|
||||
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
|
||||
|
||||
/* CONTROL OMAP STATUS register to identify OMAP3 features */
|
||||
|
|
|
|||
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