memory: tegra: Squash tegra20-mc into common tegra-mc driver
Tegra30+ has some minor differences in registers / bits layout compared to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver in a preparation for the upcoming MC hot reset controls implementation, avoiding code duplication. Note that this currently doesn't report the value of MC_GART_ERROR_REQ because it is located within the GART register area and cannot be safely accessed from the MC driver (this happens to work only by accident). The proper solution is to integrate the GART driver with the MC driver, much like is done for the Tegra SMMU, but that is an invasive change and will be part of a separate patch series. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko
Thierry Reding
Родитель
85dce8918f
Коммит
a8d502fd33
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@ -104,16 +104,6 @@ config MVEBU_DEVBUS
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Armada 370 and Armada XP. This controller allows to handle flash
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devices such as NOR, NAND, SRAM, and FPGA.
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config TEGRA20_MC
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bool "Tegra20 Memory Controller(MC) driver"
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default y
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depends on ARCH_TEGRA_2x_SOC
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help
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This driver is for the Memory Controller(MC) module available
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in Tegra20 SoCs, mainly for a address translation fault
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analysis, especially for IOMMU/GART(Graphics Address
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Relocation Table) module.
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config FSL_CORENET_CF
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tristate "Freescale CoreNet Error Reporting"
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depends on FSL_SOC_BOOKE
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@ -16,7 +16,6 @@ obj-$(CONFIG_OMAP_GPMC) += omap-gpmc.o
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obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o
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obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
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obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
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obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
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obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o
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obj-$(CONFIG_MTK_SMI) += mtk-smi.o
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obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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tegra-mc-y := mc.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
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@ -37,6 +37,9 @@
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#define MC_ERR_ADR 0x0c
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#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
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#define MC_SECURITY_VIOLATION_STATUS 0x74
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
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@ -46,6 +49,9 @@
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#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
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static const struct of_device_id tegra_mc_of_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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{ .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
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#endif
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@ -221,6 +227,7 @@ static int tegra_mc_setup_timings(struct tegra_mc *mc)
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static const char *const status_names[32] = {
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[ 1] = "External interrupt",
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[ 6] = "EMEM address decode error",
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[ 7] = "GART page fault",
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[ 8] = "Security violation",
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[ 9] = "EMEM arbitration error",
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[10] = "Page fault",
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@ -334,11 +341,78 @@ static irqreturn_t tegra_mc_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
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{
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struct tegra_mc *mc = data;
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unsigned long status;
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unsigned int bit;
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/* mask all interrupts to avoid flooding */
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status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
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if (!status)
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return IRQ_NONE;
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for_each_set_bit(bit, &status, 32) {
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const char *direction = "read", *secure = "";
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const char *error = status_names[bit];
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const char *client, *desc;
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phys_addr_t addr;
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u32 value, reg;
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u8 id, type;
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switch (BIT(bit)) {
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case MC_INT_DECERR_EMEM:
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reg = MC_DECERR_EMEM_OTHERS_STATUS;
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value = mc_readl(mc, reg);
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id = value & mc->soc->client_id_mask;
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desc = error_names[2];
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if (value & BIT(31))
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direction = "write";
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break;
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case MC_INT_INVALID_GART_PAGE:
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dev_err_ratelimited(mc->dev, "%s\n", error);
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continue;
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case MC_INT_SECURITY_VIOLATION:
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reg = MC_SECURITY_VIOLATION_STATUS;
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value = mc_readl(mc, reg);
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id = value & mc->soc->client_id_mask;
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type = (value & BIT(30)) ? 4 : 3;
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desc = error_names[type];
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secure = "secure ";
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if (value & BIT(31))
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direction = "write";
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break;
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default:
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continue;
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}
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client = mc->soc->clients[id].name;
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addr = mc_readl(mc, reg + sizeof(u32));
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dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
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client, secure, direction, &addr, error,
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desc);
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}
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/* clear interrupts */
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mc_writel(mc, status, MC_INTSTATUS);
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return IRQ_HANDLED;
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}
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static int tegra_mc_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct resource *res;
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struct tegra_mc *mc;
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void *isr;
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int err;
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match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
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@ -361,18 +435,32 @@ static int tegra_mc_probe(struct platform_device *pdev)
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if (IS_ERR(mc->regs))
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return PTR_ERR(mc->regs);
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mc->clk = devm_clk_get(&pdev->dev, "mc");
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if (IS_ERR(mc->clk)) {
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dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
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PTR_ERR(mc->clk));
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return PTR_ERR(mc->clk);
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}
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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if (mc->soc == &tegra20_mc_soc) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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mc->regs2 = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mc->regs2))
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return PTR_ERR(mc->regs2);
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err = tegra_mc_setup_latency_allowance(mc);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
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err);
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return err;
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isr = tegra20_mc_irq;
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} else
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#endif
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{
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mc->clk = devm_clk_get(&pdev->dev, "mc");
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if (IS_ERR(mc->clk)) {
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dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
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PTR_ERR(mc->clk));
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return PTR_ERR(mc->clk);
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}
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err = tegra_mc_setup_latency_allowance(mc);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
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err);
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return err;
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}
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isr = tegra_mc_irq;
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}
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err = tegra_mc_setup_timings(mc);
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@ -400,7 +488,7 @@ static int tegra_mc_probe(struct platform_device *pdev)
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mc_writel(mc, mc->soc->intmask, MC_INTMASK);
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err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED,
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err = devm_request_irq(&pdev->dev, mc->irq, isr, IRQF_SHARED,
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dev_name(&pdev->dev), mc);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
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@ -21,19 +21,30 @@
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#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
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#define MC_INT_ARBITRATION_EMEM (1 << 9)
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#define MC_INT_SECURITY_VIOLATION (1 << 8)
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#define MC_INT_INVALID_GART_PAGE (1 << 7)
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#define MC_INT_DECERR_EMEM (1 << 6)
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static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
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{
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if (mc->regs2 && offset >= 0x24)
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return readl(mc->regs2 + offset - 0x3c);
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return readl(mc->regs + offset);
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}
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static inline void mc_writel(struct tegra_mc *mc, u32 value,
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unsigned long offset)
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{
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if (mc->regs2 && offset >= 0x24)
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return writel(value, mc->regs2 + offset - 0x3c);
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writel(value, mc->regs + offset);
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}
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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extern const struct tegra_mc_soc tegra20_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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extern const struct tegra_mc_soc tegra30_mc_soc;
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#endif
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@ -0,0 +1,178 @@
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/*
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* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "mc.h"
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static const struct tegra_mc_client tegra20_mc_clients[] = {
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{
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.id = 0x00,
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.name = "display0a",
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}, {
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.id = 0x01,
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.name = "display0ab",
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}, {
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.id = 0x02,
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.name = "display0b",
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}, {
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.id = 0x03,
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.name = "display0bb",
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}, {
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.id = 0x04,
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.name = "display0c",
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}, {
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.id = 0x05,
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.name = "display0cb",
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}, {
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.id = 0x06,
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.name = "display1b",
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}, {
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.id = 0x07,
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.name = "display1bb",
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}, {
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.id = 0x08,
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.name = "eppup",
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}, {
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.id = 0x09,
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.name = "g2pr",
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}, {
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.id = 0x0a,
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.name = "g2sr",
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}, {
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.id = 0x0b,
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.name = "mpeunifbr",
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}, {
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.id = 0x0c,
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.name = "viruv",
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}, {
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.id = 0x0d,
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.name = "avpcarm7r",
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}, {
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.id = 0x0e,
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.name = "displayhc",
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}, {
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.id = 0x0f,
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.name = "displayhcb",
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}, {
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.id = 0x10,
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.name = "fdcdrd",
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}, {
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.id = 0x11,
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.name = "g2dr",
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}, {
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.id = 0x12,
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.name = "host1xdmar",
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}, {
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.id = 0x13,
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.name = "host1xr",
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}, {
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.id = 0x14,
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.name = "idxsrd",
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}, {
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.id = 0x15,
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.name = "mpcorer",
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}, {
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.id = 0x16,
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.name = "mpe_ipred",
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}, {
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.id = 0x17,
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.name = "mpeamemrd",
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}, {
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.id = 0x18,
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.name = "mpecsrd",
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}, {
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.id = 0x19,
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.name = "ppcsahbdmar",
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}, {
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.id = 0x1a,
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.name = "ppcsahbslvr",
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}, {
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.id = 0x1b,
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.name = "texsrd",
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}, {
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.id = 0x1c,
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.name = "vdebsevr",
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}, {
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.id = 0x1d,
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.name = "vdember",
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}, {
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.id = 0x1e,
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.name = "vdemcer",
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}, {
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.id = 0x1f,
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.name = "vdetper",
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}, {
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.id = 0x20,
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.name = "eppu",
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}, {
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.id = 0x21,
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.name = "eppv",
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}, {
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.id = 0x22,
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.name = "eppy",
|
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}, {
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.id = 0x23,
|
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.name = "mpeunifbw",
|
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}, {
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.id = 0x24,
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.name = "viwsb",
|
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}, {
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.id = 0x25,
|
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.name = "viwu",
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}, {
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.id = 0x26,
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.name = "viwv",
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}, {
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.id = 0x27,
|
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.name = "viwy",
|
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}, {
|
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.id = 0x28,
|
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.name = "g2dw",
|
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}, {
|
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.id = 0x29,
|
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.name = "avpcarm7w",
|
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}, {
|
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.id = 0x2a,
|
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.name = "fdcdwr",
|
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}, {
|
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.id = 0x2b,
|
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.name = "host1xw",
|
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}, {
|
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.id = 0x2c,
|
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.name = "ispw",
|
||||
}, {
|
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.id = 0x2d,
|
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.name = "mpcorew",
|
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}, {
|
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.id = 0x2e,
|
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.name = "mpecswr",
|
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}, {
|
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.id = 0x2f,
|
||||
.name = "ppcsahbdmaw",
|
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}, {
|
||||
.id = 0x30,
|
||||
.name = "ppcsahbslvw",
|
||||
}, {
|
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.id = 0x31,
|
||||
.name = "vdebsevw",
|
||||
}, {
|
||||
.id = 0x32,
|
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.name = "vdembew",
|
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}, {
|
||||
.id = 0x33,
|
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.name = "vdetpmw",
|
||||
},
|
||||
};
|
||||
|
||||
const struct tegra_mc_soc tegra20_mc_soc = {
|
||||
.clients = tegra20_mc_clients,
|
||||
.num_clients = ARRAY_SIZE(tegra20_mc_clients),
|
||||
.num_address_bits = 32,
|
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.client_id_mask = 0x3f,
|
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.intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
|
||||
MC_INT_DECERR_EMEM,
|
||||
};
|
||||
|
|
@ -1,254 +0,0 @@
|
|||
/*
|
||||
* Tegra20 Memory Controller
|
||||
*
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/ratelimit.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#define DRV_NAME "tegra20-mc"
|
||||
|
||||
#define MC_INTSTATUS 0x0
|
||||
#define MC_INTMASK 0x4
|
||||
|
||||
#define MC_INT_ERR_SHIFT 6
|
||||
#define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT)
|
||||
#define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT)
|
||||
#define MC_INT_INVALID_GART_PAGE BIT(MC_INT_ERR_SHIFT + 1)
|
||||
#define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2)
|
||||
#define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3)
|
||||
|
||||
#define MC_GART_ERROR_REQ 0x30
|
||||
#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
|
||||
#define MC_SECURITY_VIOLATION_STATUS 0x74
|
||||
|
||||
#define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */
|
||||
|
||||
#define MC_CLIENT_ID_MASK 0x3f
|
||||
|
||||
#define NUM_MC_REG_BANKS 2
|
||||
|
||||
struct tegra20_mc {
|
||||
void __iomem *regs[NUM_MC_REG_BANKS];
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
static inline u32 mc_readl(struct tegra20_mc *mc, u32 offs)
|
||||
{
|
||||
u32 val = 0;
|
||||
|
||||
if (offs < 0x24)
|
||||
val = readl(mc->regs[0] + offs);
|
||||
else if (offs < 0x400)
|
||||
val = readl(mc->regs[1] + offs - 0x3c);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void mc_writel(struct tegra20_mc *mc, u32 val, u32 offs)
|
||||
{
|
||||
if (offs < 0x24)
|
||||
writel(val, mc->regs[0] + offs);
|
||||
else if (offs < 0x400)
|
||||
writel(val, mc->regs[1] + offs - 0x3c);
|
||||
}
|
||||
|
||||
static const char * const tegra20_mc_client[] = {
|
||||
"cbr_display0a",
|
||||
"cbr_display0ab",
|
||||
"cbr_display0b",
|
||||
"cbr_display0bb",
|
||||
"cbr_display0c",
|
||||
"cbr_display0cb",
|
||||
"cbr_display1b",
|
||||
"cbr_display1bb",
|
||||
"cbr_eppup",
|
||||
"cbr_g2pr",
|
||||
"cbr_g2sr",
|
||||
"cbr_mpeunifbr",
|
||||
"cbr_viruv",
|
||||
"csr_avpcarm7r",
|
||||
"csr_displayhc",
|
||||
"csr_displayhcb",
|
||||
"csr_fdcdrd",
|
||||
"csr_g2dr",
|
||||
"csr_host1xdmar",
|
||||
"csr_host1xr",
|
||||
"csr_idxsrd",
|
||||
"csr_mpcorer",
|
||||
"csr_mpe_ipred",
|
||||
"csr_mpeamemrd",
|
||||
"csr_mpecsrd",
|
||||
"csr_ppcsahbdmar",
|
||||
"csr_ppcsahbslvr",
|
||||
"csr_texsrd",
|
||||
"csr_vdebsevr",
|
||||
"csr_vdember",
|
||||
"csr_vdemcer",
|
||||
"csr_vdetper",
|
||||
"cbw_eppu",
|
||||
"cbw_eppv",
|
||||
"cbw_eppy",
|
||||
"cbw_mpeunifbw",
|
||||
"cbw_viwsb",
|
||||
"cbw_viwu",
|
||||
"cbw_viwv",
|
||||
"cbw_viwy",
|
||||
"ccw_g2dw",
|
||||
"csw_avpcarm7w",
|
||||
"csw_fdcdwr",
|
||||
"csw_host1xw",
|
||||
"csw_ispw",
|
||||
"csw_mpcorew",
|
||||
"csw_mpecswr",
|
||||
"csw_ppcsahbdmaw",
|
||||
"csw_ppcsahbslvw",
|
||||
"csw_vdebsevw",
|
||||
"csw_vdembew",
|
||||
"csw_vdetpmw",
|
||||
};
|
||||
|
||||
static void tegra20_mc_decode(struct tegra20_mc *mc, int n)
|
||||
{
|
||||
u32 addr, req;
|
||||
const char *client = "Unknown";
|
||||
int idx, cid;
|
||||
const struct reg_info {
|
||||
u32 offset;
|
||||
u32 write_bit; /* 0=READ, 1=WRITE */
|
||||
int cid_shift;
|
||||
char *message;
|
||||
} reg[] = {
|
||||
{
|
||||
.offset = MC_DECERR_EMEM_OTHERS_STATUS,
|
||||
.write_bit = 31,
|
||||
.message = "MC_DECERR",
|
||||
},
|
||||
{
|
||||
.offset = MC_GART_ERROR_REQ,
|
||||
.cid_shift = 1,
|
||||
.message = "MC_GART_ERR",
|
||||
|
||||
},
|
||||
{
|
||||
.offset = MC_SECURITY_VIOLATION_STATUS,
|
||||
.write_bit = 31,
|
||||
.message = "MC_SECURITY_ERR",
|
||||
},
|
||||
};
|
||||
|
||||
idx = n - MC_INT_ERR_SHIFT;
|
||||
if ((idx < 0) || (idx >= ARRAY_SIZE(reg))) {
|
||||
dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n",
|
||||
BIT(n));
|
||||
return;
|
||||
}
|
||||
|
||||
req = mc_readl(mc, reg[idx].offset);
|
||||
cid = (req >> reg[idx].cid_shift) & MC_CLIENT_ID_MASK;
|
||||
if (cid < ARRAY_SIZE(tegra20_mc_client))
|
||||
client = tegra20_mc_client[cid];
|
||||
|
||||
addr = mc_readl(mc, reg[idx].offset + sizeof(u32));
|
||||
|
||||
dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s)\n",
|
||||
reg[idx].message, req, addr, client,
|
||||
(req & BIT(reg[idx].write_bit)) ? "write" : "read",
|
||||
(reg[idx].offset == MC_SECURITY_VIOLATION_STATUS) ?
|
||||
((req & SECURITY_VIOLATION_TYPE) ?
|
||||
"carveout" : "trustzone") : "");
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra20_mc_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra20-mc", },
|
||||
{},
|
||||
};
|
||||
|
||||
static irqreturn_t tegra20_mc_isr(int irq, void *data)
|
||||
{
|
||||
u32 stat, mask, bit;
|
||||
struct tegra20_mc *mc = data;
|
||||
|
||||
stat = mc_readl(mc, MC_INTSTATUS);
|
||||
mask = mc_readl(mc, MC_INTMASK);
|
||||
mask &= stat;
|
||||
if (!mask)
|
||||
return IRQ_NONE;
|
||||
while ((bit = ffs(mask)) != 0) {
|
||||
tegra20_mc_decode(mc, bit - 1);
|
||||
mask &= ~BIT(bit - 1);
|
||||
}
|
||||
|
||||
mc_writel(mc, stat, MC_INTSTATUS);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int tegra20_mc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *irq;
|
||||
struct tegra20_mc *mc;
|
||||
int i, err;
|
||||
u32 intmask;
|
||||
|
||||
mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
|
||||
if (!mc)
|
||||
return -ENOMEM;
|
||||
mc->dev = &pdev->dev;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
|
||||
struct resource *res;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
mc->regs[i] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mc->regs[i]))
|
||||
return PTR_ERR(mc->regs[i]);
|
||||
}
|
||||
|
||||
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!irq)
|
||||
return -ENODEV;
|
||||
err = devm_request_irq(&pdev->dev, irq->start, tegra20_mc_isr,
|
||||
IRQF_SHARED, dev_name(&pdev->dev), mc);
|
||||
if (err)
|
||||
return -ENODEV;
|
||||
|
||||
platform_set_drvdata(pdev, mc);
|
||||
|
||||
intmask = MC_INT_INVALID_GART_PAGE |
|
||||
MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION;
|
||||
mc_writel(mc, intmask, MC_INTMASK);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra20_mc_driver = {
|
||||
.probe = tegra20_mc_probe,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.of_match_table = tegra20_mc_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(tegra20_mc_driver);
|
||||
|
||||
MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
|
||||
MODULE_DESCRIPTION("Tegra20 MC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
|
|
@ -115,7 +115,7 @@ struct tegra_mc_soc {
|
|||
struct tegra_mc {
|
||||
struct device *dev;
|
||||
struct tegra_smmu *smmu;
|
||||
void __iomem *regs;
|
||||
void __iomem *regs, *regs2;
|
||||
struct clk *clk;
|
||||
int irq;
|
||||
|
||||
|
|
|
|||
Загрузка…
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