Clk:spear6xx:Fix: Rename clk ids within predefined limit
The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk
ids are exceeding this predefined limit.
This patch is intended to rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
ras_gen1_synth_gate_clk -> ras_syn1_gclk
pll3_48m -> pll3_
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Vipul Kumar Samar
Shiraz Hashim
Родитель
5cfc545f50
Коммит
a8f4bf0eb4
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@ -423,7 +423,7 @@ void __init spear6xx_map_io(void)
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static void __init spear6xx_timer_init(void)
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{
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char pclk_name[] = "pll3_48m_clk";
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char pclk_name[] = "pll3_clk";
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struct clk *gpt_clk, *pclk;
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spear6xx_clk_init();
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@ -97,13 +97,12 @@ static struct aux_rate_tbl aux_rtbl[] = {
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{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
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};
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static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", };
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static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
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};
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static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
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static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", };
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static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
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static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", };
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static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
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static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
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static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
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static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
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static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
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static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
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static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
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"pll2_clk", };
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@ -136,9 +135,9 @@ void __init spear6xx_clk_init(void)
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clk_register_clkdev(clk, NULL, "rtc-spear");
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/* clock derived from 30 MHz osc clk */
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clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
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clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
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48000000);
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clk_register_clkdev(clk, "pll3_48m_clk", NULL);
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clk_register_clkdev(clk, "pll3_clk", NULL);
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clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
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0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
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@ -146,9 +145,9 @@ void __init spear6xx_clk_init(void)
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clk_register_clkdev(clk, "vco1_clk", NULL);
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clk_register_clkdev(clk1, "pll1_clk", NULL);
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clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
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"osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
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ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
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clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
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0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
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&_lock, &clk1, NULL);
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clk_register_clkdev(clk, "vco2_clk", NULL);
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clk_register_clkdev(clk1, "pll2_clk", NULL);
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@ -165,111 +164,111 @@ void __init spear6xx_clk_init(void)
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HCLK_RATIO_MASK, 0, &_lock);
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clk_register_clkdev(clk, "ahb_clk", NULL);
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clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
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"pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
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ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
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clk_register_clkdev(clk, "uart_synth_clk", NULL);
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clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
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clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
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UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "uart_syn_clk", NULL);
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clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents,
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clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
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ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
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UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "uart_mux_clk", NULL);
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clk_register_clkdev(clk, "uart_mclk", NULL);
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clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0,
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PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock);
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clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
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UART0_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d0000000.serial");
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clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0,
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PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock);
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clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
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UART1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d0080000.serial");
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clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
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"pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
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ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
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clk_register_clkdev(clk, "firda_synth_clk", NULL);
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clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
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clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
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0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "firda_syn_clk", NULL);
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clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
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clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
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ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
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FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "firda_mux_clk", NULL);
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clk_register_clkdev(clk, "firda_mclk", NULL);
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clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
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clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
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PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "firda");
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clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk",
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"pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl,
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ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
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clk_register_clkdev(clk, "clcd_synth_clk", NULL);
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clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL);
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clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
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0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "clcd_syn_clk", NULL);
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clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents,
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clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
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ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
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CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "clcd_mux_clk", NULL);
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clk_register_clkdev(clk, "clcd_mclk", NULL);
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clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0,
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clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
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PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "clcd");
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/* gpt clocks */
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clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
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clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
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gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
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clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL);
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clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
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clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents,
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clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
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ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
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GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt0");
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clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents,
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clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
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ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
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GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
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clk_register_clkdev(clk, "gpt1_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
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clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
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PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt1");
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clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
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clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
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gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
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clk_register_clkdev(clk, "gpt2_synth_clk", NULL);
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clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
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clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
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clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
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ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
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GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
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clk_register_clkdev(clk, "gpt2_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
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clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
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PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt2");
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clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
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clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
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gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
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clk_register_clkdev(clk, "gpt3_synth_clk", NULL);
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clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
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clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents,
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clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
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ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
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GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
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clk_register_clkdev(clk, "gpt3_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
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clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
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PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt3");
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/* clock derived from pll3 clk */
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clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0,
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clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
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PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "usbh.0_clk");
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clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0,
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clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
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PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "usbh.1_clk");
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clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
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PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
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clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
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USBD_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "designware_udc");
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/* clock derived from ahb clk */
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@ -278,9 +277,8 @@ void __init spear6xx_clk_init(void)
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clk_register_clkdev(clk, "ahbmult2_clk", NULL);
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clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
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ARRAY_SIZE(ddr_parents),
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0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0,
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&_lock);
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ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
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MCTR_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "ddr_clk", NULL);
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clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
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