tools/perf: Add required memory barriers
To match patch bf378d341e ("perf: Fix perf ring buffer memory
ordering") change userspace to also adhere to the ordering outlined.
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Michael Neuling <mikey@neuling.org>
Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: james.hogan@imgtec.com
Cc: Vince Weaver <vince@deater.net>
Cc: Victor Kaplansky <VICTORK@il.ibm.com>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Anton Blanchard <anton@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Michael Ellerman <michael@ellerman.id.au>
Link: http://lkml.kernel.org/r/20131030104246.GH16117@laptop.programming.kicks-ass.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Peter Zijlstra
Ingo Molnar
Родитель
0a196848ca
Коммит
a94d342b9c
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@ -4,6 +4,8 @@
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#include <asm/unistd.h>
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#if defined(__i386__)
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#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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#define CPUINFO_PROC "model name"
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@ -13,6 +15,8 @@
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#endif
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#if defined(__x86_64__)
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#define mb() asm volatile("mfence" ::: "memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#define rmb() asm volatile("lfence" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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#define CPUINFO_PROC "model name"
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@ -23,45 +27,61 @@
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#ifdef __powerpc__
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#include "../../arch/powerpc/include/uapi/asm/unistd.h"
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#define mb() asm volatile ("sync" ::: "memory")
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#define wmb() asm volatile ("sync" ::: "memory")
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#define rmb() asm volatile ("sync" ::: "memory")
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#define cpu_relax() asm volatile ("" ::: "memory");
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#define CPUINFO_PROC "cpu"
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#endif
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#ifdef __s390__
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#define mb() asm volatile("bcr 15,0" ::: "memory")
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#define wmb() asm volatile("bcr 15,0" ::: "memory")
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#define rmb() asm volatile("bcr 15,0" ::: "memory")
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#define cpu_relax() asm volatile("" ::: "memory");
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#endif
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#ifdef __sh__
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#if defined(__SH4A__) || defined(__SH5__)
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# define mb() asm volatile("synco" ::: "memory")
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# define wmb() asm volatile("synco" ::: "memory")
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# define rmb() asm volatile("synco" ::: "memory")
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#else
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# define mb() asm volatile("" ::: "memory")
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# define wmb() asm volatile("" ::: "memory")
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# define rmb() asm volatile("" ::: "memory")
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#endif
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#define cpu_relax() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "cpu type"
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#endif
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#ifdef __hppa__
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#define mb() asm volatile("" ::: "memory")
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#define wmb() asm volatile("" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define cpu_relax() asm volatile("" ::: "memory");
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#define CPUINFO_PROC "cpu"
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#endif
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#ifdef __sparc__
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#ifdef __LP64__
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#define mb() asm volatile("ba,pt %%xcc, 1f\n" \
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"membar #StoreLoad\n" \
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"1:\n":::"memory")
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#else
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#define mb() asm volatile("":::"memory")
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#endif
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#define wmb() asm volatile("":::"memory")
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#define rmb() asm volatile("":::"memory")
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#define cpu_relax() asm volatile("":::"memory")
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#define CPUINFO_PROC "cpu"
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#endif
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#ifdef __alpha__
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#define mb() asm volatile("mb" ::: "memory")
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#define wmb() asm volatile("wmb" ::: "memory")
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#define rmb() asm volatile("mb" ::: "memory")
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#define cpu_relax() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "cpu model"
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#endif
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#ifdef __ia64__
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#define mb() asm volatile ("mf" ::: "memory")
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#define wmb() asm volatile ("mf" ::: "memory")
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#define rmb() asm volatile ("mf" ::: "memory")
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#define cpu_relax() asm volatile ("hint @pause" ::: "memory")
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#define CPUINFO_PROC "model name"
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@ -72,40 +92,55 @@
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* Use the __kuser_memory_barrier helper in the CPU helper page. See
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* arch/arm/kernel/entry-armv.S in the kernel source for details.
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*/
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#define mb() ((void(*)(void))0xffff0fa0)()
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#define wmb() ((void(*)(void))0xffff0fa0)()
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#define rmb() ((void(*)(void))0xffff0fa0)()
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#define cpu_relax() asm volatile("":::"memory")
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#define CPUINFO_PROC "Processor"
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#endif
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#ifdef __aarch64__
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#define rmb() asm volatile("dmb ld" ::: "memory")
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#define mb() asm volatile("dmb ish" ::: "memory")
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#define wmb() asm volatile("dmb ishld" ::: "memory")
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#define rmb() asm volatile("dmb ishst" ::: "memory")
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#define cpu_relax() asm volatile("yield" ::: "memory")
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#endif
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#ifdef __mips__
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#define rmb() asm volatile( \
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#define mb() asm volatile( \
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".set mips2\n\t" \
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"sync\n\t" \
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".set mips0" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#define cpu_relax() asm volatile("" ::: "memory")
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#define wmb() mb()
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#define rmb() mb()
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#define CPUINFO_PROC "cpu model"
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#endif
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#ifdef __arc__
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#define mb() asm volatile("" ::: "memory")
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#define wmb() asm volatile("" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define cpu_relax() rmb()
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#define CPUINFO_PROC "Processor"
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#endif
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#ifdef __metag__
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#define mb() asm volatile("" ::: "memory")
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#define wmb() asm volatile("" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define cpu_relax() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "CPU"
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#endif
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#define barrier() asm volatile ("" ::: "memory")
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#ifndef cpu_relax
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#define cpu_relax() barrier()
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#endif
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#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
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#include <time.h>
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#include <unistd.h>
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#include <sys/types.h>
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@ -9,8 +9,6 @@
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#if defined(__x86_64__) || defined(__i386__)
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#define barrier() asm volatile("" ::: "memory")
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static u64 rdpmc(unsigned int counter)
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{
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unsigned int low, high;
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@ -177,7 +177,7 @@ int perf_evlist__strerror_open(struct perf_evlist *evlist, int err, char *buf, s
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static inline unsigned int perf_mmap__read_head(struct perf_mmap *mm)
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{
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struct perf_event_mmap_page *pc = mm->base;
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int head = pc->data_head;
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int head = ACCESS_ONCE(pc->data_head);
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rmb();
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return head;
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}
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@ -190,7 +190,7 @@ static inline void perf_mmap__write_tail(struct perf_mmap *md,
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/*
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* ensure all reads are done before we write the tail out.
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*/
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/* mb(); */
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mb();
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pc->data_tail = tail;
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}
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