drm/amdgpu: add interface to enable/disable mmhub pg on raven
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2fcd43cef6
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a95890b45f
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@ -414,6 +414,54 @@ void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev)
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WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
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}
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void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t pctl0_reng_execute = 0;
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uint32_t pctl1_reng_execute = 0;
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if (amdgpu_sriov_vf(adev))
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return;
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pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
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pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
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if (enable) {
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pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
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PCTL0_RENG_EXECUTE,
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RENG_EXECUTE_ON_PWR_UP, 1);
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pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
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PCTL0_RENG_EXECUTE,
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RENG_EXECUTE_ON_REG_UPDATE, 1);
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WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
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pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
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PCTL1_RENG_EXECUTE,
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RENG_EXECUTE_ON_PWR_UP, 1);
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pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
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PCTL1_RENG_EXECUTE,
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RENG_EXECUTE_ON_REG_UPDATE, 1);
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WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
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} else {
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pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
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PCTL0_RENG_EXECUTE,
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RENG_EXECUTE_ON_PWR_UP, 0);
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pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
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PCTL0_RENG_EXECUTE,
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RENG_EXECUTE_ON_REG_UPDATE, 0);
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WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
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pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
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PCTL1_RENG_EXECUTE,
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RENG_EXECUTE_ON_PWR_UP, 0);
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pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
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PCTL1_RENG_EXECUTE,
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RENG_EXECUTE_ON_REG_UPDATE, 0);
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WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
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}
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}
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int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
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{
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if (amdgpu_sriov_vf(adev)) {
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@ -33,6 +33,8 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
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enum amd_clockgating_state state);
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void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
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void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev);
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void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
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bool enable);
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extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs;
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extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block;
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