Merge branch 'for-upstream' of git://openrisc.net/jonas/linux
Pull OpenRISC updates from Jonas Bonn: "An equal number of bug fixes and trivial cleanups; no new features. - Two patches to fix errors thrown by the updated toolchain. - Three other bug fixes. - Four trivial cleanups." * 'for-upstream' of git://openrisc.net/jonas/linux: openrisc: add missing header inclusion openrisc: really pass correct arg to schedule_tail Add bitops include needed for ext2 filesystem openrisc: update DTLB-miss handler last openrisc: fix up vmalloc page table loading openrisc idle: delete pm_idle openrisc: remove CONFIG_SYMBOL_PREFIX openrisc: avoid using function parameter regs in reset vector openrisc: remove unused current_regs
This commit is contained in:
Linus Torvalds
Коммит
a9a07d40bc
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@ -26,10 +26,6 @@ config OPENRISC
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config MMU
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def_bool y
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config SYMBOL_PREFIX
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string
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default ""
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config HAVE_DMA_ATTRS
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def_bool y
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@ -54,6 +54,7 @@
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#include <asm-generic/bitops/atomic.h>
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#include <asm-generic/bitops/non-atomic.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic.h>
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#endif /* __ASM_GENERIC_BITOPS_H */
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@ -70,7 +70,6 @@ struct thread_struct {
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*/
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#define task_pt_regs(task) user_regs(task_thread_info(task))
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#define current_regs() user_regs(current_thread_info())
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#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
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@ -201,12 +201,17 @@ EXCEPTION_ENTRY(_bus_fault_handler)
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l.nop
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/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
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EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
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l.and r5,r5,r0
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l.j 1f
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l.nop
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EXCEPTION_ENTRY(_data_page_fault_handler)
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/* set up parameters for do_page_fault */
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l.ori r5,r0,0x300 // exception vector
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1:
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l.addi r3,r1,0 // pt_regs
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/* r4 set be EXCEPTION_HANDLE */ // effective address of fault
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l.ori r5,r0,0x300 // exception vector
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/*
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* __PHX__: TODO
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@ -276,12 +281,17 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
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l.nop
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/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
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EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
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l.and r5,r5,r0
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l.j 1f
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l.nop
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EXCEPTION_ENTRY(_insn_page_fault_handler)
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/* set up parameters for do_page_fault */
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l.ori r5,r0,0x400 // exception vector
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1:
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l.addi r3,r1,0 // pt_regs
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/* r4 set be EXCEPTION_HANDLE */ // effective address of fault
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l.ori r5,r0,0x400 // exception vector
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l.ori r6,r0,0x0 // !write access
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/* call fault.c handler in or32/mm/fault.c */
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@ -1040,7 +1050,7 @@ ENTRY(_switch)
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* we are expected to have set up the arg to schedule_tail already,
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* hence we do so here unconditionally:
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*/
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l.lwz r3,TI_STACK(r3) /* Load 'prev' as schedule_tail arg */
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l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */
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l.jr r9
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l.nop
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@ -19,6 +19,7 @@
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#include <linux/threads.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/serial_reg.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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@ -291,9 +292,9 @@
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/* Jump to .init code at _start which lives in the .head section
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* and will be discarded after boot.
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*/
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LOAD_SYMBOL_2_GPR(r4, _start)
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tophys (r3,r4) /* MMU disabled */
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l.jr r3
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LOAD_SYMBOL_2_GPR(r15, _start)
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tophys (r13,r15) /* MMU disabled */
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l.jr r13
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l.nop
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/* ---[ 0x200: BUS exception ]------------------------------------------- */
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@ -1069,8 +1070,7 @@ d_pte_not_present:
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EXCEPTION_LOAD_GPR4
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EXCEPTION_LOAD_GPR5
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EXCEPTION_LOAD_GPR6
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l.j _dispatch_do_dpage_fault
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l.nop
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EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
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/* ==============================================[ ITLB miss handler ]=== */
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ENTRY(itlb_miss_handler)
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@ -1192,8 +1192,7 @@ i_pte_not_present:
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EXCEPTION_LOAD_GPR4
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EXCEPTION_LOAD_GPR5
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EXCEPTION_LOAD_GPR6
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l.j _dispatch_do_ipage_fault
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l.nop
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EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
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/* ==============================================[ boot tlb handlers ]=== */
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@ -167,15 +167,26 @@ void __init paging_init(void)
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unsigned long *dtlb_vector = __va(0x900);
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unsigned long *itlb_vector = __va(0xa00);
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printk(KERN_INFO "itlb_miss_handler %p\n", &itlb_miss_handler);
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*itlb_vector = ((unsigned long)&itlb_miss_handler -
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(unsigned long)itlb_vector) >> 2;
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/* Soft ordering constraint to ensure that dtlb_vector is
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* the last thing updated
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*/
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barrier();
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printk(KERN_INFO "dtlb_miss_handler %p\n", &dtlb_miss_handler);
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*dtlb_vector = ((unsigned long)&dtlb_miss_handler -
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(unsigned long)dtlb_vector) >> 2;
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printk(KERN_INFO "itlb_miss_handler %p\n", &itlb_miss_handler);
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*itlb_vector = ((unsigned long)&itlb_miss_handler -
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(unsigned long)itlb_vector) >> 2;
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}
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/* Soft ordering constraint to ensure that cache invalidation and
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* TLB flush really happen _after_ code has been modified.
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*/
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barrier();
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/* Invalidate instruction caches after code modification */
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mtspr(SPR_ICBIR, 0x900);
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mtspr(SPR_ICBIR, 0xa00);
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