Merge series "ASoC: brcm: add dsl and pon chip audio driver" from Kevin Li <kevin-ke.li@broadcom.com>:
Changes in v2: * Make the comment a C++ one for license header * Remove all empty functions * Change all variable to use kernel coding style * Comment chip TX RX block independently generate I2S bus signals Kevin Li (2): ASoC: brcm: Add DSL/PON SoC audio driver ASoC: brcm: DSL/PON SoC device tree bindings of audio driver .../bindings/sound/brcm,bcm63xx-audio.txt | 29 ++ sound/soc/bcm/Kconfig | 9 + sound/soc/bcm/Makefile | 4 + sound/soc/bcm/bcm63xx-i2s-whistler.c | 317 ++++++++++++ sound/soc/bcm/bcm63xx-i2s.h | 90 ++++ sound/soc/bcm/bcm63xx-pcm-whistler.c | 485 ++++++++++++++++++ 6 files changed, 934 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/brcm,bcm63xx-audio.txt create mode 100644 sound/soc/bcm/bcm63xx-i2s-whistler.c create mode 100644 sound/soc/bcm/bcm63xx-i2s.h create mode 100644 sound/soc/bcm/bcm63xx-pcm-whistler.c -- 2.25.1
This commit is contained in:
Mark Brown
Коммит
a9bb153d3f
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@ -0,0 +1,29 @@
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Broadcom DSL/PON BCM63xx Audio I2S controller
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Required properties:
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- compatible: Should be "brcm,bcm63xx-i2s".
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- #address-cells: 32bit valued, 1 cell.
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- #size-cells: 32bit valued, 0 cell.
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- reg: Should contain audio registers location and length
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- interrupts: Should contain the interrupt for the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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Please refer to clock-bindings.txt.
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- clock-names: One of each entry matching the clocks phandles list:
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- "i2sclk" (generated clock) Required.
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- "i2sosc" (fixed 200MHz clock) Required.
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(1) : The generated clock is required only when any of TX and RX
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works on Master Mode.
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(2) : The fixed 200MHz clock is from internal chip and always on
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Example:
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i2s: bcm63xx-i2s {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,bcm63xx-i2s";
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reg = <0xFF802080 0xFF>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&i2sclk>, <&osc>;
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clock-names = "i2sclk","i2sosc";
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};
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@ -17,3 +17,12 @@ config SND_SOC_CYGNUS
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Cygnus chips (bcm958300, bcm958305, bcm911360)
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If you don't know what to do here, say N.
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config SND_BCM63XX_I2S_WHISTLER
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tristate "SoC Audio support for the Broadcom BCM63XX I2S module"
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select REGMAP_MMIO
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help
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Say Y if you want to add support for ASoC audio on Broadcom
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DSL/PON chips (bcm63158, bcm63178)
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If you don't know what to do here, say N
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@ -9,3 +9,7 @@ snd-soc-cygnus-objs := cygnus-pcm.o cygnus-ssp.o
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obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-cygnus.o
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# BCM63XX Platform Support
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snd-soc-63xx-objs := bcm63xx-i2s-whistler.o bcm63xx-pcm-whistler.o
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obj-$(CONFIG_SND_BCM63XX_I2S_WHISTLER) += snd-soc-63xx.o
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@ -0,0 +1,317 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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// linux/sound/bcm/bcm63xx-i2s-whistler.c
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// BCM63xx whistler i2s driver
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// Copyright (c) 2020 Broadcom Corporation
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// Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "bcm63xx-i2s.h"
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#define DRV_NAME "brcm-i2s"
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static bool brcm_i2s_wr_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case I2S_TX_CFG ... I2S_TX_DESC_IFF_LEN:
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case I2S_TX_CFG_2 ... I2S_RX_DESC_IFF_LEN:
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case I2S_RX_CFG_2 ... I2S_REG_MAX:
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return true;
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default:
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return false;
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}
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}
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static bool brcm_i2s_rd_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case I2S_TX_CFG ... I2S_REG_MAX:
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return true;
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default:
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return false;
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}
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}
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static bool brcm_i2s_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case I2S_TX_CFG:
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case I2S_TX_IRQ_CTL:
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case I2S_TX_DESC_IFF_ADDR:
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case I2S_TX_DESC_IFF_LEN:
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case I2S_TX_DESC_OFF_ADDR:
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case I2S_TX_DESC_OFF_LEN:
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case I2S_TX_CFG_2:
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case I2S_RX_CFG:
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case I2S_RX_IRQ_CTL:
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case I2S_RX_DESC_OFF_ADDR:
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case I2S_RX_DESC_OFF_LEN:
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case I2S_RX_DESC_IFF_LEN:
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case I2S_RX_DESC_IFF_ADDR:
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case I2S_RX_CFG_2:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config brcm_i2s_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = I2S_REG_MAX,
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.writeable_reg = brcm_i2s_wr_reg,
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.readable_reg = brcm_i2s_rd_reg,
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.volatile_reg = brcm_i2s_volatile_reg,
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.cache_type = REGCACHE_FLAT,
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};
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static int bcm63xx_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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int ret = 0;
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struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
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ret = clk_set_rate(i2s_priv->i2s_clk, params_rate(params));
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if (ret < 0)
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dev_err(i2s_priv->dev,
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"Can't set sample rate, err: %d\n", ret);
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return ret;
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}
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static int bcm63xx_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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unsigned int slavemode;
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struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
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struct regmap *regmap_i2s = i2s_priv->regmap_i2s;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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regmap_update_bits(regmap_i2s, I2S_TX_CFG,
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I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
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I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE,
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I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
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I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE);
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regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 0);
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regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 0);
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regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 1);
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/* TX and RX block each have an independent bit to indicate
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* if it is generating the clock for the I2S bus. The bus
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* clocks need to be generated from either the TX or RX block,
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* but not both
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*/
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regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);
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if (slavemode & I2S_RX_SLAVE_MODE_MASK)
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regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
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I2S_TX_SLAVE_MODE_MASK,
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I2S_TX_MASTER_MODE);
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else
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regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
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I2S_TX_SLAVE_MODE_MASK,
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I2S_TX_SLAVE_MODE);
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} else {
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regmap_update_bits(regmap_i2s, I2S_RX_CFG,
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I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
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I2S_RX_CLOCK_ENABLE,
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I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
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I2S_RX_CLOCK_ENABLE);
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regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 0);
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regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 0);
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regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 1);
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regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);
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if (slavemode & I2S_TX_SLAVE_MODE_MASK)
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regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
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I2S_RX_SLAVE_MODE_MASK, 0);
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else
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regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
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I2S_RX_SLAVE_MODE_MASK,
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I2S_RX_SLAVE_MODE);
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}
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return 0;
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}
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static void bcm63xx_i2s_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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unsigned int enabled, slavemode;
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struct bcm_i2s_priv *i2s_priv = snd_soc_dai_get_drvdata(dai);
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struct regmap *regmap_i2s = i2s_priv->regmap_i2s;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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regmap_update_bits(regmap_i2s, I2S_TX_CFG,
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I2S_TX_OUT_R | I2S_TX_DATA_ALIGNMENT |
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I2S_TX_DATA_ENABLE | I2S_TX_CLOCK_ENABLE, 0);
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regmap_write(regmap_i2s, I2S_TX_IRQ_CTL, 1);
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regmap_write(regmap_i2s, I2S_TX_IRQ_IFF_THLD, 4);
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regmap_write(regmap_i2s, I2S_TX_IRQ_OFF_THLD, 4);
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regmap_read(regmap_i2s, I2S_TX_CFG_2, &slavemode);
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slavemode = slavemode & I2S_TX_SLAVE_MODE_MASK;
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if (!slavemode) {
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regmap_read(regmap_i2s, I2S_RX_CFG, &enabled);
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enabled = enabled & I2S_RX_ENABLE_MASK;
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if (enabled)
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regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
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I2S_RX_SLAVE_MODE_MASK,
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I2S_RX_MASTER_MODE);
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}
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regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
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I2S_TX_SLAVE_MODE_MASK,
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I2S_TX_SLAVE_MODE);
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} else {
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regmap_update_bits(regmap_i2s, I2S_RX_CFG,
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I2S_RX_IN_R | I2S_RX_DATA_ALIGNMENT |
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I2S_RX_CLOCK_ENABLE, 0);
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regmap_write(regmap_i2s, I2S_RX_IRQ_CTL, 1);
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regmap_write(regmap_i2s, I2S_RX_IRQ_IFF_THLD, 4);
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regmap_write(regmap_i2s, I2S_RX_IRQ_OFF_THLD, 4);
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regmap_read(regmap_i2s, I2S_RX_CFG_2, &slavemode);
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slavemode = slavemode & I2S_RX_SLAVE_MODE_MASK;
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if (!slavemode) {
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regmap_read(regmap_i2s, I2S_TX_CFG, &enabled);
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enabled = enabled & I2S_TX_ENABLE_MASK;
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if (enabled)
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regmap_update_bits(regmap_i2s, I2S_TX_CFG_2,
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I2S_TX_SLAVE_MODE_MASK,
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I2S_TX_MASTER_MODE);
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}
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regmap_update_bits(regmap_i2s, I2S_RX_CFG_2,
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I2S_RX_SLAVE_MODE_MASK, I2S_RX_SLAVE_MODE);
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}
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}
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static const struct snd_soc_dai_ops bcm63xx_i2s_dai_ops = {
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.startup = bcm63xx_i2s_startup,
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.shutdown = bcm63xx_i2s_shutdown,
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.hw_params = bcm63xx_i2s_hw_params,
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};
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static struct snd_soc_dai_driver bcm63xx_i2s_dai = {
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.name = DRV_NAME,
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.playback = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S32_LE,
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},
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.capture = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S32_LE,
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},
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.ops = &bcm63xx_i2s_dai_ops,
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.symmetric_rates = 1,
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.symmetric_channels = 1,
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};
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static const struct snd_soc_component_driver bcm63xx_i2s_component = {
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.name = "bcm63xx",
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};
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static int bcm63xx_i2s_dev_probe(struct platform_device *pdev)
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{
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int ret = 0;
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void __iomem *regs;
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struct resource *r_mem, *region;
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struct bcm_i2s_priv *i2s_priv;
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struct regmap *regmap_i2s;
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struct clk *i2s_clk;
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i2s_priv = devm_kzalloc(&pdev->dev, sizeof(*i2s_priv), GFP_KERNEL);
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if (!i2s_priv)
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return -ENOMEM;
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i2s_clk = devm_clk_get(&pdev->dev, "i2sclk");
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if (IS_ERR(i2s_clk)) {
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dev_err(&pdev->dev, "%s: cannot get a brcm clock: %ld\n",
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__func__, PTR_ERR(i2s_clk));
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return PTR_ERR(i2s_clk);
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}
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r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r_mem) {
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dev_err(&pdev->dev, "Unable to get register resource.\n");
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return -ENODEV;
|
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}
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region = devm_request_mem_region(&pdev->dev, r_mem->start,
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resource_size(r_mem), DRV_NAME);
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if (!region) {
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dev_err(&pdev->dev, "Memory region already claimed\n");
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return -EBUSY;
|
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}
|
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regs = devm_ioremap_resource(&pdev->dev, r_mem);
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if (IS_ERR(regs)) {
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ret = PTR_ERR(regs);
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return ret;
|
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}
|
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regmap_i2s = devm_regmap_init_mmio(&pdev->dev,
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regs, &brcm_i2s_regmap_config);
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if (IS_ERR(regmap_i2s))
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return PTR_ERR(regmap_i2s);
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regmap_update_bits(regmap_i2s, I2S_MISC_CFG,
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I2S_PAD_LVL_LOOP_DIS_MASK,
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I2S_PAD_LVL_LOOP_DIS_ENABLE);
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|
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ret = devm_snd_soc_register_component(&pdev->dev,
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&bcm63xx_i2s_component,
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&bcm63xx_i2s_dai, 1);
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if (ret) {
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dev_err(&pdev->dev, "failed to register the dai\n");
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return ret;
|
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}
|
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|
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i2s_priv->dev = &pdev->dev;
|
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i2s_priv->i2s_clk = i2s_clk;
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i2s_priv->regmap_i2s = regmap_i2s;
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dev_set_drvdata(&pdev->dev, i2s_priv);
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ret = bcm63xx_soc_platform_probe(pdev, i2s_priv);
|
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if (ret)
|
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dev_err(&pdev->dev, "failed to register the pcm\n");
|
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|
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return ret;
|
||||
}
|
||||
|
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static int bcm63xx_i2s_dev_remove(struct platform_device *pdev)
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{
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bcm63xx_soc_platform_remove(pdev);
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return 0;
|
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}
|
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|
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#ifdef CONFIG_OF
|
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static const struct of_device_id snd_soc_bcm_audio_match[] = {
|
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{.compatible = "brcm,bcm63xx-i2s"},
|
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{ }
|
||||
};
|
||||
#endif
|
||||
|
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static struct platform_driver bcm63xx_i2s_driver = {
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
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.of_match_table = of_match_ptr(snd_soc_bcm_audio_match),
|
||||
},
|
||||
.probe = bcm63xx_i2s_dev_probe,
|
||||
.remove = bcm63xx_i2s_dev_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(bcm63xx_i2s_driver);
|
||||
|
||||
MODULE_AUTHOR("Kevin,Li <kevin-ke.li@broadcom.com>");
|
||||
MODULE_DESCRIPTION("Broadcom DSL XPON ASOC I2S Interface");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
// linux/sound/soc/bcm/bcm63xx-i2s.h
|
||||
// Copyright (c) 2020 Broadcom Corporation
|
||||
// Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>
|
||||
|
||||
#ifndef __BCM63XX_I2S_H
|
||||
#define __BCM63XX_I2S_H
|
||||
|
||||
#define I2S_DESC_FIFO_DEPTH 8
|
||||
#define I2S_MISC_CFG (0x003C)
|
||||
#define I2S_PAD_LVL_LOOP_DIS_MASK (1 << 2)
|
||||
#define I2S_PAD_LVL_LOOP_DIS_ENABLE I2S_PAD_LVL_LOOP_DIS_MASK
|
||||
|
||||
#define I2S_TX_ENABLE_MASK (1 << 31)
|
||||
#define I2S_TX_ENABLE I2S_TX_ENABLE_MASK
|
||||
#define I2S_TX_OUT_R (1 << 19)
|
||||
#define I2S_TX_DATA_ALIGNMENT (1 << 2)
|
||||
#define I2S_TX_DATA_ENABLE (1 << 1)
|
||||
#define I2S_TX_CLOCK_ENABLE (1 << 0)
|
||||
|
||||
#define I2S_TX_DESC_OFF_LEVEL_SHIFT 12
|
||||
#define I2S_TX_DESC_OFF_LEVEL_MASK (0x0F << I2S_TX_DESC_OFF_LEVEL_SHIFT)
|
||||
#define I2S_TX_DESC_IFF_LEVEL_SHIFT 8
|
||||
#define I2S_TX_DESC_IFF_LEVEL_MASK (0x0F << I2S_TX_DESC_IFF_LEVEL_SHIFT)
|
||||
#define I2S_TX_DESC_OFF_INTR_EN_MSK (1 << 1)
|
||||
#define I2S_TX_DESC_OFF_INTR_EN I2S_TX_DESC_OFF_INTR_EN_MSK
|
||||
|
||||
#define I2S_TX_CFG (0x0000)
|
||||
#define I2S_TX_IRQ_CTL (0x0004)
|
||||
#define I2S_TX_IRQ_EN (0x0008)
|
||||
#define I2S_TX_IRQ_IFF_THLD (0x000c)
|
||||
#define I2S_TX_IRQ_OFF_THLD (0x0010)
|
||||
#define I2S_TX_DESC_IFF_ADDR (0x0014)
|
||||
#define I2S_TX_DESC_IFF_LEN (0x0018)
|
||||
#define I2S_TX_DESC_OFF_ADDR (0x001C)
|
||||
#define I2S_TX_DESC_OFF_LEN (0x0020)
|
||||
#define I2S_TX_CFG_2 (0x0024)
|
||||
#define I2S_TX_SLAVE_MODE_SHIFT 13
|
||||
#define I2S_TX_SLAVE_MODE_MASK (1 << I2S_TX_SLAVE_MODE_SHIFT)
|
||||
#define I2S_TX_SLAVE_MODE I2S_TX_SLAVE_MODE_MASK
|
||||
#define I2S_TX_MASTER_MODE 0
|
||||
#define I2S_TX_INTR_MASK 0x0F
|
||||
|
||||
#define I2S_RX_ENABLE_MASK (1 << 31)
|
||||
#define I2S_RX_ENABLE I2S_RX_ENABLE_MASK
|
||||
#define I2S_RX_IN_R (1 << 19)
|
||||
#define I2S_RX_DATA_ALIGNMENT (1 << 2)
|
||||
#define I2S_RX_CLOCK_ENABLE (1 << 0)
|
||||
|
||||
#define I2S_RX_DESC_OFF_LEVEL_SHIFT 12
|
||||
#define I2S_RX_DESC_OFF_LEVEL_MASK (0x0F << I2S_RX_DESC_OFF_LEVEL_SHIFT)
|
||||
#define I2S_RX_DESC_IFF_LEVEL_SHIFT 8
|
||||
#define I2S_RX_DESC_IFF_LEVEL_MASK (0x0F << I2S_RX_DESC_IFF_LEVEL_SHIFT)
|
||||
#define I2S_RX_DESC_OFF_INTR_EN_MSK (1 << 1)
|
||||
#define I2S_RX_DESC_OFF_INTR_EN I2S_RX_DESC_OFF_INTR_EN_MSK
|
||||
|
||||
#define I2S_RX_CFG (0x0040) /* 20c0 */
|
||||
#define I2S_RX_IRQ_CTL (0x0044)
|
||||
#define I2S_RX_IRQ_EN (0x0048)
|
||||
#define I2S_RX_IRQ_IFF_THLD (0x004C)
|
||||
#define I2S_RX_IRQ_OFF_THLD (0x0050)
|
||||
#define I2S_RX_DESC_IFF_ADDR (0x0054)
|
||||
#define I2S_RX_DESC_IFF_LEN (0x0058)
|
||||
#define I2S_RX_DESC_OFF_ADDR (0x005C)
|
||||
#define I2S_RX_DESC_OFF_LEN (0x0060)
|
||||
#define I2S_RX_CFG_2 (0x0064)
|
||||
#define I2S_RX_SLAVE_MODE_SHIFT 13
|
||||
#define I2S_RX_SLAVE_MODE_MASK (1 << I2S_RX_SLAVE_MODE_SHIFT)
|
||||
#define I2S_RX_SLAVE_MODE I2S_RX_SLAVE_MODE_MASK
|
||||
#define I2S_RX_MASTER_MODE 0
|
||||
#define I2S_RX_INTR_MASK 0x0F
|
||||
|
||||
#define I2S_REG_MAX 0x007C
|
||||
|
||||
struct bcm_i2s_priv {
|
||||
struct device *dev;
|
||||
struct resource *r_irq;
|
||||
struct regmap *regmap_i2s;
|
||||
struct clk *i2s_clk;
|
||||
struct snd_pcm_substream *play_substream;
|
||||
struct snd_pcm_substream *capture_substream;
|
||||
struct i2s_dma_desc *play_dma_desc;
|
||||
struct i2s_dma_desc *capture_dma_desc;
|
||||
};
|
||||
|
||||
extern int bcm63xx_soc_platform_probe(struct platform_device *pdev,
|
||||
struct bcm_i2s_priv *i2s_priv);
|
||||
extern int bcm63xx_soc_platform_remove(struct platform_device *pdev);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,485 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
// linux/sound/bcm/bcm63xx-pcm-whistler.c
|
||||
// BCM63xx whistler pcm interface
|
||||
// Copyright (c) 2020 Broadcom Corporation
|
||||
// Author: Kevin-Ke Li <kevin-ke.li@broadcom.com>
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <sound/soc.h>
|
||||
#include "bcm63xx-i2s.h"
|
||||
|
||||
|
||||
struct i2s_dma_desc {
|
||||
unsigned char *dma_area;
|
||||
dma_addr_t dma_addr;
|
||||
unsigned int dma_len;
|
||||
};
|
||||
|
||||
struct bcm63xx_runtime_data {
|
||||
int dma_len;
|
||||
dma_addr_t dma_addr;
|
||||
dma_addr_t dma_addr_next;
|
||||
};
|
||||
|
||||
static const struct snd_pcm_hardware bcm63xx_pcm_hardware = {
|
||||
.info = SNDRV_PCM_INFO_MMAP |
|
||||
SNDRV_PCM_INFO_MMAP_VALID |
|
||||
SNDRV_PCM_INFO_INTERLEAVED |
|
||||
SNDRV_PCM_INFO_PAUSE |
|
||||
SNDRV_PCM_INFO_RESUME,
|
||||
.formats = SNDRV_PCM_FMTBIT_S32_LE, /* support S32 only */
|
||||
.period_bytes_max = 8192 - 32,
|
||||
.periods_min = 1,
|
||||
.periods_max = PAGE_SIZE/sizeof(struct i2s_dma_desc),
|
||||
.buffer_bytes_max = 128 * 1024,
|
||||
.fifo_size = 32,
|
||||
};
|
||||
|
||||
static int bcm63xx_pcm_hw_params(struct snd_soc_component *component,
|
||||
struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params)
|
||||
{
|
||||
struct i2s_dma_desc *dma_desc;
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
|
||||
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
|
||||
runtime->dma_bytes = params_buffer_bytes(params);
|
||||
|
||||
dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
|
||||
if (!dma_desc)
|
||||
return -ENOMEM;
|
||||
|
||||
snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_desc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm63xx_pcm_hw_free(struct snd_soc_component *component,
|
||||
struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct i2s_dma_desc *dma_desc;
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
|
||||
dma_desc = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
|
||||
kfree(dma_desc);
|
||||
snd_pcm_set_runtime_buffer(substream, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm63xx_pcm_trigger(struct snd_soc_component *component,
|
||||
struct snd_pcm_substream *substream, int cmd)
|
||||
{
|
||||
int ret = 0;
|
||||
struct snd_soc_pcm_runtime *rtd;
|
||||
struct bcm_i2s_priv *i2s_priv;
|
||||
struct regmap *regmap_i2s;
|
||||
|
||||
rtd = substream->private_data;
|
||||
i2s_priv = dev_get_drvdata(rtd->cpu_dai->dev);
|
||||
regmap_i2s = i2s_priv->regmap_i2s;
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
regmap_update_bits(regmap_i2s,
|
||||
I2S_TX_IRQ_EN,
|
||||
I2S_TX_DESC_OFF_INTR_EN,
|
||||
I2S_TX_DESC_OFF_INTR_EN);
|
||||
regmap_update_bits(regmap_i2s,
|
||||
I2S_TX_CFG,
|
||||
I2S_TX_ENABLE_MASK,
|
||||
I2S_TX_ENABLE);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
regmap_write(regmap_i2s,
|
||||
I2S_TX_IRQ_EN,
|
||||
0);
|
||||
regmap_update_bits(regmap_i2s,
|
||||
I2S_TX_CFG,
|
||||
I2S_TX_ENABLE_MASK,
|
||||
0);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
}
|
||||
} else {
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
regmap_update_bits(regmap_i2s,
|
||||
I2S_RX_IRQ_EN,
|
||||
I2S_RX_DESC_OFF_INTR_EN_MSK,
|
||||
I2S_RX_DESC_OFF_INTR_EN);
|
||||
regmap_update_bits(regmap_i2s,
|
||||
I2S_RX_CFG,
|
||||
I2S_RX_ENABLE_MASK,
|
||||
I2S_RX_ENABLE);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
regmap_update_bits(regmap_i2s,
|
||||
I2S_RX_IRQ_EN,
|
||||
I2S_RX_DESC_OFF_INTR_EN_MSK,
|
||||
0);
|
||||
regmap_update_bits(regmap_i2s,
|
||||
I2S_RX_CFG,
|
||||
I2S_RX_ENABLE_MASK,
|
||||
0);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bcm63xx_pcm_prepare(struct snd_soc_component *component,
|
||||
struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct i2s_dma_desc *dma_desc;
|
||||
struct regmap *regmap_i2s;
|
||||
struct bcm_i2s_priv *i2s_priv;
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
uint32_t regaddr_desclen, regaddr_descaddr;
|
||||
|
||||
dma_desc = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
|
||||
dma_desc->dma_len = snd_pcm_lib_period_bytes(substream);
|
||||
dma_desc->dma_addr = runtime->dma_addr;
|
||||
dma_desc->dma_area = runtime->dma_area;
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
regaddr_desclen = I2S_TX_DESC_IFF_LEN;
|
||||
regaddr_descaddr = I2S_TX_DESC_IFF_ADDR;
|
||||
} else {
|
||||
regaddr_desclen = I2S_RX_DESC_IFF_LEN;
|
||||
regaddr_descaddr = I2S_RX_DESC_IFF_ADDR;
|
||||
}
|
||||
|
||||
i2s_priv = dev_get_drvdata(rtd->cpu_dai->dev);
|
||||
regmap_i2s = i2s_priv->regmap_i2s;
|
||||
|
||||
regmap_write(regmap_i2s, regaddr_desclen, dma_desc->dma_len);
|
||||
regmap_write(regmap_i2s, regaddr_descaddr, dma_desc->dma_addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static snd_pcm_uframes_t
|
||||
bcm63xx_pcm_pointer(struct snd_soc_component *component,
|
||||
struct snd_pcm_substream *substream)
|
||||
{
|
||||
snd_pcm_uframes_t x;
|
||||
struct bcm63xx_runtime_data *prtd = substream->runtime->private_data;
|
||||
|
||||
if ((void *)prtd->dma_addr_next == NULL)
|
||||
prtd->dma_addr_next = substream->runtime->dma_addr;
|
||||
|
||||
x = bytes_to_frames(substream->runtime,
|
||||
prtd->dma_addr_next - substream->runtime->dma_addr);
|
||||
|
||||
return x == substream->runtime->buffer_size ? 0 : x;
|
||||
}
|
||||
|
||||
static int bcm63xx_pcm_mmap(struct snd_soc_component *component,
|
||||
struct snd_pcm_substream *substream,
|
||||
struct vm_area_struct *vma)
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
|
||||
return dma_mmap_wc(substream->pcm->card->dev, vma,
|
||||
runtime->dma_area,
|
||||
runtime->dma_addr,
|
||||
runtime->dma_bytes);
|
||||
|
||||
}
|
||||
|
||||
static int bcm63xx_pcm_open(struct snd_soc_component *component,
|
||||
struct snd_pcm_substream *substream)
|
||||
{
|
||||
int ret = 0;
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct bcm63xx_runtime_data *prtd;
|
||||
|
||||
runtime->hw = bcm63xx_pcm_hardware;
|
||||
ret = snd_pcm_hw_constraint_step(runtime, 0,
|
||||
SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = snd_pcm_hw_constraint_step(runtime, 0,
|
||||
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = snd_pcm_hw_constraint_integer(runtime,
|
||||
SNDRV_PCM_HW_PARAM_PERIODS);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = -ENOMEM;
|
||||
prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
|
||||
if (!prtd)
|
||||
goto out;
|
||||
|
||||
runtime->private_data = prtd;
|
||||
return 0;
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bcm63xx_pcm_close(struct snd_soc_component *component,
|
||||
struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = substream->runtime;
|
||||
struct bcm63xx_runtime_data *prtd = runtime->private_data;
|
||||
|
||||
kfree(prtd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t i2s_dma_isr(int irq, void *bcm_i2s_priv)
|
||||
{
|
||||
unsigned int availdepth, ifflevel, offlevel, int_status, val_1, val_2;
|
||||
struct bcm63xx_runtime_data *prtd;
|
||||
struct snd_pcm_substream *substream;
|
||||
struct snd_pcm_runtime *runtime;
|
||||
struct regmap *regmap_i2s;
|
||||
struct i2s_dma_desc *dma_desc;
|
||||
struct snd_soc_pcm_runtime *rtd;
|
||||
struct bcm_i2s_priv *i2s_priv;
|
||||
|
||||
i2s_priv = (struct bcm_i2s_priv *)bcm_i2s_priv;
|
||||
regmap_i2s = i2s_priv->regmap_i2s;
|
||||
|
||||
/* rx */
|
||||
regmap_read(regmap_i2s, I2S_RX_IRQ_CTL, &int_status);
|
||||
|
||||
if (int_status & I2S_RX_DESC_OFF_INTR_EN_MSK) {
|
||||
substream = i2s_priv->capture_substream;
|
||||
runtime = substream->runtime;
|
||||
rtd = substream->private_data;
|
||||
prtd = runtime->private_data;
|
||||
dma_desc = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
|
||||
|
||||
offlevel = (int_status & I2S_RX_DESC_OFF_LEVEL_MASK) >>
|
||||
I2S_RX_DESC_OFF_LEVEL_SHIFT;
|
||||
while (offlevel) {
|
||||
regmap_read(regmap_i2s, I2S_RX_DESC_OFF_ADDR, &val_1);
|
||||
regmap_read(regmap_i2s, I2S_RX_DESC_OFF_LEN, &val_2);
|
||||
offlevel--;
|
||||
}
|
||||
prtd->dma_addr_next = val_1 + val_2;
|
||||
ifflevel = (int_status & I2S_RX_DESC_IFF_LEVEL_MASK) >>
|
||||
I2S_RX_DESC_IFF_LEVEL_SHIFT;
|
||||
|
||||
availdepth = I2S_DESC_FIFO_DEPTH - ifflevel;
|
||||
while (availdepth) {
|
||||
dma_desc->dma_addr +=
|
||||
snd_pcm_lib_period_bytes(substream);
|
||||
dma_desc->dma_area +=
|
||||
snd_pcm_lib_period_bytes(substream);
|
||||
if (dma_desc->dma_addr - runtime->dma_addr >=
|
||||
runtime->dma_bytes) {
|
||||
dma_desc->dma_addr = runtime->dma_addr;
|
||||
dma_desc->dma_area = runtime->dma_area;
|
||||
}
|
||||
|
||||
prtd->dma_addr = dma_desc->dma_addr;
|
||||
regmap_write(regmap_i2s, I2S_RX_DESC_IFF_LEN,
|
||||
snd_pcm_lib_period_bytes(substream));
|
||||
regmap_write(regmap_i2s, I2S_RX_DESC_IFF_ADDR,
|
||||
dma_desc->dma_addr);
|
||||
availdepth--;
|
||||
}
|
||||
|
||||
snd_pcm_period_elapsed(substream);
|
||||
|
||||
/* Clear interrupt by writing 0 */
|
||||
regmap_update_bits(regmap_i2s, I2S_RX_IRQ_CTL,
|
||||
I2S_RX_INTR_MASK, 0);
|
||||
}
|
||||
|
||||
/* tx */
|
||||
regmap_read(regmap_i2s, I2S_TX_IRQ_CTL, &int_status);
|
||||
|
||||
if (int_status & I2S_TX_DESC_OFF_INTR_EN_MSK) {
|
||||
substream = i2s_priv->play_substream;
|
||||
runtime = substream->runtime;
|
||||
rtd = substream->private_data;
|
||||
prtd = runtime->private_data;
|
||||
dma_desc = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
|
||||
|
||||
offlevel = (int_status & I2S_TX_DESC_OFF_LEVEL_MASK) >>
|
||||
I2S_TX_DESC_OFF_LEVEL_SHIFT;
|
||||
while (offlevel) {
|
||||
regmap_read(regmap_i2s, I2S_TX_DESC_OFF_ADDR, &val_1);
|
||||
regmap_read(regmap_i2s, I2S_TX_DESC_OFF_LEN, &val_2);
|
||||
prtd->dma_addr_next = val_1 + val_2;
|
||||
offlevel--;
|
||||
}
|
||||
|
||||
ifflevel = (int_status & I2S_TX_DESC_IFF_LEVEL_MASK) >>
|
||||
I2S_TX_DESC_IFF_LEVEL_SHIFT;
|
||||
availdepth = I2S_DESC_FIFO_DEPTH - ifflevel;
|
||||
|
||||
while (availdepth) {
|
||||
dma_desc->dma_addr +=
|
||||
snd_pcm_lib_period_bytes(substream);
|
||||
dma_desc->dma_area +=
|
||||
snd_pcm_lib_period_bytes(substream);
|
||||
|
||||
if (dma_desc->dma_addr - runtime->dma_addr >=
|
||||
runtime->dma_bytes) {
|
||||
dma_desc->dma_addr = runtime->dma_addr;
|
||||
dma_desc->dma_area = runtime->dma_area;
|
||||
}
|
||||
|
||||
prtd->dma_addr = dma_desc->dma_addr;
|
||||
regmap_write(regmap_i2s, I2S_TX_DESC_IFF_LEN,
|
||||
snd_pcm_lib_period_bytes(substream));
|
||||
regmap_write(regmap_i2s, I2S_TX_DESC_IFF_ADDR,
|
||||
dma_desc->dma_addr);
|
||||
availdepth--;
|
||||
}
|
||||
|
||||
snd_pcm_period_elapsed(substream);
|
||||
|
||||
/* Clear interrupt by writing 0 */
|
||||
regmap_update_bits(regmap_i2s, I2S_TX_IRQ_CTL,
|
||||
I2S_TX_INTR_MASK, 0);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int bcm63xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
|
||||
{
|
||||
struct snd_pcm_substream *substream = pcm->streams[stream].substream;
|
||||
struct snd_dma_buffer *buf = &substream->dma_buffer;
|
||||
size_t size = bcm63xx_pcm_hardware.buffer_bytes_max;
|
||||
|
||||
buf->dev.type = SNDRV_DMA_TYPE_DEV;
|
||||
buf->dev.dev = pcm->card->dev;
|
||||
buf->private_data = NULL;
|
||||
|
||||
buf->area = dma_alloc_wc(pcm->card->dev,
|
||||
size, &buf->addr,
|
||||
GFP_KERNEL);
|
||||
if (!buf->area)
|
||||
return -ENOMEM;
|
||||
buf->bytes = size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm63xx_soc_pcm_new(struct snd_soc_component *component,
|
||||
struct snd_soc_pcm_runtime *rtd)
|
||||
{
|
||||
struct snd_pcm *pcm = rtd->pcm;
|
||||
struct bcm_i2s_priv *i2s_priv;
|
||||
int ret;
|
||||
|
||||
i2s_priv = dev_get_drvdata(rtd->cpu_dai->dev);
|
||||
|
||||
of_dma_configure(pcm->card->dev, pcm->card->dev->of_node, 1);
|
||||
|
||||
ret = dma_coerce_mask_and_coherent(pcm->card->dev, DMA_BIT_MASK(32));
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
|
||||
ret = bcm63xx_pcm_preallocate_dma_buffer(pcm,
|
||||
SNDRV_PCM_STREAM_PLAYBACK);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
i2s_priv->play_substream =
|
||||
pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
|
||||
}
|
||||
|
||||
if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
|
||||
ret = bcm63xx_pcm_preallocate_dma_buffer(pcm,
|
||||
SNDRV_PCM_STREAM_CAPTURE);
|
||||
if (ret)
|
||||
goto out;
|
||||
i2s_priv->capture_substream =
|
||||
pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
|
||||
}
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void bcm63xx_pcm_free_dma_buffers(struct snd_soc_component *component,
|
||||
struct snd_pcm *pcm)
|
||||
{
|
||||
int stream;
|
||||
struct snd_dma_buffer *buf;
|
||||
struct snd_pcm_substream *substream;
|
||||
|
||||
for (stream = 0; stream < 2; stream++) {
|
||||
substream = pcm->streams[stream].substream;
|
||||
if (!substream)
|
||||
continue;
|
||||
buf = &substream->dma_buffer;
|
||||
if (!buf->area)
|
||||
continue;
|
||||
dma_free_wc(pcm->card->dev, buf->bytes,
|
||||
buf->area, buf->addr);
|
||||
buf->area = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct snd_soc_component_driver bcm63xx_soc_platform = {
|
||||
.open = bcm63xx_pcm_open,
|
||||
.close = bcm63xx_pcm_close,
|
||||
.hw_params = bcm63xx_pcm_hw_params,
|
||||
.hw_free = bcm63xx_pcm_hw_free,
|
||||
.prepare = bcm63xx_pcm_prepare,
|
||||
.trigger = bcm63xx_pcm_trigger,
|
||||
.pointer = bcm63xx_pcm_pointer,
|
||||
.mmap = bcm63xx_pcm_mmap,
|
||||
.pcm_construct = bcm63xx_soc_pcm_new,
|
||||
.pcm_destruct = bcm63xx_pcm_free_dma_buffers,
|
||||
};
|
||||
|
||||
int bcm63xx_soc_platform_probe(struct platform_device *pdev,
|
||||
struct bcm_i2s_priv *i2s_priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
i2s_priv->r_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!i2s_priv->r_irq) {
|
||||
dev_err(&pdev->dev, "Unable to get register irq resource.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, i2s_priv->r_irq->start, i2s_dma_isr,
|
||||
i2s_priv->r_irq->flags, "i2s_dma", (void *)i2s_priv);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"i2s_init: failed to request interrupt.ret=%d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return devm_snd_soc_register_component(&pdev->dev,
|
||||
&bcm63xx_soc_platform, NULL, 0);
|
||||
}
|
||||
|
||||
int bcm63xx_soc_platform_remove(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
MODULE_AUTHOR("Kevin,Li <kevin-ke.li@broadcom.com>");
|
||||
MODULE_DESCRIPTION("Broadcom DSL XPON ASOC PCM Interface");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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