omap2+: Use dmtimer macros for clockevent
This patch makes timer-gp.c to use only a subset of dmtimer functions without the need to initialize dmtimer code early. Also note that now with the inline functions, timer_set_next_event becomes more efficient in the lines of assembly code. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
This commit is contained in:
Tony Lindgren
Родитель
caf64f2fdc
Коммит
aa56188998
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@ -45,10 +45,33 @@
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#include "timer-gp.h"
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/* Parent clocks, eventually these will come from the clock framework */
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#define OMAP2_MPU_SOURCE "sys_ck"
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#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
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#define OMAP4_MPU_SOURCE "sys_clkin_ck"
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#define OMAP2_32K_SOURCE "func_32k_ck"
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#define OMAP3_32K_SOURCE "omap_32k_fck"
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#define OMAP4_32K_SOURCE "sys_32k_ck"
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#ifdef CONFIG_OMAP_32K_TIMER
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#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
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#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
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#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
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#define OMAP3_SECURE_TIMER 12
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#else
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#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
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#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
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#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
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#define OMAP3_SECURE_TIMER 1
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#endif
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/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
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#define MAX_GPTIMER_ID 12
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/* Clockevent code */
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static struct omap_dm_timer clkev;
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static struct omap_dm_timer *gptimer;
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static struct clock_event_device clockevent_gpt;
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static u8 __initdata gptimer_id = 1;
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@ -57,10 +80,9 @@ struct omap_dm_timer *gptimer_wakeup;
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static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
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{
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struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
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struct clock_event_device *evt = &clockevent_gpt;
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omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
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__omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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@ -75,7 +97,8 @@ static struct irqaction omap2_gp_timer_irq = {
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static int omap2_gp_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
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__omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
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0xffffffff - cycles, 1);
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return 0;
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}
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@ -85,13 +108,18 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
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{
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u32 period;
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omap_dm_timer_stop(gptimer);
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__omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
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period = clkev.rate / HZ;
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period -= 1;
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omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
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/* Looks like we need to first set the load value separately */
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__omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
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0xffffffff - period, 1);
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__omap_dm_timer_load_start(clkev.io_base,
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OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
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0xffffffff - period, 1);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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@ -130,43 +158,89 @@ int __init omap2_gp_clockevent_set_gptimer(u8 id)
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return 0;
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}
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static void __init omap2_gp_clockevent_init(void)
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static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
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int gptimer_id,
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const char *fck_source)
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{
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u32 tick_rate;
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int src;
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char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
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char name[10]; /* 10 = sizeof("gptXX_Xck0") */
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struct omap_hwmod *oh;
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size_t size;
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int res = 0;
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inited = 1;
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sprintf(name, "timer%d", gptimer_id);
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omap_hwmod_setup_one(name);
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oh = omap_hwmod_lookup(name);
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if (!oh)
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return -ENODEV;
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sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
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omap_hwmod_setup_one(clockevent_hwmod_name);
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timer->irq = oh->mpu_irqs[0].irq;
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timer->phys_base = oh->slaves[0]->addr->pa_start;
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size = oh->slaves[0]->addr->pa_end - timer->phys_base;
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/* Static mapping, never released */
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timer->io_base = ioremap(timer->phys_base, size);
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if (!timer->io_base)
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return -ENXIO;
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/* After the dmtimer is using hwmod these clocks won't be needed */
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sprintf(name, "gpt%d_fck", gptimer_id);
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timer->fclk = clk_get(NULL, name);
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if (IS_ERR(timer->fclk))
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return -ENODEV;
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sprintf(name, "gpt%d_ick", gptimer_id);
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timer->iclk = clk_get(NULL, name);
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if (IS_ERR(timer->iclk)) {
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clk_put(timer->fclk);
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return -ENODEV;
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}
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omap_hwmod_enable(oh);
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if (gptimer_id != 12) {
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struct clk *src;
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src = clk_get(NULL, fck_source);
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if (IS_ERR(src)) {
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res = -EINVAL;
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} else {
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res = __omap_dm_timer_set_source(timer->fclk, src);
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if (IS_ERR_VALUE(res))
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pr_warning("%s: timer%i cannot set source\n",
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__func__, gptimer_id);
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clk_put(src);
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}
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}
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__omap_dm_timer_reset(timer->io_base, 1, 1);
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timer->posted = 1;
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timer->rate = clk_get_rate(timer->fclk);
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timer->reserved = 1;
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gptimer = omap_dm_timer_request_specific(gptimer_id);
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BUG_ON(gptimer == NULL);
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gptimer_wakeup = gptimer;
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#if defined(CONFIG_OMAP_32K_TIMER)
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src = OMAP_TIMER_SRC_32_KHZ;
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#else
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src = OMAP_TIMER_SRC_SYS_CLK;
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WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
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"secure 32KiHz clock source\n");
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#endif
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return res;
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}
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if (gptimer_id != 12)
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WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
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"timer-gp: omap_dm_timer_set_source() failed\n");
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static void __init omap2_gp_clockevent_init(int gptimer_id,
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const char *fck_source)
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{
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int res;
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tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
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inited = 1;
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pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
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gptimer_id, tick_rate);
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res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
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BUG_ON(res);
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omap2_gp_timer_irq.dev_id = (void *)gptimer;
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setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
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omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
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setup_irq(clkev.irq, &omap2_gp_timer_irq);
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clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
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__omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
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clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
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clockevent_gpt.shift);
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clockevent_gpt.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &clockevent_gpt);
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@ -176,6 +250,9 @@ static void __init omap2_gp_clockevent_init(void)
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clockevent_gpt.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_gpt);
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pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
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gptimer_id, clkev.rate);
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}
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/* Clocksource code */
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@ -247,11 +324,11 @@ static void __init omap2_gp_clocksource_init(void)
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}
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#endif
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#define OMAP_SYS_TIMER_INIT(name) \
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#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src) \
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static void __init omap##name##_timer_init(void) \
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{ \
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omap_dm_timer_init(); \
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omap2_gp_clockevent_init(); \
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omap2_gp_clockevent_init((clkev_nr), clkev_src); \
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omap2_gp_clocksource_init(); \
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}
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@ -261,14 +338,14 @@ struct sys_timer omap##name##_timer = { \
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};
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#ifdef CONFIG_ARCH_OMAP2
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OMAP_SYS_TIMER_INIT(2)
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OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE)
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OMAP_SYS_TIMER(2)
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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OMAP_SYS_TIMER_INIT(3)
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OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE)
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OMAP_SYS_TIMER(3)
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OMAP_SYS_TIMER_INIT(3_secure)
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OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE)
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OMAP_SYS_TIMER(3_secure)
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#endif
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@ -280,7 +357,7 @@ static void __init omap4_timer_init(void)
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BUG_ON(!twd_base);
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#endif
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omap_dm_timer_init();
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omap2_gp_clockevent_init();
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omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
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omap2_gp_clocksource_init();
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}
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OMAP_SYS_TIMER(4)
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@ -216,6 +216,7 @@ struct omap_dm_timer {
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struct clk *iclk, *fclk;
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#endif
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void __iomem *io_base;
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unsigned long rate;
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unsigned reserved:1;
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unsigned enabled:1;
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unsigned posted:1;
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