drm: imx: imx-hdmi: split phy configuration to platform driver
hdmi phy configuration is platform specific, which can be adjusted according to the board to get the best SI Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Andy Yan
Philipp Zabel
Родитель
3d1b35a3d9
Коммит
aaa757a092
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@ -713,76 +713,14 @@ static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable)
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HDMI_PHY_CONF0_SELDIPIF_MASK);
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}
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enum {
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RES_8,
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RES_10,
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RES_12,
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RES_MAX,
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};
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struct mpll_config {
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unsigned long mpixelclock;
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struct {
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u16 cpce;
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u16 gmp;
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} res[RES_MAX];
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};
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static const struct mpll_config mpll_config[] = {
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{
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45250000, {
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{ 0x01e0, 0x0000 },
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{ 0x21e1, 0x0000 },
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{ 0x41e2, 0x0000 }
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},
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}, {
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92500000, {
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{ 0x0140, 0x0005 },
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{ 0x2141, 0x0005 },
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{ 0x4142, 0x0005 },
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},
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}, {
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148500000, {
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{ 0x00a0, 0x000a },
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{ 0x20a1, 0x000a },
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{ 0x40a2, 0x000a },
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},
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}, {
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~0UL, {
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{ 0x00a0, 0x000a },
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{ 0x2001, 0x000f },
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{ 0x4002, 0x000f },
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},
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}
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};
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struct curr_ctrl {
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unsigned long mpixelclock;
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u16 curr[RES_MAX];
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};
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static const struct curr_ctrl curr_ctrl[] = {
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/* pixelclk bpp8 bpp10 bpp12 */
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{
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54000000, { 0x091c, 0x091c, 0x06dc },
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}, {
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58400000, { 0x091c, 0x06dc, 0x06dc },
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}, {
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72000000, { 0x06dc, 0x06dc, 0x091c },
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}, {
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74250000, { 0x06dc, 0x0b5c, 0x091c },
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}, {
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118800000, { 0x091c, 0x091c, 0x06dc },
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}, {
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216000000, { 0x06dc, 0x0b5c, 0x091c },
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}
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};
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static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
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unsigned char res, int cscon)
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{
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unsigned res_idx, i;
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u8 val, msec;
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const struct mpll_config *mpll_config = hdmi->plat_data->mpll_cfg;
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const struct curr_ctrl *curr_ctrl = hdmi->plat_data->cur_ctr;
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const struct sym_term *sym_term = hdmi->plat_data->sym_term;
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if (prep)
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return -EINVAL;
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@ -828,7 +766,7 @@ static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
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hdmi_phy_test_clear(hdmi, 0);
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/* PLL/MPLL Cfg - always match on final entry */
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for (i = 0; i < ARRAY_SIZE(mpll_config) - 1; i++)
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for (i = 0; mpll_config[i].mpixelclock != (~0UL); i++)
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if (hdmi->hdmi_data.video_mode.mpixelclock <=
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mpll_config[i].mpixelclock)
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break;
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@ -836,12 +774,12 @@ static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
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hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
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hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
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for (i = 0; i < ARRAY_SIZE(curr_ctrl); i++)
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for (i = 0; curr_ctrl[i].mpixelclock != (~0UL); i++)
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if (hdmi->hdmi_data.video_mode.mpixelclock <=
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curr_ctrl[i].mpixelclock)
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break;
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if (i >= ARRAY_SIZE(curr_ctrl)) {
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if (curr_ctrl[i].mpixelclock == (~0UL)) {
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dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
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hdmi->hdmi_data.video_mode.mpixelclock);
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return -EINVAL;
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@ -852,10 +790,17 @@ static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
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hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
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hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
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for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)
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if (hdmi->hdmi_data.video_mode.mpixelclock <=
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sym_term[i].mpixelclock)
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break;
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/* RESISTANCE TERM 133Ohm Cfg */
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hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */
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hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19); /* TXTERM */
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/* PREEMP Cgf 0.00 */
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hdmi_phy_i2c_write(hdmi, 0x800d, 0x09); /* CKSYMTXCTRL */
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hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
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/* TX/CK LVL 10 */
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hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
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/* REMOVE CLK TERM */
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@ -1037,6 +1037,35 @@ enum imx_hdmi_devtype {
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struct imx_hdmi_plat_data {
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enum imx_hdmi_devtype dev_type;
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const struct mpll_config *mpll_cfg;
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const struct curr_ctrl *cur_ctr;
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const struct sym_term *sym_term;
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};
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enum {
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RES_8,
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RES_10,
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RES_12,
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RES_MAX,
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};
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struct mpll_config {
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unsigned long mpixelclock;
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struct {
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u16 cpce;
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u16 gmp;
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} res[RES_MAX];
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};
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struct curr_ctrl {
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unsigned long mpixelclock;
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u16 curr[RES_MAX];
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};
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struct sym_term {
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unsigned long mpixelclock;
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u16 sym_ctr; /*clock symbol and transmitter control*/
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u16 term; /*transmission termination value*/
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};
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int imx_hdmi_bind(struct device *dev, struct device *master,
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@ -28,6 +28,57 @@ struct imx_hdmi_priv {
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struct regmap *regmap;
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};
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static const struct mpll_config imx_mpll_cfg[] = {
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{
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45250000, {
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{ 0x01e0, 0x0000 },
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{ 0x21e1, 0x0000 },
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{ 0x41e2, 0x0000 }
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},
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}, {
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92500000, {
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{ 0x0140, 0x0005 },
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{ 0x2141, 0x0005 },
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{ 0x4142, 0x0005 },
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},
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}, {
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148500000, {
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{ 0x00a0, 0x000a },
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{ 0x20a1, 0x000a },
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{ 0x40a2, 0x000a },
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},
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}, {
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~0UL, {
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{ 0x00a0, 0x000a },
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{ 0x2001, 0x000f },
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{ 0x4002, 0x000f },
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},
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}
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};
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static const struct curr_ctrl imx_cur_ctr[] = {
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/* pixelclk bpp8 bpp10 bpp12 */
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{
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54000000, { 0x091c, 0x091c, 0x06dc },
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}, {
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58400000, { 0x091c, 0x06dc, 0x06dc },
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}, {
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72000000, { 0x06dc, 0x06dc, 0x091c },
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}, {
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74250000, { 0x06dc, 0x0b5c, 0x091c },
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}, {
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118800000, { 0x091c, 0x091c, 0x06dc },
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}, {
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216000000, { 0x06dc, 0x0b5c, 0x091c },
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}
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};
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static const struct sym_term imx_sym_term[] = {
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/*pixelclk symbol term*/
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{ 148500000, 0x800d, 0x0005 },
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{ ~0UL, 0x0000, 0x0000 }
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};
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static int imx_hdmi_parse_dt(struct imx_hdmi_priv *hdmi)
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{
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struct device_node *np = hdmi->dev->of_node;
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@ -88,10 +139,16 @@ static struct drm_encoder_funcs imx_hdmi_encoder_funcs = {
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};
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static struct imx_hdmi_plat_data imx6q_hdmi_drv_data = {
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.mpll_cfg = imx_mpll_cfg,
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.cur_ctr = imx_cur_ctr,
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.sym_term = imx_sym_term,
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.dev_type = IMX6Q_HDMI,
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};
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static struct imx_hdmi_plat_data imx6dl_hdmi_drv_data = {
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.mpll_cfg = imx_mpll_cfg,
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.cur_ctr = imx_cur_ctr,
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.sym_term = imx_sym_term,
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.dev_type = IMX6DL_HDMI,
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};
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