iwlwifi: document keep-warm buffer
Document keep-warm buffer Consolidate flow handler address definitions Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1282,20 +1282,37 @@ enum {
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/********************* END TXPOWER *****************************************/
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/****************************/
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/* Flow Handler Definitions */
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/****************************/
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/**********************/
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/* Addresses */
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/**********************/
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/*
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* This I/O area is directly read/writable by driver (e.g. Linux uses writel())
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* Addresses are offsets from device's PCI hardware base address.
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*/
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#define FH_MEM_LOWER_BOUND (0x1000)
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#define FH_MEM_UPPER_BOUND (0x1EF0)
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#define IWL_FH_REGS_LOWER_BOUND (0x1000)
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#define IWL_FH_REGS_UPPER_BOUND (0x2000)
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/**
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* Keep-Warm (KW) buffer base address.
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*
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* Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
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* host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
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* DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
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* from going into a power-savings mode that would cause higher DRAM latency,
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* and possible data over/under-runs, before all Tx/Rx is complete.
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*
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* Driver loads IWL_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
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* of the buffer, which must be 4K aligned. Once this is set up, the 4965
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* automatically invokes keep-warm accesses when normal accesses might not
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* be sufficient to maintain fast DRAM response.
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*
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* Bit fields:
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* 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
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*/
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#define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
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/* CBBC Area - Circular buffers base address cache pointers table */
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#define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
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#define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
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@ -1326,16 +1343,16 @@ enum {
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#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008)
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/* TCSR */
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#define IWL_FH_TCSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xD00)
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#define IWL_FH_TCSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xE60)
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#define IWL_FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
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#define IWL_FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
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#define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
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(IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
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/* TSSR Area - Tx shared status registers */
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/* TSSR */
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#define IWL_FH_TSSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEA0)
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#define IWL_FH_TSSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEC0)
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#define IWL_FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
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#define IWL_FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
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#define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010)
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