drm/i915: Add DP training pattern 3 for CHV
CHV supports DP training pattern 3. Add the required stuff. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Родитель
a5043453aa
Коммит
aad3d14d25
drivers/gpu/drm/i915
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@ -3489,6 +3489,8 @@ enum punit_power_well {
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#define DP_LINK_TRAIN_OFF (3 << 28)
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#define DP_LINK_TRAIN_OFF (3 << 28)
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#define DP_LINK_TRAIN_MASK (3 << 28)
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#define DP_LINK_TRAIN_MASK (3 << 28)
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#define DP_LINK_TRAIN_SHIFT 28
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#define DP_LINK_TRAIN_SHIFT 28
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#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
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#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
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/* CPT Link training mode */
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/* CPT Link training mode */
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#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
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#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
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@ -2959,6 +2959,9 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
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}
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}
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} else {
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} else {
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if (IS_CHERRYVIEW(dev))
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*DP &= ~DP_LINK_TRAIN_MASK_CHV;
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else
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*DP &= ~DP_LINK_TRAIN_MASK;
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*DP &= ~DP_LINK_TRAIN_MASK;
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switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
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switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
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@ -2972,8 +2975,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
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*DP |= DP_LINK_TRAIN_PAT_2;
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*DP |= DP_LINK_TRAIN_PAT_2;
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break;
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break;
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case DP_TRAINING_PATTERN_3:
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case DP_TRAINING_PATTERN_3:
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if (IS_CHERRYVIEW(dev)) {
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*DP |= DP_LINK_TRAIN_PAT_3_CHV;
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} else {
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DRM_ERROR("DP training pattern 3 not supported\n");
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DRM_ERROR("DP training pattern 3 not supported\n");
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*DP |= DP_LINK_TRAIN_PAT_2;
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*DP |= DP_LINK_TRAIN_PAT_2;
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}
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break;
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break;
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}
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}
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}
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}
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@ -3260,6 +3267,9 @@ intel_dp_link_down(struct intel_dp *intel_dp)
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DP &= ~DP_LINK_TRAIN_MASK_CPT;
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DP &= ~DP_LINK_TRAIN_MASK_CPT;
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I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
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I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
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} else {
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} else {
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if (IS_CHERRYVIEW(dev))
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DP &= ~DP_LINK_TRAIN_MASK_CHV;
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else
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DP &= ~DP_LINK_TRAIN_MASK;
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DP &= ~DP_LINK_TRAIN_MASK;
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I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
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I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
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}
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}
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