net: dsa: qca8k: handle error with qca8k_rmw operation
qca8k_rmw can fail. Rework any user to handle error values and correctly return. Change qca8k_rmw to return the error code or 0 instead of the reg value. The reg returned by qca8k_rmw wasn't used anywhere, so this doesn't cause any functional change. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ansuel Smith
David S. Miller
Родитель
d7805757c7
Коммит
aaf421425c
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@ -190,12 +190,13 @@ exit:
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return ret;
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}
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static u32
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qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
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static int
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qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
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{
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struct mii_bus *bus = priv->bus;
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u16 r1, r2, page;
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u32 ret;
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u32 val;
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int ret;
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qca8k_split_addr(reg, &r1, &r2, &page);
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@ -205,10 +206,15 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
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if (ret < 0)
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goto exit;
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ret = qca8k_mii_read32(bus, 0x10 | r2, r1);
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ret &= ~mask;
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ret |= val;
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qca8k_mii_write32(bus, 0x10 | r2, r1, ret);
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val = qca8k_mii_read32(bus, 0x10 | r2, r1);
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if (val < 0) {
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ret = val;
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goto exit;
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}
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val &= ~mask;
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val |= write_val;
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qca8k_mii_write32(bus, 0x10 | r2, r1, val);
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exit:
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mutex_unlock(&bus->mdio_lock);
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@ -216,16 +222,16 @@ exit:
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return ret;
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}
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static void
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static int
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qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
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{
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qca8k_rmw(priv, reg, 0, val);
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return qca8k_rmw(priv, reg, 0, val);
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}
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static void
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static int
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qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
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{
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qca8k_rmw(priv, reg, val, 0);
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return qca8k_rmw(priv, reg, val, 0);
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}
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static int
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@ -570,12 +576,19 @@ qca8k_mib_init(struct qca8k_priv *priv)
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int ret;
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mutex_lock(&priv->reg_mutex);
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qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
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ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
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if (ret)
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goto exit;
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qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
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qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
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ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
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if (ret)
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goto exit;
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ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
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exit:
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mutex_unlock(&priv->reg_mutex);
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return ret;
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}
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@ -747,9 +760,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv)
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* a dt-overlay and driver reload changed the configuration
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*/
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qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_EN);
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return 0;
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return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_EN);
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}
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priv->ops.phy_read = qca8k_phy_read;
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@ -782,8 +794,12 @@ qca8k_setup(struct dsa_switch *ds)
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return ret;
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/* Enable CPU Port */
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qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
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QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
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ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
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QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
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if (ret) {
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dev_err(priv->dev, "failed enabling CPU port");
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return ret;
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}
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/* Enable MIB counters */
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ret = qca8k_mib_init(priv);
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@ -800,9 +816,12 @@ qca8k_setup(struct dsa_switch *ds)
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}
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/* Disable forwarding by default on all ports */
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for (i = 0; i < QCA8K_NUM_PORTS; i++)
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qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER, 0);
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for (i = 0; i < QCA8K_NUM_PORTS; i++) {
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER, 0);
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if (ret)
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return ret;
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}
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/* Disable MAC by default on all ports */
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for (i = 1; i < QCA8K_NUM_PORTS; i++)
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@ -821,28 +840,37 @@ qca8k_setup(struct dsa_switch *ds)
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for (i = 0; i < QCA8K_NUM_PORTS; i++) {
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/* CPU port gets connected to all user ports of the switch */
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if (dsa_is_cpu_port(ds, i)) {
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qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
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QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
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QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
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if (ret)
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return ret;
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}
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/* Individual user ports get connected to CPU port only */
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if (dsa_is_user_port(ds, i)) {
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int shift = 16 * (i % 2);
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qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER,
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BIT(QCA8K_CPU_PORT));
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER,
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BIT(QCA8K_CPU_PORT));
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if (ret)
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return ret;
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/* Enable ARP Auto-learning by default */
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qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_LEARN);
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ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_LEARN);
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if (ret)
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return ret;
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/* For port based vlans to work we need to set the
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* default egress vid
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*/
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qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
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0xfff << shift,
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QCA8K_PORT_VID_DEF << shift);
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ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
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0xfff << shift,
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QCA8K_PORT_VID_DEF << shift);
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if (ret)
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return ret;
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ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
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QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
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QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
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@ -1234,7 +1262,7 @@ qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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int port_mask = BIT(QCA8K_CPU_PORT);
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int i;
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int i, ret;
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for (i = 1; i < QCA8K_NUM_PORTS; i++) {
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if (dsa_to_port(ds, i)->bridge_dev != br)
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@ -1242,17 +1270,20 @@ qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
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/* Add this port to the portvlan mask of the other ports
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* in the bridge
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*/
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qca8k_reg_set(priv,
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QCA8K_PORT_LOOKUP_CTRL(i),
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BIT(port));
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ret = qca8k_reg_set(priv,
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QCA8K_PORT_LOOKUP_CTRL(i),
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BIT(port));
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if (ret)
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return ret;
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if (i != port)
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port_mask |= BIT(i);
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}
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/* Add all other ports to this ports portvlan mask */
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qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
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QCA8K_PORT_LOOKUP_MEMBER, port_mask);
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return 0;
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/* Add all other ports to this ports portvlan mask */
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
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QCA8K_PORT_LOOKUP_MEMBER, port_mask);
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return ret;
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}
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static void
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@ -1389,18 +1420,19 @@ qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
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struct netlink_ext_ack *extack)
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{
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struct qca8k_priv *priv = ds->priv;
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int ret;
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if (vlan_filtering) {
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qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
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QCA8K_PORT_LOOKUP_VLAN_MODE,
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QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
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QCA8K_PORT_LOOKUP_VLAN_MODE,
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QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
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} else {
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qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
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QCA8K_PORT_LOOKUP_VLAN_MODE,
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QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
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ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
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QCA8K_PORT_LOOKUP_VLAN_MODE,
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QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
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}
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return 0;
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return ret;
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}
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static int
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@ -1422,16 +1454,17 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port,
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if (pvid) {
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int shift = 16 * (port % 2);
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qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
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0xfff << shift, vlan->vid << shift);
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ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
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0xfff << shift, vlan->vid << shift);
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if (ret)
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return ret;
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ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
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QCA8K_PORT_VLAN_CVID(vlan->vid) |
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QCA8K_PORT_VLAN_SVID(vlan->vid));
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if (ret)
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return ret;
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}
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return 0;
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return ret;
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}
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static int
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