Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "This contains fixes for exynos, amdgpu, radeon, i915 and qxl. It also contains some fixes to the core drm edid parser. qxl: - fix for a cursor hotspot issue radeon: - some MST fixes that I've been running locally and make my monitor a bit happier exynos: - fix some regressions and build fixes amdgpu: - a couple of small fixes i915: - two DP MST fixes and a couple of other regression fixes Nothing too out of the ordinary or surprising at this point" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/exynos: Use VIDEO_SAMSUNG_S5P_G2D=n as G2D Kconfig dependency drm/exynos: fix a warning message drm/exynos: mic: fix an error code drm/exynos: fimd: fix broken dp_clock control drm/exynos: build fbdev code conditionally drm/exynos: fix adjusted_mode pointer in exynos_plane_mode_set drm/exynos: fix error handling in exynos_drm_subdrv_open drm/amd/amdgpu: fix irq domain remove for tonga ih drm/i915: fix deadlock on lid open drm/radeon: use helper for mst connector dpms. drm/radeon/mst: port some MST setup code from DAL. drm/amdgpu: add invisible pin size statistic drm/edid: Fix DMT 1024x768@43Hz (interlaced) timings drm/i915: Exit cherryview_irq_handler() after one pass drm/i915: Call intel_dp_mst_resume() before resuming displays drm/i915: Fix race condition in intel_dp_destroy_mst_connector() drm/edid: Fix parsing of EDID 1.4 Established Timings III descriptor drm/edid: Fix EDID Established Timings I and II drm/qxl: fix cursor position with non-zero hotspot
This commit is contained in:
Коммит
ab5f9ebac1
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@ -2034,6 +2034,7 @@ struct amdgpu_device {
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/* tracking pinned memory */
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u64 vram_pin_size;
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u64 invisible_pin_size;
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u64 gart_pin_size;
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/* amdkfd interface */
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@ -384,7 +384,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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vram_gtt.vram_size = adev->mc.real_vram_size;
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vram_gtt.vram_size -= adev->vram_pin_size;
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vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
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vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
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vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
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vram_gtt.gtt_size = adev->mc.gtt_size;
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vram_gtt.gtt_size -= adev->gart_pin_size;
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return copy_to_user(out, &vram_gtt,
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@ -424,9 +424,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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bo->pin_count = 1;
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if (gpu_addr != NULL)
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*gpu_addr = amdgpu_bo_gpu_offset(bo);
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if (domain == AMDGPU_GEM_DOMAIN_VRAM)
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if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
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bo->adev->vram_pin_size += amdgpu_bo_size(bo);
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else
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if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
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bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
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} else
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bo->adev->gart_pin_size += amdgpu_bo_size(bo);
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} else {
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dev_err(bo->adev->dev, "%p pin failed\n", bo);
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@ -456,9 +458,11 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
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}
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r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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if (likely(r == 0)) {
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if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
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if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
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bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
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else
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if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
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bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
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} else
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bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
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} else {
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dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
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@ -307,7 +307,7 @@ static int tonga_ih_sw_fini(void *handle)
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amdgpu_irq_fini(adev);
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amdgpu_ih_ring_fini(adev);
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amdgpu_irq_add_domain(adev);
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amdgpu_irq_remove_domain(adev);
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return 0;
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}
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@ -205,7 +205,7 @@ static const struct drm_display_mode drm_dmt_modes[] = {
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
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/* 0x0f - 1024x768@43Hz, interlace */
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{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
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1208, 1264, 0, 768, 768, 772, 817, 0,
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1208, 1264, 0, 768, 768, 776, 817, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
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DRM_MODE_FLAG_INTERLACE) },
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/* 0x10 - 1024x768@60Hz */
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@ -522,12 +522,12 @@ static const struct drm_display_mode edid_est_modes[] = {
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720, 840, 0, 480, 481, 484, 500, 0,
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DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
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{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
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704, 832, 0, 480, 489, 491, 520, 0,
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704, 832, 0, 480, 489, 492, 520, 0,
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DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
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{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
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768, 864, 0, 480, 483, 486, 525, 0,
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DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
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{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
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{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
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752, 800, 0, 480, 490, 492, 525, 0,
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DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
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{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
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@ -539,7 +539,7 @@ static const struct drm_display_mode edid_est_modes[] = {
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{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
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1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
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{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
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{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
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1136, 1312, 0, 768, 769, 772, 800, 0,
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DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
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{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
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@ -2241,7 +2241,7 @@ drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
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{
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int i, j, m, modes = 0;
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struct drm_display_mode *mode;
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u8 *est = ((u8 *)timing) + 5;
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u8 *est = ((u8 *)timing) + 6;
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for (i = 0; i < 6; i++) {
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for (j = 7; j >= 0; j--) {
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@ -94,7 +94,7 @@ comment "Sub-drivers"
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config DRM_EXYNOS_G2D
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bool "G2D"
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depends on !VIDEO_SAMSUNG_S5P_G2D
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depends on VIDEO_SAMSUNG_S5P_G2D=n
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select FRAME_VECTOR
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help
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Choose this option if you want to use Exynos G2D for DRM.
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@ -2,10 +2,10 @@
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# Makefile for the drm device driver. This driver provides support for the
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# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
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exynosdrm-y := exynos_drm_drv.o exynos_drm_crtc.o exynos_drm_fbdev.o \
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exynos_drm_fb.o exynos_drm_gem.o exynos_drm_core.o \
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exynos_drm_plane.o
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exynosdrm-y := exynos_drm_drv.o exynos_drm_crtc.o exynos_drm_fb.o \
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exynos_drm_gem.o exynos_drm_core.o exynos_drm_plane.o
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exynosdrm-$(CONFIG_DRM_FBDEV_EMULATION) += exynos_drm_fbdev.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_IOMMU) += exynos_drm_iommu.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_FIMD) += exynos_drm_fimd.o
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exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON) += exynos5433_drm_decon.o
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@ -101,7 +101,7 @@ int exynos_drm_subdrv_open(struct drm_device *dev, struct drm_file *file)
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return 0;
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err:
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list_for_each_entry_reverse(subdrv, &subdrv->list, list) {
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list_for_each_entry_continue_reverse(subdrv, &exynos_drm_subdrv_list, list) {
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if (subdrv->close)
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subdrv->close(dev, subdrv->dev, file);
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}
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@ -199,17 +199,6 @@ dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index)
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return exynos_fb->dma_addr[index];
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}
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static void exynos_drm_output_poll_changed(struct drm_device *dev)
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{
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struct exynos_drm_private *private = dev->dev_private;
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struct drm_fb_helper *fb_helper = private->fb_helper;
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if (fb_helper)
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drm_fb_helper_hotplug_event(fb_helper);
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else
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exynos_drm_fbdev_init(dev);
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}
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static const struct drm_mode_config_funcs exynos_drm_mode_config_funcs = {
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.fb_create = exynos_user_fb_create,
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.output_poll_changed = exynos_drm_output_poll_changed,
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@ -317,3 +317,14 @@ void exynos_drm_fbdev_restore_mode(struct drm_device *dev)
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drm_fb_helper_restore_fbdev_mode_unlocked(private->fb_helper);
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}
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void exynos_drm_output_poll_changed(struct drm_device *dev)
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{
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struct exynos_drm_private *private = dev->dev_private;
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struct drm_fb_helper *fb_helper = private->fb_helper;
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if (fb_helper)
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drm_fb_helper_hotplug_event(fb_helper);
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else
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exynos_drm_fbdev_init(dev);
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}
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@ -15,9 +15,30 @@
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#ifndef _EXYNOS_DRM_FBDEV_H_
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#define _EXYNOS_DRM_FBDEV_H_
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#ifdef CONFIG_DRM_FBDEV_EMULATION
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int exynos_drm_fbdev_init(struct drm_device *dev);
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int exynos_drm_fbdev_reinit(struct drm_device *dev);
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void exynos_drm_fbdev_fini(struct drm_device *dev);
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void exynos_drm_fbdev_restore_mode(struct drm_device *dev);
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void exynos_drm_output_poll_changed(struct drm_device *dev);
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#else
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static inline int exynos_drm_fbdev_init(struct drm_device *dev)
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{
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return 0;
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}
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static inline void exynos_drm_fbdev_fini(struct drm_device *dev)
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{
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}
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static inline void exynos_drm_fbdev_restore_mode(struct drm_device *dev)
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{
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}
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#define exynos_drm_output_poll_changed (NULL)
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#endif
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#endif
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@ -888,7 +888,7 @@ static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
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* clock. On these SoCs the bootloader may enable it but any
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* power domain off/on will reset it to disable state.
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*/
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if (ctx->driver_data != &exynos5_fimd_driver_data ||
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if (ctx->driver_data != &exynos5_fimd_driver_data &&
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ctx->driver_data != &exynos5420_fimd_driver_data)
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return;
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|
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@ -129,7 +129,7 @@ static void mic_set_path(struct exynos_mic *mic, bool enable)
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} else
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val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX);
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regmap_write(mic->sysreg, DSD_CFG_MUX, val);
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ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val);
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if (ret)
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DRM_ERROR("mic: Failed to read system register\n");
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}
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|
@ -457,6 +457,7 @@ static int exynos_mic_probe(struct platform_device *pdev)
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"samsung,disp-syscon");
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if (IS_ERR(mic->sysreg)) {
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DRM_ERROR("mic: Failed to get system register.\n");
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ret = PTR_ERR(mic->sysreg);
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goto err;
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}
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|
|
|
@ -11,9 +11,10 @@
|
|||
|
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#include <drm/drmP.h>
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|
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#include <drm/exynos_drm.h>
|
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#include <drm/drm_plane_helper.h>
|
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#include <drm/drm_atomic.h>
|
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#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_plane_helper.h>
|
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#include <drm/exynos_drm.h>
|
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#include "exynos_drm_drv.h"
|
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#include "exynos_drm_crtc.h"
|
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#include "exynos_drm_fb.h"
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|
@ -57,11 +58,12 @@ static int exynos_plane_get_size(int start, unsigned length, unsigned last)
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}
|
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|
||||
static void exynos_plane_mode_set(struct exynos_drm_plane_state *exynos_state)
|
||||
|
||||
{
|
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struct drm_plane_state *state = &exynos_state->base;
|
||||
struct drm_crtc *crtc = exynos_state->base.crtc;
|
||||
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
|
||||
struct drm_crtc *crtc = state->crtc;
|
||||
struct drm_crtc_state *crtc_state =
|
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drm_atomic_get_existing_crtc_state(state->state, crtc);
|
||||
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
|
||||
int crtc_x, crtc_y;
|
||||
unsigned int crtc_w, crtc_h;
|
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unsigned int src_x, src_y;
|
||||
|
|
|
@ -758,10 +758,10 @@ static int i915_drm_resume(struct drm_device *dev)
|
|||
dev_priv->display.hpd_irq_setup(dev);
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
|
||||
intel_display_resume(dev);
|
||||
|
||||
intel_dp_mst_resume(dev);
|
||||
|
||||
intel_display_resume(dev);
|
||||
|
||||
/*
|
||||
* ... but also need to make sure that hotplug processing
|
||||
* doesn't cause havoc. Like in the driver load code we don't
|
||||
|
|
|
@ -1829,7 +1829,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
|
|||
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
|
||||
disable_rpm_wakeref_asserts(dev_priv);
|
||||
|
||||
for (;;) {
|
||||
do {
|
||||
master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
|
||||
iir = I915_READ(VLV_IIR);
|
||||
|
||||
|
@ -1857,7 +1857,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
|
|||
|
||||
I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
|
||||
POSTING_READ(GEN8_MASTER_IRQ);
|
||||
}
|
||||
} while (0);
|
||||
|
||||
enable_rpm_wakeref_asserts(dev_priv);
|
||||
|
||||
|
|
|
@ -506,6 +506,8 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
|
|||
struct intel_connector *intel_connector = to_intel_connector(connector);
|
||||
struct drm_device *dev = connector->dev;
|
||||
|
||||
intel_connector->unregister(intel_connector);
|
||||
|
||||
/* need to nuke the connector */
|
||||
drm_modeset_lock_all(dev);
|
||||
if (connector->state->crtc) {
|
||||
|
@ -519,11 +521,7 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
|
|||
|
||||
WARN(ret, "Disabling mst crtc failed with %i\n", ret);
|
||||
}
|
||||
drm_modeset_unlock_all(dev);
|
||||
|
||||
intel_connector->unregister(intel_connector);
|
||||
|
||||
drm_modeset_lock_all(dev);
|
||||
intel_connector_remove_from_fbdev(intel_connector);
|
||||
drm_connector_cleanup(connector);
|
||||
drm_modeset_unlock_all(dev);
|
||||
|
|
|
@ -478,11 +478,8 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
|
|||
* and as part of the cleanup in the hw state restore we also redisable
|
||||
* the vga plane.
|
||||
*/
|
||||
if (!HAS_PCH_SPLIT(dev)) {
|
||||
drm_modeset_lock_all(dev);
|
||||
if (!HAS_PCH_SPLIT(dev))
|
||||
intel_display_resume(dev);
|
||||
drm_modeset_unlock_all(dev);
|
||||
}
|
||||
|
||||
dev_priv->modeset_restore = MODESET_DONE;
|
||||
|
||||
|
|
|
@ -375,10 +375,15 @@ static int qxl_crtc_cursor_set2(struct drm_crtc *crtc,
|
|||
|
||||
qxl_bo_kunmap(user_bo);
|
||||
|
||||
qcrtc->cur_x += qcrtc->hot_spot_x - hot_x;
|
||||
qcrtc->cur_y += qcrtc->hot_spot_y - hot_y;
|
||||
qcrtc->hot_spot_x = hot_x;
|
||||
qcrtc->hot_spot_y = hot_y;
|
||||
|
||||
cmd = (struct qxl_cursor_cmd *)qxl_release_map(qdev, release);
|
||||
cmd->type = QXL_CURSOR_SET;
|
||||
cmd->u.set.position.x = qcrtc->cur_x;
|
||||
cmd->u.set.position.y = qcrtc->cur_y;
|
||||
cmd->u.set.position.x = qcrtc->cur_x + qcrtc->hot_spot_x;
|
||||
cmd->u.set.position.y = qcrtc->cur_y + qcrtc->hot_spot_y;
|
||||
|
||||
cmd->u.set.shape = qxl_bo_physical_address(qdev, cursor_bo, 0);
|
||||
|
||||
|
@ -441,8 +446,8 @@ static int qxl_crtc_cursor_move(struct drm_crtc *crtc,
|
|||
|
||||
cmd = (struct qxl_cursor_cmd *)qxl_release_map(qdev, release);
|
||||
cmd->type = QXL_CURSOR_MOVE;
|
||||
cmd->u.position.x = qcrtc->cur_x;
|
||||
cmd->u.position.y = qcrtc->cur_y;
|
||||
cmd->u.position.x = qcrtc->cur_x + qcrtc->hot_spot_x;
|
||||
cmd->u.position.y = qcrtc->cur_y + qcrtc->hot_spot_y;
|
||||
qxl_release_unmap(qdev, release, &cmd->release_info);
|
||||
|
||||
qxl_push_cursor_ring_release(qdev, release, QXL_CMD_CURSOR, false);
|
||||
|
|
|
@ -135,6 +135,8 @@ struct qxl_crtc {
|
|||
int index;
|
||||
int cur_x;
|
||||
int cur_y;
|
||||
int hot_spot_x;
|
||||
int hot_spot_y;
|
||||
};
|
||||
|
||||
struct qxl_output {
|
||||
|
|
|
@ -109,6 +109,8 @@
|
|||
#define NI_DP_MSE_SAT2 0x7398
|
||||
|
||||
#define NI_DP_MSE_SAT_UPDATE 0x739c
|
||||
# define NI_DP_MSE_SAT_UPDATE_MASK 0x3
|
||||
# define NI_DP_MSE_16_MTP_KEEPOUT 0x100
|
||||
|
||||
#define NI_DIG_BE_CNTL 0x7140
|
||||
# define NI_DIG_FE_SOURCE_SELECT(x) (((x) & 0x7f) << 8)
|
||||
|
|
|
@ -89,8 +89,16 @@ static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
|
|||
WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
|
||||
|
||||
do {
|
||||
unsigned value1, value2;
|
||||
udelay(10);
|
||||
temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
|
||||
} while ((temp & 0x1) && retries++ < 10000);
|
||||
|
||||
value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
|
||||
value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
|
||||
|
||||
if (!value1 && !value2)
|
||||
break;
|
||||
} while (retries++ < 50);
|
||||
|
||||
if (retries == 10000)
|
||||
DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
|
||||
|
@ -150,7 +158,7 @@ static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, uint32_t y)
|
||||
static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
|
||||
{
|
||||
struct drm_device *dev = mst->base.dev;
|
||||
struct radeon_device *rdev = dev->dev_private;
|
||||
|
@ -158,6 +166,8 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
|
|||
uint32_t val, temp;
|
||||
uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
|
||||
int retries = 0;
|
||||
uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
|
||||
uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
|
||||
|
||||
val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
|
||||
|
||||
|
@ -165,6 +175,7 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
|
|||
|
||||
do {
|
||||
temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
|
||||
udelay(10);
|
||||
} while ((temp & 0x1) && (retries++ < 10000));
|
||||
|
||||
if (retries >= 10000)
|
||||
|
@ -246,14 +257,8 @@ radeon_dp_mst_connector_destroy(struct drm_connector *connector)
|
|||
kfree(radeon_connector);
|
||||
}
|
||||
|
||||
static int radeon_connector_dpms(struct drm_connector *connector, int mode)
|
||||
{
|
||||
DRM_DEBUG_KMS("\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
|
||||
.dpms = radeon_connector_dpms,
|
||||
.dpms = drm_helper_connector_dpms,
|
||||
.detect = radeon_dp_mst_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
.destroy = radeon_dp_mst_connector_destroy,
|
||||
|
@ -394,7 +399,7 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
|
|||
struct drm_crtc *crtc;
|
||||
struct radeon_crtc *radeon_crtc;
|
||||
int ret, slots;
|
||||
|
||||
s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
|
||||
if (!ASIC_IS_DCE5(rdev)) {
|
||||
DRM_ERROR("got mst dpms on non-DCE5\n");
|
||||
return;
|
||||
|
@ -456,7 +461,11 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
|
|||
|
||||
mst_enc->enc_active = true;
|
||||
radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
|
||||
radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0);
|
||||
|
||||
fixed_pbn = drm_int2fixp(mst_enc->pbn);
|
||||
fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
|
||||
avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
|
||||
radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
|
||||
|
||||
atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
|
||||
mst_enc->fe);
|
||||
|
|
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