EDAC, altera: Add Arria10 Ethernet EDAC support
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update to support a common compatibility string for all Ethernet FIFOs in the DT. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1466603939-7526-8-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
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@ -391,6 +391,13 @@ config EDAC_ALTERA_OCRAM
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Support for error detection and correction on the
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Altera On-Chip RAM Memory for Altera SoCs.
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config EDAC_ALTERA_ETHERNET
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bool "Altera Ethernet FIFO ECC"
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depends on EDAC_ALTERA=y
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help
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Support for error detection and correction on the
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Altera Ethernet FIFO Memory for Altera SoCs.
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config EDAC_SYNOPSYS
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tristate "Synopsys DDR Memory Controller"
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depends on EDAC_MM_EDAC && ARCH_ZYNQ
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@ -1258,6 +1258,33 @@ static const struct edac_device_prv_data a10_l2ecc_data = {
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#endif /* CONFIG_EDAC_ALTERA_L2C */
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/********************* Ethernet Device Functions ********************/
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#ifdef CONFIG_EDAC_ALTERA_ETHERNET
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static const struct edac_device_prv_data a10_enetecc_data = {
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.setup = altr_check_ecc_deps,
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.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
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.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
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.dbgfs_name = "altr_trigger",
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.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
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.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
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.ce_set_mask = ALTR_A10_ECC_TSERRA,
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.ue_set_mask = ALTR_A10_ECC_TDERRA,
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.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
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.ecc_irq_handler = altr_edac_a10_ecc_irq,
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.inject_fops = &altr_edac_a10_device_inject_fops,
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};
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static int __init socfpga_init_ethernet_ecc(void)
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{
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return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
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}
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early_initcall(socfpga_init_ethernet_ecc);
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#endif /* CONFIG_EDAC_ALTERA_ETHERNET */
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/********************* Arria10 EDAC Device Functions *************************/
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static const struct of_device_id altr_edac_a10_device_of_match[] = {
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#ifdef CONFIG_EDAC_ALTERA_L2C
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@ -1266,6 +1293,10 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = {
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#ifdef CONFIG_EDAC_ALTERA_OCRAM
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{ .compatible = "altr,socfpga-a10-ocram-ecc",
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.data = &a10_ocramecc_data },
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#endif
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#ifdef CONFIG_EDAC_ALTERA_ETHERNET
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{ .compatible = "altr,socfpga-eth-mac-ecc",
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.data = &a10_enetecc_data },
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#endif
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{},
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};
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@ -1555,8 +1586,10 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
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continue;
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if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc"))
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altr_edac_a10_device_add(edac, child);
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else if (of_device_is_compatible(child,
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"altr,socfpga-a10-ocram-ecc"))
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else if ((of_device_is_compatible(child,
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"altr,socfpga-a10-ocram-ecc")) ||
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(of_device_is_compatible(child,
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"altr,socfpga-eth-mac-ecc")))
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altr_edac_a10_device_add(edac, child);
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else if (of_device_is_compatible(child,
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"altr,sdram-edac-a10"))
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@ -285,6 +285,9 @@ struct altr_sdram_mc_data {
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/* Arria 10 OCRAM ECC Management Group Defines */
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#define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
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/* Arria 10 Ethernet ECC Management Group Defines */
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#define ALTR_A10_COMMON_ECC_EN_CTL BIT(0)
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/* A10 ECC Controller memory initialization timeout */
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#define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000
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