efi/cper, cxl: Decode CXL Protocol Error Section
Add support for decoding CXL Protocol Error Section as defined in UEFI 2.10 Section N.2.13. Do the section decoding in a new cper_cxl.c file. This new file will be used in the future for more CXL CPERs decode support. Add this to the existing UEFI_CPER config. Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Smita Koralahalli
Ard Biesheuvel
Родитель
d981a88c16
Коммит
abdbf1a25d
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@ -19,7 +19,7 @@ endif
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obj-$(CONFIG_EFI_PARAMS_FROM_FDT) += fdtparams.o
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obj-$(CONFIG_EFI_ESRT) += esrt.o
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obj-$(CONFIG_EFI_VARS_PSTORE) += efi-pstore.o
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obj-$(CONFIG_UEFI_CPER) += cper.o
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obj-$(CONFIG_UEFI_CPER) += cper.o cper_cxl.o
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obj-$(CONFIG_EFI_RUNTIME_WRAPPERS) += runtime-wrappers.o
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subdir-$(CONFIG_EFI_STUB) += libstub
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obj-$(CONFIG_EFI_BOOTLOADER_CONTROL) += efibc.o
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@ -24,6 +24,7 @@
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#include <linux/bcd.h>
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#include <acpi/ghes.h>
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#include <ras/ras_event.h>
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#include "cper_cxl.h"
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/*
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* CPER record ID need to be unique even after reboot, because record
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@ -595,6 +596,14 @@ cper_estatus_print_section(const char *pfx, struct acpi_hest_generic_data *gdata
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cper_print_fw_err(newpfx, gdata, fw_err);
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else
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goto err_section_too_small;
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} else if (guid_equal(sec_type, &CPER_SEC_CXL_PROT_ERR)) {
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struct cper_sec_prot_err *prot_err = acpi_hest_get_payload(gdata);
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printk("%ssection_type: CXL Protocol Error\n", newpfx);
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if (gdata->error_data_length >= sizeof(*prot_err))
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cper_print_prot_err(newpfx, prot_err);
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else
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goto err_section_too_small;
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} else {
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const void *err = acpi_hest_get_payload(gdata);
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@ -0,0 +1,152 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* UEFI Common Platform Error Record (CPER) support for CXL Section.
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*
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* Copyright (C) 2022 Advanced Micro Devices, Inc.
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*
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* Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
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*/
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#include <linux/cper.h>
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#include "cper_cxl.h"
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#define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0)
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#define PROT_ERR_VALID_AGENT_ADDRESS BIT_ULL(1)
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#define PROT_ERR_VALID_DEVICE_ID BIT_ULL(2)
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#define PROT_ERR_VALID_SERIAL_NUMBER BIT_ULL(3)
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#define PROT_ERR_VALID_CAPABILITY BIT_ULL(4)
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#define PROT_ERR_VALID_DVSEC BIT_ULL(5)
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static const char * const prot_err_agent_type_strs[] = {
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"Restricted CXL Device",
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"Restricted CXL Host Downstream Port",
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"CXL Device",
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"CXL Logical Device",
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"CXL Fabric Manager managed Logical Device",
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"CXL Root Port",
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"CXL Downstream Switch Port",
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"CXL Upstream Switch Port",
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};
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/*
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* The layout of the enumeration and the values matches CXL Agent Type
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* field in the UEFI 2.10 Section N.2.13,
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*/
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enum {
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RCD, /* Restricted CXL Device */
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RCH_DP, /* Restricted CXL Host Downstream Port */
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DEVICE, /* CXL Device */
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LD, /* CXL Logical Device */
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FMLD, /* CXL Fabric Manager managed Logical Device */
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RP, /* CXL Root Port */
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DSP, /* CXL Downstream Switch Port */
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USP, /* CXL Upstream Switch Port */
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};
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void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_err)
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{
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if (prot_err->valid_bits & PROT_ERR_VALID_AGENT_TYPE)
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pr_info("%s agent_type: %d, %s\n", pfx, prot_err->agent_type,
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prot_err->agent_type < ARRAY_SIZE(prot_err_agent_type_strs)
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? prot_err_agent_type_strs[prot_err->agent_type]
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: "unknown");
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if (prot_err->valid_bits & PROT_ERR_VALID_AGENT_ADDRESS) {
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switch (prot_err->agent_type) {
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/*
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* According to UEFI 2.10 Section N.2.13, the term CXL Device
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* is used to refer to Restricted CXL Device, CXL Device, CXL
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* Logical Device or a CXL Fabric Manager Managed Logical
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* Device.
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*/
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case RCD:
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case DEVICE:
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case LD:
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case FMLD:
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case RP:
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case DSP:
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case USP:
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pr_info("%s agent_address: %04x:%02x:%02x.%x\n",
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pfx, prot_err->agent_addr.segment,
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prot_err->agent_addr.bus,
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prot_err->agent_addr.device,
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prot_err->agent_addr.function);
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break;
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case RCH_DP:
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pr_info("%s rcrb_base_address: 0x%016llx\n", pfx,
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prot_err->agent_addr.rcrb_base_addr);
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break;
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default:
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break;
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}
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}
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if (prot_err->valid_bits & PROT_ERR_VALID_DEVICE_ID) {
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const __u8 *class_code;
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switch (prot_err->agent_type) {
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case RCD:
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case DEVICE:
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case LD:
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case FMLD:
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case RP:
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case DSP:
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case USP:
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pr_info("%s slot: %d\n", pfx,
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prot_err->device_id.slot >> CPER_PCIE_SLOT_SHIFT);
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pr_info("%s vendor_id: 0x%04x, device_id: 0x%04x\n",
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pfx, prot_err->device_id.vendor_id,
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prot_err->device_id.device_id);
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pr_info("%s sub_vendor_id: 0x%04x, sub_device_id: 0x%04x\n",
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pfx, prot_err->device_id.subsystem_vendor_id,
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prot_err->device_id.subsystem_id);
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class_code = prot_err->device_id.class_code;
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pr_info("%s class_code: %02x%02x\n", pfx,
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class_code[1], class_code[0]);
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break;
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default:
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break;
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}
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}
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if (prot_err->valid_bits & PROT_ERR_VALID_SERIAL_NUMBER) {
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switch (prot_err->agent_type) {
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case RCD:
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case DEVICE:
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case LD:
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case FMLD:
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pr_info("%s lower_dw: 0x%08x, upper_dw: 0x%08x\n", pfx,
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prot_err->dev_serial_num.lower_dw,
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prot_err->dev_serial_num.upper_dw);
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break;
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default:
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break;
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}
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}
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if (prot_err->valid_bits & PROT_ERR_VALID_CAPABILITY) {
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switch (prot_err->agent_type) {
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case RCD:
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case DEVICE:
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case LD:
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case FMLD:
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case RP:
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case DSP:
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case USP:
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print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4,
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prot_err->capability,
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sizeof(prot_err->capability), 0);
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break;
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default:
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break;
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}
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}
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if (prot_err->valid_bits & PROT_ERR_VALID_DVSEC) {
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pr_info("%s DVSEC length: 0x%04x\n", pfx, prot_err->dvsec_len);
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pr_info("%s CXL DVSEC:\n", pfx);
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print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, (prot_err + 1),
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prot_err->dvsec_len, 0);
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}
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}
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@ -0,0 +1,66 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* UEFI Common Platform Error Record (CPER) support for CXL Section.
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*
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* Copyright (C) 2022 Advanced Micro Devices, Inc.
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*
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* Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
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*/
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#ifndef LINUX_CPER_CXL_H
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#define LINUX_CPER_CXL_H
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/* CXL Protocol Error Section */
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#define CPER_SEC_CXL_PROT_ERR \
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GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78, \
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0x4B, 0x77, 0x10, 0x48)
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#pragma pack(1)
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/* Compute Express Link Protocol Error Section, UEFI v2.10 sec N.2.13 */
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struct cper_sec_prot_err {
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u64 valid_bits;
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u8 agent_type;
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u8 reserved[7];
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/*
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* Except for RCH Downstream Port, all the remaining CXL Agent
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* types are uniquely identified by the PCIe compatible SBDF number.
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*/
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union {
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u64 rcrb_base_addr;
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struct {
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u8 function;
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u8 device;
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u8 bus;
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u16 segment;
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u8 reserved_1[3];
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};
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} agent_addr;
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struct {
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u16 vendor_id;
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u16 device_id;
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u16 subsystem_vendor_id;
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u16 subsystem_id;
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u8 class_code[2];
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u16 slot;
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u8 reserved_1[4];
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} device_id;
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struct {
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u32 lower_dw;
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u32 upper_dw;
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} dev_serial_num;
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u8 capability[60];
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u16 dvsec_len;
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u16 err_len;
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u8 reserved_2[4];
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};
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#pragma pack()
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void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_err);
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#endif //__CPER_CXL_
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