Merge branch 'for-joerg/arm-smmu/updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu
This commit is contained in:
Joerg Roedel
Коммит
ac1d35659b
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@ -19,8 +19,17 @@
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#define pr_fmt(fmt) "ACPI: IORT: " fmt
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#include <linux/acpi_iort.h>
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#include <linux/iommu.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define IORT_TYPE_MASK(type) (1 << (type))
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#define IORT_MSI_TYPE (1 << ACPI_IORT_NODE_ITS_GROUP)
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#define IORT_IOMMU_TYPE ((1 << ACPI_IORT_NODE_SMMU) | \
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(1 << ACPI_IORT_NODE_SMMU_V3))
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struct iort_its_msi_chip {
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struct list_head list;
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@ -28,6 +37,90 @@ struct iort_its_msi_chip {
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u32 translation_id;
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};
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struct iort_fwnode {
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struct list_head list;
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struct acpi_iort_node *iort_node;
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struct fwnode_handle *fwnode;
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};
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static LIST_HEAD(iort_fwnode_list);
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static DEFINE_SPINLOCK(iort_fwnode_lock);
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/**
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* iort_set_fwnode() - Create iort_fwnode and use it to register
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* iommu data in the iort_fwnode_list
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*
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* @node: IORT table node associated with the IOMMU
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* @fwnode: fwnode associated with the IORT node
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*
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* Returns: 0 on success
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* <0 on failure
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*/
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static inline int iort_set_fwnode(struct acpi_iort_node *iort_node,
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struct fwnode_handle *fwnode)
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{
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struct iort_fwnode *np;
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np = kzalloc(sizeof(struct iort_fwnode), GFP_ATOMIC);
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if (WARN_ON(!np))
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return -ENOMEM;
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INIT_LIST_HEAD(&np->list);
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np->iort_node = iort_node;
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np->fwnode = fwnode;
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spin_lock(&iort_fwnode_lock);
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list_add_tail(&np->list, &iort_fwnode_list);
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spin_unlock(&iort_fwnode_lock);
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return 0;
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}
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/**
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* iort_get_fwnode() - Retrieve fwnode associated with an IORT node
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*
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* @node: IORT table node to be looked-up
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*
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* Returns: fwnode_handle pointer on success, NULL on failure
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*/
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static inline
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struct fwnode_handle *iort_get_fwnode(struct acpi_iort_node *node)
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{
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struct iort_fwnode *curr;
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struct fwnode_handle *fwnode = NULL;
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spin_lock(&iort_fwnode_lock);
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list_for_each_entry(curr, &iort_fwnode_list, list) {
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if (curr->iort_node == node) {
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fwnode = curr->fwnode;
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break;
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}
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}
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spin_unlock(&iort_fwnode_lock);
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return fwnode;
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}
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/**
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* iort_delete_fwnode() - Delete fwnode associated with an IORT node
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*
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* @node: IORT table node associated with fwnode to delete
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*/
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static inline void iort_delete_fwnode(struct acpi_iort_node *node)
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{
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struct iort_fwnode *curr, *tmp;
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spin_lock(&iort_fwnode_lock);
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list_for_each_entry_safe(curr, tmp, &iort_fwnode_list, list) {
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if (curr->iort_node == node) {
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list_del(&curr->list);
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kfree(curr);
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break;
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}
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}
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spin_unlock(&iort_fwnode_lock);
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}
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typedef acpi_status (*iort_find_node_callback)
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(struct acpi_iort_node *node, void *context);
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@ -141,6 +234,21 @@ static struct acpi_iort_node *iort_scan_node(enum acpi_iort_node_type type,
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return NULL;
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}
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static acpi_status
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iort_match_type_callback(struct acpi_iort_node *node, void *context)
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{
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return AE_OK;
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}
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bool iort_node_match(u8 type)
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{
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struct acpi_iort_node *node;
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node = iort_scan_node(type, iort_match_type_callback, NULL);
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return node != NULL;
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}
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static acpi_status iort_match_node_callback(struct acpi_iort_node *node,
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void *context)
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{
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@ -212,9 +320,48 @@ static int iort_id_map(struct acpi_iort_id_mapping *map, u8 type, u32 rid_in,
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return 0;
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}
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static
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struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node,
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u32 *id_out, u8 type_mask,
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int index)
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{
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struct acpi_iort_node *parent;
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struct acpi_iort_id_mapping *map;
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if (!node->mapping_offset || !node->mapping_count ||
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index >= node->mapping_count)
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return NULL;
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map = ACPI_ADD_PTR(struct acpi_iort_id_mapping, node,
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node->mapping_offset);
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/* Firmware bug! */
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if (!map->output_reference) {
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pr_err(FW_BUG "[node %p type %d] ID map has NULL parent reference\n",
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node, node->type);
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return NULL;
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}
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parent = ACPI_ADD_PTR(struct acpi_iort_node, iort_table,
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map->output_reference);
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if (!(IORT_TYPE_MASK(parent->type) & type_mask))
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return NULL;
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if (map[index].flags & ACPI_IORT_ID_SINGLE_MAPPING) {
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if (node->type == ACPI_IORT_NODE_NAMED_COMPONENT ||
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node->type == ACPI_IORT_NODE_PCI_ROOT_COMPLEX) {
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*id_out = map[index].output_base;
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return parent;
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}
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}
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return NULL;
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}
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static struct acpi_iort_node *iort_node_map_rid(struct acpi_iort_node *node,
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u32 rid_in, u32 *rid_out,
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u8 type)
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u8 type_mask)
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{
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u32 rid = rid_in;
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@ -223,7 +370,7 @@ static struct acpi_iort_node *iort_node_map_rid(struct acpi_iort_node *node,
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struct acpi_iort_id_mapping *map;
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int i;
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if (node->type == type) {
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if (IORT_TYPE_MASK(node->type) & type_mask) {
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if (rid_out)
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*rid_out = rid;
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return node;
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@ -296,7 +443,7 @@ u32 iort_msi_map_rid(struct device *dev, u32 req_id)
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if (!node)
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return req_id;
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iort_node_map_rid(node, req_id, &dev_id, ACPI_IORT_NODE_ITS_GROUP);
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iort_node_map_rid(node, req_id, &dev_id, IORT_MSI_TYPE);
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return dev_id;
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}
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@ -318,7 +465,7 @@ static int iort_dev_find_its_id(struct device *dev, u32 req_id,
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if (!node)
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return -ENXIO;
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node = iort_node_map_rid(node, req_id, NULL, ACPI_IORT_NODE_ITS_GROUP);
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node = iort_node_map_rid(node, req_id, NULL, IORT_MSI_TYPE);
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if (!node)
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return -ENXIO;
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@ -356,13 +503,437 @@ struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id)
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return irq_find_matching_fwnode(handle, DOMAIN_BUS_PCI_MSI);
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}
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static int __get_pci_rid(struct pci_dev *pdev, u16 alias, void *data)
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{
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u32 *rid = data;
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*rid = alias;
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return 0;
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}
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static int arm_smmu_iort_xlate(struct device *dev, u32 streamid,
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struct fwnode_handle *fwnode,
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const struct iommu_ops *ops)
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{
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int ret = iommu_fwspec_init(dev, fwnode, ops);
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if (!ret)
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ret = iommu_fwspec_add_ids(dev, &streamid, 1);
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return ret;
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}
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static const struct iommu_ops *iort_iommu_xlate(struct device *dev,
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struct acpi_iort_node *node,
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u32 streamid)
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{
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const struct iommu_ops *ops = NULL;
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int ret = -ENODEV;
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struct fwnode_handle *iort_fwnode;
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if (node) {
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iort_fwnode = iort_get_fwnode(node);
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if (!iort_fwnode)
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return NULL;
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ops = iommu_get_instance(iort_fwnode);
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if (!ops)
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return NULL;
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ret = arm_smmu_iort_xlate(dev, streamid, iort_fwnode, ops);
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}
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return ret ? NULL : ops;
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}
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/**
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* iort_iommu_configure - Set-up IOMMU configuration for a device.
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*
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* @dev: device to configure
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*
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* Returns: iommu_ops pointer on configuration success
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* NULL on configuration failure
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*/
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const struct iommu_ops *iort_iommu_configure(struct device *dev)
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{
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struct acpi_iort_node *node, *parent;
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const struct iommu_ops *ops = NULL;
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u32 streamid = 0;
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if (dev_is_pci(dev)) {
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struct pci_bus *bus = to_pci_dev(dev)->bus;
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u32 rid;
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pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid,
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&rid);
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node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX,
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iort_match_node_callback, &bus->dev);
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if (!node)
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return NULL;
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parent = iort_node_map_rid(node, rid, &streamid,
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IORT_IOMMU_TYPE);
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ops = iort_iommu_xlate(dev, parent, streamid);
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} else {
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int i = 0;
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node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT,
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iort_match_node_callback, dev);
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if (!node)
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return NULL;
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parent = iort_node_get_id(node, &streamid,
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IORT_IOMMU_TYPE, i++);
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while (parent) {
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ops = iort_iommu_xlate(dev, parent, streamid);
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parent = iort_node_get_id(node, &streamid,
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IORT_IOMMU_TYPE, i++);
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}
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}
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return ops;
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}
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static void __init acpi_iort_register_irq(int hwirq, const char *name,
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int trigger,
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struct resource *res)
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{
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int irq = acpi_register_gsi(NULL, hwirq, trigger,
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ACPI_ACTIVE_HIGH);
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if (irq <= 0) {
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pr_err("could not register gsi hwirq %d name [%s]\n", hwirq,
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name);
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return;
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}
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res->start = irq;
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res->end = irq;
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res->flags = IORESOURCE_IRQ;
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res->name = name;
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}
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static int __init arm_smmu_v3_count_resources(struct acpi_iort_node *node)
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{
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struct acpi_iort_smmu_v3 *smmu;
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/* Always present mem resource */
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int num_res = 1;
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/* Retrieve SMMUv3 specific data */
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smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
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if (smmu->event_gsiv)
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num_res++;
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if (smmu->pri_gsiv)
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num_res++;
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if (smmu->gerr_gsiv)
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num_res++;
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if (smmu->sync_gsiv)
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num_res++;
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return num_res;
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}
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static void __init arm_smmu_v3_init_resources(struct resource *res,
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struct acpi_iort_node *node)
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{
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struct acpi_iort_smmu_v3 *smmu;
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int num_res = 0;
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/* Retrieve SMMUv3 specific data */
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smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
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res[num_res].start = smmu->base_address;
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res[num_res].end = smmu->base_address + SZ_128K - 1;
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res[num_res].flags = IORESOURCE_MEM;
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num_res++;
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if (smmu->event_gsiv)
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acpi_iort_register_irq(smmu->event_gsiv, "eventq",
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ACPI_EDGE_SENSITIVE,
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&res[num_res++]);
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if (smmu->pri_gsiv)
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acpi_iort_register_irq(smmu->pri_gsiv, "priq",
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ACPI_EDGE_SENSITIVE,
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&res[num_res++]);
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|
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if (smmu->gerr_gsiv)
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acpi_iort_register_irq(smmu->gerr_gsiv, "gerror",
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ACPI_EDGE_SENSITIVE,
|
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&res[num_res++]);
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|
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if (smmu->sync_gsiv)
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acpi_iort_register_irq(smmu->sync_gsiv, "cmdq-sync",
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ACPI_EDGE_SENSITIVE,
|
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&res[num_res++]);
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}
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|
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static bool __init arm_smmu_v3_is_coherent(struct acpi_iort_node *node)
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{
|
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struct acpi_iort_smmu_v3 *smmu;
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|
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/* Retrieve SMMUv3 specific data */
|
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smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
|
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|
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return smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE;
|
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}
|
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|
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static int __init arm_smmu_count_resources(struct acpi_iort_node *node)
|
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{
|
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struct acpi_iort_smmu *smmu;
|
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|
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/* Retrieve SMMU specific data */
|
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smmu = (struct acpi_iort_smmu *)node->node_data;
|
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|
||||
/*
|
||||
* Only consider the global fault interrupt and ignore the
|
||||
* configuration access interrupt.
|
||||
*
|
||||
* MMIO address and global fault interrupt resources are always
|
||||
* present so add them to the context interrupt count as a static
|
||||
* value.
|
||||
*/
|
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return smmu->context_interrupt_count + 2;
|
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}
|
||||
|
||||
static void __init arm_smmu_init_resources(struct resource *res,
|
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struct acpi_iort_node *node)
|
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{
|
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struct acpi_iort_smmu *smmu;
|
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int i, hw_irq, trigger, num_res = 0;
|
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u64 *ctx_irq, *glb_irq;
|
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|
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/* Retrieve SMMU specific data */
|
||||
smmu = (struct acpi_iort_smmu *)node->node_data;
|
||||
|
||||
res[num_res].start = smmu->base_address;
|
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res[num_res].end = smmu->base_address + smmu->span - 1;
|
||||
res[num_res].flags = IORESOURCE_MEM;
|
||||
num_res++;
|
||||
|
||||
glb_irq = ACPI_ADD_PTR(u64, node, smmu->global_interrupt_offset);
|
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/* Global IRQs */
|
||||
hw_irq = IORT_IRQ_MASK(glb_irq[0]);
|
||||
trigger = IORT_IRQ_TRIGGER_MASK(glb_irq[0]);
|
||||
|
||||
acpi_iort_register_irq(hw_irq, "arm-smmu-global", trigger,
|
||||
&res[num_res++]);
|
||||
|
||||
/* Context IRQs */
|
||||
ctx_irq = ACPI_ADD_PTR(u64, node, smmu->context_interrupt_offset);
|
||||
for (i = 0; i < smmu->context_interrupt_count; i++) {
|
||||
hw_irq = IORT_IRQ_MASK(ctx_irq[i]);
|
||||
trigger = IORT_IRQ_TRIGGER_MASK(ctx_irq[i]);
|
||||
|
||||
acpi_iort_register_irq(hw_irq, "arm-smmu-context", trigger,
|
||||
&res[num_res++]);
|
||||
}
|
||||
}
|
||||
|
||||
static bool __init arm_smmu_is_coherent(struct acpi_iort_node *node)
|
||||
{
|
||||
struct acpi_iort_smmu *smmu;
|
||||
|
||||
/* Retrieve SMMU specific data */
|
||||
smmu = (struct acpi_iort_smmu *)node->node_data;
|
||||
|
||||
return smmu->flags & ACPI_IORT_SMMU_COHERENT_WALK;
|
||||
}
|
||||
|
||||
struct iort_iommu_config {
|
||||
const char *name;
|
||||
int (*iommu_init)(struct acpi_iort_node *node);
|
||||
bool (*iommu_is_coherent)(struct acpi_iort_node *node);
|
||||
int (*iommu_count_resources)(struct acpi_iort_node *node);
|
||||
void (*iommu_init_resources)(struct resource *res,
|
||||
struct acpi_iort_node *node);
|
||||
};
|
||||
|
||||
static const struct iort_iommu_config iort_arm_smmu_v3_cfg __initconst = {
|
||||
.name = "arm-smmu-v3",
|
||||
.iommu_is_coherent = arm_smmu_v3_is_coherent,
|
||||
.iommu_count_resources = arm_smmu_v3_count_resources,
|
||||
.iommu_init_resources = arm_smmu_v3_init_resources
|
||||
};
|
||||
|
||||
static const struct iort_iommu_config iort_arm_smmu_cfg __initconst = {
|
||||
.name = "arm-smmu",
|
||||
.iommu_is_coherent = arm_smmu_is_coherent,
|
||||
.iommu_count_resources = arm_smmu_count_resources,
|
||||
.iommu_init_resources = arm_smmu_init_resources
|
||||
};
|
||||
|
||||
static __init
|
||||
const struct iort_iommu_config *iort_get_iommu_cfg(struct acpi_iort_node *node)
|
||||
{
|
||||
switch (node->type) {
|
||||
case ACPI_IORT_NODE_SMMU_V3:
|
||||
return &iort_arm_smmu_v3_cfg;
|
||||
case ACPI_IORT_NODE_SMMU:
|
||||
return &iort_arm_smmu_cfg;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* iort_add_smmu_platform_device() - Allocate a platform device for SMMU
|
||||
* @node: Pointer to SMMU ACPI IORT node
|
||||
*
|
||||
* Returns: 0 on success, <0 failure
|
||||
*/
|
||||
static int __init iort_add_smmu_platform_device(struct acpi_iort_node *node)
|
||||
{
|
||||
struct fwnode_handle *fwnode;
|
||||
struct platform_device *pdev;
|
||||
struct resource *r;
|
||||
enum dev_dma_attr attr;
|
||||
int ret, count;
|
||||
const struct iort_iommu_config *ops = iort_get_iommu_cfg(node);
|
||||
|
||||
if (!ops)
|
||||
return -ENODEV;
|
||||
|
||||
pdev = platform_device_alloc(ops->name, PLATFORM_DEVID_AUTO);
|
||||
if (!pdev)
|
||||
return PTR_ERR(pdev);
|
||||
|
||||
count = ops->iommu_count_resources(node);
|
||||
|
||||
r = kcalloc(count, sizeof(*r), GFP_KERNEL);
|
||||
if (!r) {
|
||||
ret = -ENOMEM;
|
||||
goto dev_put;
|
||||
}
|
||||
|
||||
ops->iommu_init_resources(r, node);
|
||||
|
||||
ret = platform_device_add_resources(pdev, r, count);
|
||||
/*
|
||||
* Resources are duplicated in platform_device_add_resources,
|
||||
* free their allocated memory
|
||||
*/
|
||||
kfree(r);
|
||||
|
||||
if (ret)
|
||||
goto dev_put;
|
||||
|
||||
/*
|
||||
* Add a copy of IORT node pointer to platform_data to
|
||||
* be used to retrieve IORT data information.
|
||||
*/
|
||||
ret = platform_device_add_data(pdev, &node, sizeof(node));
|
||||
if (ret)
|
||||
goto dev_put;
|
||||
|
||||
/*
|
||||
* We expect the dma masks to be equivalent for
|
||||
* all SMMUs set-ups
|
||||
*/
|
||||
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
|
||||
|
||||
fwnode = iort_get_fwnode(node);
|
||||
|
||||
if (!fwnode) {
|
||||
ret = -ENODEV;
|
||||
goto dev_put;
|
||||
}
|
||||
|
||||
pdev->dev.fwnode = fwnode;
|
||||
|
||||
attr = ops->iommu_is_coherent(node) ?
|
||||
DEV_DMA_COHERENT : DEV_DMA_NON_COHERENT;
|
||||
|
||||
/* Configure DMA for the page table walker */
|
||||
acpi_dma_configure(&pdev->dev, attr);
|
||||
|
||||
ret = platform_device_add(pdev);
|
||||
if (ret)
|
||||
goto dma_deconfigure;
|
||||
|
||||
return 0;
|
||||
|
||||
dma_deconfigure:
|
||||
acpi_dma_deconfigure(&pdev->dev);
|
||||
dev_put:
|
||||
platform_device_put(pdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __init iort_init_platform_devices(void)
|
||||
{
|
||||
struct acpi_iort_node *iort_node, *iort_end;
|
||||
struct acpi_table_iort *iort;
|
||||
struct fwnode_handle *fwnode;
|
||||
int i, ret;
|
||||
|
||||
/*
|
||||
* iort_table and iort both point to the start of IORT table, but
|
||||
* have different struct types
|
||||
*/
|
||||
iort = (struct acpi_table_iort *)iort_table;
|
||||
|
||||
/* Get the first IORT node */
|
||||
iort_node = ACPI_ADD_PTR(struct acpi_iort_node, iort,
|
||||
iort->node_offset);
|
||||
iort_end = ACPI_ADD_PTR(struct acpi_iort_node, iort,
|
||||
iort_table->length);
|
||||
|
||||
for (i = 0; i < iort->node_count; i++) {
|
||||
if (iort_node >= iort_end) {
|
||||
pr_err("iort node pointer overflows, bad table\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if ((iort_node->type == ACPI_IORT_NODE_SMMU) ||
|
||||
(iort_node->type == ACPI_IORT_NODE_SMMU_V3)) {
|
||||
|
||||
fwnode = acpi_alloc_fwnode_static();
|
||||
if (!fwnode)
|
||||
return;
|
||||
|
||||
iort_set_fwnode(iort_node, fwnode);
|
||||
|
||||
ret = iort_add_smmu_platform_device(iort_node);
|
||||
if (ret) {
|
||||
iort_delete_fwnode(iort_node);
|
||||
acpi_free_fwnode_static(fwnode);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
iort_node = ACPI_ADD_PTR(struct acpi_iort_node, iort_node,
|
||||
iort_node->length);
|
||||
}
|
||||
}
|
||||
|
||||
void __init acpi_iort_init(void)
|
||||
{
|
||||
acpi_status status;
|
||||
|
||||
status = acpi_get_table(ACPI_SIG_IORT, 0, &iort_table);
|
||||
if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
|
||||
const char *msg = acpi_format_exception(status);
|
||||
pr_err("Failed to get table, %s\n", msg);
|
||||
if (ACPI_FAILURE(status)) {
|
||||
if (status != AE_NOT_FOUND) {
|
||||
const char *msg = acpi_format_exception(status);
|
||||
|
||||
pr_err("Failed to get table, %s\n", msg);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
iort_init_platform_devices();
|
||||
|
||||
acpi_probe_device_table(iort);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -227,8 +227,7 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
|
|||
|
||||
attr = acpi_get_dma_attr(acpi_dev);
|
||||
if (attr != DEV_DMA_NOT_SUPPORTED)
|
||||
arch_setup_dma_ops(dev, 0, 0, NULL,
|
||||
attr == DEV_DMA_COHERENT);
|
||||
acpi_dma_configure(dev, attr);
|
||||
|
||||
acpi_physnode_link_name(physical_node_name, node_id);
|
||||
retval = sysfs_create_link(&acpi_dev->dev.kobj, &dev->kobj,
|
||||
|
|
@ -251,6 +250,7 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
|
|||
return 0;
|
||||
|
||||
err:
|
||||
acpi_dma_deconfigure(dev);
|
||||
ACPI_COMPANION_SET(dev, NULL);
|
||||
put_device(dev);
|
||||
put_device(&acpi_dev->dev);
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/acpi_iort.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/kthread.h>
|
||||
#include <linux/dmi.h>
|
||||
|
|
@ -1370,6 +1371,50 @@ enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev)
|
|||
return DEV_DMA_NON_COHERENT;
|
||||
}
|
||||
|
||||
/**
|
||||
* acpi_dma_configure - Set-up DMA configuration for the device.
|
||||
* @dev: The pointer to the device
|
||||
* @attr: device dma attributes
|
||||
*/
|
||||
void acpi_dma_configure(struct device *dev, enum dev_dma_attr attr)
|
||||
{
|
||||
const struct iommu_ops *iommu;
|
||||
|
||||
/*
|
||||
* Set default coherent_dma_mask to 32 bit. Drivers are expected to
|
||||
* setup the correct supported mask.
|
||||
*/
|
||||
if (!dev->coherent_dma_mask)
|
||||
dev->coherent_dma_mask = DMA_BIT_MASK(32);
|
||||
|
||||
/*
|
||||
* Set it to coherent_dma_mask by default if the architecture
|
||||
* code has not set it.
|
||||
*/
|
||||
if (!dev->dma_mask)
|
||||
dev->dma_mask = &dev->coherent_dma_mask;
|
||||
|
||||
iommu = iort_iommu_configure(dev);
|
||||
|
||||
/*
|
||||
* Assume dma valid range starts at 0 and covers the whole
|
||||
* coherent_dma_mask.
|
||||
*/
|
||||
arch_setup_dma_ops(dev, 0, dev->coherent_dma_mask + 1, iommu,
|
||||
attr == DEV_DMA_COHERENT);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(acpi_dma_configure);
|
||||
|
||||
/**
|
||||
* acpi_dma_deconfigure - Tear-down DMA configuration for the device.
|
||||
* @dev: The pointer to the device
|
||||
*/
|
||||
void acpi_dma_deconfigure(struct device *dev)
|
||||
{
|
||||
arch_teardown_dma_ops(dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(acpi_dma_deconfigure);
|
||||
|
||||
static void acpi_init_coherency(struct acpi_device *adev)
|
||||
{
|
||||
unsigned long long cca = 0;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@
|
|||
* This driver is powered by bad coffee and bombay mix.
|
||||
*/
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/acpi_iort.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dma-iommu.h>
|
||||
#include <linux/err.h>
|
||||
|
|
@ -1358,7 +1360,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
|
|||
} while (size -= granule);
|
||||
}
|
||||
|
||||
static struct iommu_gather_ops arm_smmu_gather_ops = {
|
||||
static const struct iommu_gather_ops arm_smmu_gather_ops = {
|
||||
.tlb_flush_all = arm_smmu_tlb_inv_context,
|
||||
.tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
|
||||
.tlb_sync = arm_smmu_tlb_sync,
|
||||
|
|
@ -1723,13 +1725,14 @@ static struct platform_driver arm_smmu_driver;
|
|||
|
||||
static int arm_smmu_match_node(struct device *dev, void *data)
|
||||
{
|
||||
return dev->of_node == data;
|
||||
return dev->fwnode == data;
|
||||
}
|
||||
|
||||
static struct arm_smmu_device *arm_smmu_get_by_node(struct device_node *np)
|
||||
static
|
||||
struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
|
||||
{
|
||||
struct device *dev = driver_find_device(&arm_smmu_driver.driver, NULL,
|
||||
np, arm_smmu_match_node);
|
||||
fwnode, arm_smmu_match_node);
|
||||
put_device(dev);
|
||||
return dev ? dev_get_drvdata(dev) : NULL;
|
||||
}
|
||||
|
|
@ -1765,7 +1768,7 @@ static int arm_smmu_add_device(struct device *dev)
|
|||
master = fwspec->iommu_priv;
|
||||
smmu = master->smmu;
|
||||
} else {
|
||||
smmu = arm_smmu_get_by_node(to_of_node(fwspec->iommu_fwnode));
|
||||
smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode);
|
||||
if (!smmu)
|
||||
return -ENODEV;
|
||||
master = kzalloc(sizeof(*master), GFP_KERNEL);
|
||||
|
|
@ -2380,10 +2383,10 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int arm_smmu_device_probe(struct arm_smmu_device *smmu)
|
||||
static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
|
||||
{
|
||||
u32 reg;
|
||||
bool coherent;
|
||||
bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY;
|
||||
|
||||
/* IDR0 */
|
||||
reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0);
|
||||
|
|
@ -2435,13 +2438,9 @@ static int arm_smmu_device_probe(struct arm_smmu_device *smmu)
|
|||
smmu->features |= ARM_SMMU_FEAT_HYP;
|
||||
|
||||
/*
|
||||
* The dma-coherent property is used in preference to the ID
|
||||
* The coherency feature as set by FW is used in preference to the ID
|
||||
* register, but warn on mismatch.
|
||||
*/
|
||||
coherent = of_dma_is_coherent(smmu->dev->of_node);
|
||||
if (coherent)
|
||||
smmu->features |= ARM_SMMU_FEAT_COHERENCY;
|
||||
|
||||
if (!!(reg & IDR0_COHACC) != coherent)
|
||||
dev_warn(smmu->dev, "IDR0.COHACC overridden by dma-coherent property (%s)\n",
|
||||
coherent ? "true" : "false");
|
||||
|
|
@ -2562,21 +2561,61 @@ static int arm_smmu_device_probe(struct arm_smmu_device *smmu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
||||
#ifdef CONFIG_ACPI
|
||||
static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
|
||||
struct arm_smmu_device *smmu)
|
||||
{
|
||||
struct acpi_iort_smmu_v3 *iort_smmu;
|
||||
struct device *dev = smmu->dev;
|
||||
struct acpi_iort_node *node;
|
||||
|
||||
node = *(struct acpi_iort_node **)dev_get_platdata(dev);
|
||||
|
||||
/* Retrieve SMMUv3 specific data */
|
||||
iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
|
||||
|
||||
if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE)
|
||||
smmu->features |= ARM_SMMU_FEAT_COHERENCY;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev,
|
||||
struct arm_smmu_device *smmu)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int arm_smmu_device_dt_probe(struct platform_device *pdev,
|
||||
struct arm_smmu_device *smmu)
|
||||
{
|
||||
int irq, ret;
|
||||
struct resource *res;
|
||||
struct arm_smmu_device *smmu;
|
||||
struct device *dev = &pdev->dev;
|
||||
bool bypass = true;
|
||||
u32 cells;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (of_property_read_u32(dev->of_node, "#iommu-cells", &cells))
|
||||
dev_err(dev, "missing #iommu-cells property\n");
|
||||
else if (cells != 1)
|
||||
dev_err(dev, "invalid #iommu-cells value (%d)\n", cells);
|
||||
else
|
||||
bypass = false;
|
||||
ret = 0;
|
||||
|
||||
parse_driver_options(smmu);
|
||||
|
||||
if (of_dma_is_coherent(dev->of_node))
|
||||
smmu->features |= ARM_SMMU_FEAT_COHERENCY;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int arm_smmu_device_probe(struct platform_device *pdev)
|
||||
{
|
||||
int irq, ret;
|
||||
struct resource *res;
|
||||
struct arm_smmu_device *smmu;
|
||||
struct device *dev = &pdev->dev;
|
||||
bool bypass;
|
||||
|
||||
smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
|
||||
if (!smmu) {
|
||||
|
|
@ -2613,10 +2652,19 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
|||
if (irq > 0)
|
||||
smmu->gerr_irq = irq;
|
||||
|
||||
parse_driver_options(smmu);
|
||||
if (dev->of_node) {
|
||||
ret = arm_smmu_device_dt_probe(pdev, smmu);
|
||||
} else {
|
||||
ret = arm_smmu_device_acpi_probe(pdev, smmu);
|
||||
if (ret == -ENODEV)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Set bypass mode according to firmware probing result */
|
||||
bypass = !!ret;
|
||||
|
||||
/* Probe the h/w */
|
||||
ret = arm_smmu_device_probe(smmu);
|
||||
ret = arm_smmu_device_hw_probe(smmu);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -2634,7 +2682,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
|
||||
/* And we're up. Go go go! */
|
||||
of_iommu_set_ops(dev->of_node, &arm_smmu_ops);
|
||||
iommu_register_instance(dev->fwnode, &arm_smmu_ops);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
if (pci_bus_type.iommu_ops != &arm_smmu_ops) {
|
||||
pci_request_acs();
|
||||
|
|
@ -2677,7 +2726,7 @@ static struct platform_driver arm_smmu_driver = {
|
|||
.name = "arm-smmu-v3",
|
||||
.of_match_table = of_match_ptr(arm_smmu_of_match),
|
||||
},
|
||||
.probe = arm_smmu_device_dt_probe,
|
||||
.probe = arm_smmu_device_probe,
|
||||
.remove = arm_smmu_device_remove,
|
||||
};
|
||||
|
||||
|
|
@ -2715,6 +2764,17 @@ static int __init arm_smmu_of_init(struct device_node *np)
|
|||
}
|
||||
IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", arm_smmu_of_init);
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static int __init acpi_smmu_v3_init(struct acpi_table_header *table)
|
||||
{
|
||||
if (iort_node_match(ACPI_IORT_NODE_SMMU_V3))
|
||||
return arm_smmu_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
IORT_ACPI_DECLARE(arm_smmu_v3, ACPI_SIG_IORT, acpi_smmu_v3_init);
|
||||
#endif
|
||||
|
||||
MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
|
||||
MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -28,6 +28,8 @@
|
|||
|
||||
#define pr_fmt(fmt) "arm-smmu: " fmt
|
||||
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/acpi_iort.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dma-iommu.h>
|
||||
|
|
@ -247,6 +249,7 @@ enum arm_smmu_s2cr_privcfg {
|
|||
#define ARM_MMU500_ACTLR_CPRE (1 << 1)
|
||||
|
||||
#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
|
||||
#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)
|
||||
|
||||
#define CB_PAR_F (1 << 0)
|
||||
|
||||
|
|
@ -642,7 +645,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
|
|||
}
|
||||
}
|
||||
|
||||
static struct iommu_gather_ops arm_smmu_gather_ops = {
|
||||
static const struct iommu_gather_ops arm_smmu_gather_ops = {
|
||||
.tlb_flush_all = arm_smmu_tlb_inv_context,
|
||||
.tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
|
||||
.tlb_sync = arm_smmu_tlb_sync,
|
||||
|
|
@ -1379,13 +1382,14 @@ static bool arm_smmu_capable(enum iommu_cap cap)
|
|||
|
||||
static int arm_smmu_match_node(struct device *dev, void *data)
|
||||
{
|
||||
return dev->of_node == data;
|
||||
return dev->fwnode == data;
|
||||
}
|
||||
|
||||
static struct arm_smmu_device *arm_smmu_get_by_node(struct device_node *np)
|
||||
static
|
||||
struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
|
||||
{
|
||||
struct device *dev = driver_find_device(&arm_smmu_driver.driver, NULL,
|
||||
np, arm_smmu_match_node);
|
||||
fwnode, arm_smmu_match_node);
|
||||
put_device(dev);
|
||||
return dev ? dev_get_drvdata(dev) : NULL;
|
||||
}
|
||||
|
|
@ -1403,7 +1407,7 @@ static int arm_smmu_add_device(struct device *dev)
|
|||
if (ret)
|
||||
goto out_free;
|
||||
} else if (fwspec && fwspec->ops == &arm_smmu_ops) {
|
||||
smmu = arm_smmu_get_by_node(to_of_node(fwspec->iommu_fwnode));
|
||||
smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode);
|
||||
} else {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
|
@ -1581,16 +1585,22 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
|
|||
for (i = 0; i < smmu->num_mapping_groups; ++i)
|
||||
arm_smmu_write_sme(smmu, i);
|
||||
|
||||
/*
|
||||
* Before clearing ARM_MMU500_ACTLR_CPRE, need to
|
||||
* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
|
||||
* bit is only present in MMU-500r2 onwards.
|
||||
*/
|
||||
reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
|
||||
major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
|
||||
if ((smmu->model == ARM_MMU500) && (major >= 2)) {
|
||||
if (smmu->model == ARM_MMU500) {
|
||||
/*
|
||||
* Before clearing ARM_MMU500_ACTLR_CPRE, need to
|
||||
* clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
|
||||
* bit is only present in MMU-500r2 onwards.
|
||||
*/
|
||||
reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
|
||||
major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
|
||||
reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
|
||||
reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
|
||||
if (major >= 2)
|
||||
reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
|
||||
/*
|
||||
* Allow unmatched Stream IDs to allocate bypass
|
||||
* TLB entries for reduced latency.
|
||||
*/
|
||||
reg |= ARM_MMU500_ACR_SMTNMB_TLBEN;
|
||||
writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
|
||||
}
|
||||
|
||||
|
|
@ -1667,7 +1677,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
|
|||
unsigned long size;
|
||||
void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
|
||||
u32 id;
|
||||
bool cttw_dt, cttw_reg;
|
||||
bool cttw_reg, cttw_fw = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK;
|
||||
int i;
|
||||
|
||||
dev_notice(smmu->dev, "probing hardware configuration...\n");
|
||||
|
|
@ -1712,20 +1722,17 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
|
|||
|
||||
/*
|
||||
* In order for DMA API calls to work properly, we must defer to what
|
||||
* the DT says about coherency, regardless of what the hardware claims.
|
||||
* the FW says about coherency, regardless of what the hardware claims.
|
||||
* Fortunately, this also opens up a workaround for systems where the
|
||||
* ID register value has ended up configured incorrectly.
|
||||
*/
|
||||
cttw_dt = of_dma_is_coherent(smmu->dev->of_node);
|
||||
cttw_reg = !!(id & ID0_CTTW);
|
||||
if (cttw_dt)
|
||||
smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
|
||||
if (cttw_dt || cttw_reg)
|
||||
if (cttw_fw || cttw_reg)
|
||||
dev_notice(smmu->dev, "\t%scoherent table walk\n",
|
||||
cttw_dt ? "" : "non-");
|
||||
if (cttw_dt != cttw_reg)
|
||||
cttw_fw ? "" : "non-");
|
||||
if (cttw_fw != cttw_reg)
|
||||
dev_notice(smmu->dev,
|
||||
"\t(IDR0.CTTW overridden by dma-coherent property)\n");
|
||||
"\t(IDR0.CTTW overridden by FW configuration)\n");
|
||||
|
||||
/* Max. number of entries we have for stream matching/indexing */
|
||||
size = 1 << ((id >> ID0_NUMSIDB_SHIFT) & ID0_NUMSIDB_MASK);
|
||||
|
|
@ -1906,15 +1913,83 @@ static const struct of_device_id arm_smmu_of_match[] = {
|
|||
};
|
||||
MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
|
||||
|
||||
static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
||||
#ifdef CONFIG_ACPI
|
||||
static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (model) {
|
||||
case ACPI_IORT_SMMU_V1:
|
||||
case ACPI_IORT_SMMU_CORELINK_MMU400:
|
||||
smmu->version = ARM_SMMU_V1;
|
||||
smmu->model = GENERIC_SMMU;
|
||||
break;
|
||||
case ACPI_IORT_SMMU_V2:
|
||||
smmu->version = ARM_SMMU_V2;
|
||||
smmu->model = GENERIC_SMMU;
|
||||
break;
|
||||
case ACPI_IORT_SMMU_CORELINK_MMU500:
|
||||
smmu->version = ARM_SMMU_V2;
|
||||
smmu->model = ARM_MMU500;
|
||||
break;
|
||||
default:
|
||||
ret = -ENODEV;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
|
||||
struct arm_smmu_device *smmu)
|
||||
{
|
||||
struct device *dev = smmu->dev;
|
||||
struct acpi_iort_node *node =
|
||||
*(struct acpi_iort_node **)dev_get_platdata(dev);
|
||||
struct acpi_iort_smmu *iort_smmu;
|
||||
int ret;
|
||||
|
||||
/* Retrieve SMMU1/2 specific data */
|
||||
iort_smmu = (struct acpi_iort_smmu *)node->node_data;
|
||||
|
||||
ret = acpi_smmu_get_data(iort_smmu->model, smmu);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Ignore the configuration access interrupt */
|
||||
smmu->num_global_irqs = 1;
|
||||
|
||||
if (iort_smmu->flags & ACPI_IORT_SMMU_COHERENT_WALK)
|
||||
smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev,
|
||||
struct arm_smmu_device *smmu)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int arm_smmu_device_dt_probe(struct platform_device *pdev,
|
||||
struct arm_smmu_device *smmu)
|
||||
{
|
||||
const struct arm_smmu_match_data *data;
|
||||
struct resource *res;
|
||||
struct arm_smmu_device *smmu;
|
||||
struct device *dev = &pdev->dev;
|
||||
int num_irqs, i, err;
|
||||
bool legacy_binding;
|
||||
|
||||
if (of_property_read_u32(dev->of_node, "#global-interrupts",
|
||||
&smmu->num_global_irqs)) {
|
||||
dev_err(dev, "missing #global-interrupts property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
data = of_device_get_match_data(dev);
|
||||
smmu->version = data->version;
|
||||
smmu->model = data->model;
|
||||
|
||||
parse_driver_options(smmu);
|
||||
|
||||
legacy_binding = of_find_property(dev->of_node, "mmu-masters", NULL);
|
||||
if (legacy_binding && !using_generic_binding) {
|
||||
if (!using_legacy_binding)
|
||||
|
|
@ -1927,6 +2002,19 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (of_dma_is_coherent(dev->of_node))
|
||||
smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int arm_smmu_device_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct arm_smmu_device *smmu;
|
||||
struct device *dev = &pdev->dev;
|
||||
int num_irqs, i, err;
|
||||
|
||||
smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
|
||||
if (!smmu) {
|
||||
dev_err(dev, "failed to allocate arm_smmu_device\n");
|
||||
|
|
@ -1934,9 +2022,13 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
|||
}
|
||||
smmu->dev = dev;
|
||||
|
||||
data = of_device_get_match_data(dev);
|
||||
smmu->version = data->version;
|
||||
smmu->model = data->model;
|
||||
if (dev->of_node)
|
||||
err = arm_smmu_device_dt_probe(pdev, smmu);
|
||||
else
|
||||
err = arm_smmu_device_acpi_probe(pdev, smmu);
|
||||
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
smmu->base = devm_ioremap_resource(dev, res);
|
||||
|
|
@ -1944,12 +2036,6 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(smmu->base);
|
||||
smmu->size = resource_size(res);
|
||||
|
||||
if (of_property_read_u32(dev->of_node, "#global-interrupts",
|
||||
&smmu->num_global_irqs)) {
|
||||
dev_err(dev, "missing #global-interrupts property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
num_irqs = 0;
|
||||
while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
|
||||
num_irqs++;
|
||||
|
|
@ -1984,8 +2070,6 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
parse_driver_options(smmu);
|
||||
|
||||
if (smmu->version == ARM_SMMU_V2 &&
|
||||
smmu->num_context_banks != smmu->num_context_irqs) {
|
||||
dev_err(dev,
|
||||
|
|
@ -2007,7 +2091,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
of_iommu_set_ops(dev->of_node, &arm_smmu_ops);
|
||||
iommu_register_instance(dev->fwnode, &arm_smmu_ops);
|
||||
platform_set_drvdata(pdev, smmu);
|
||||
arm_smmu_device_reset(smmu);
|
||||
|
||||
|
|
@ -2047,7 +2131,7 @@ static struct platform_driver arm_smmu_driver = {
|
|||
.name = "arm-smmu",
|
||||
.of_match_table = of_match_ptr(arm_smmu_of_match),
|
||||
},
|
||||
.probe = arm_smmu_device_dt_probe,
|
||||
.probe = arm_smmu_device_probe,
|
||||
.remove = arm_smmu_device_remove,
|
||||
};
|
||||
|
||||
|
|
@ -2090,6 +2174,17 @@ IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401", arm_smmu_of_init);
|
|||
IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500", arm_smmu_of_init);
|
||||
IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2", arm_smmu_of_init);
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
static int __init arm_smmu_acpi_init(struct acpi_table_header *table)
|
||||
{
|
||||
if (iort_node_match(ACPI_IORT_NODE_SMMU))
|
||||
return arm_smmu_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
IORT_ACPI_DECLARE(arm_smmu, ACPI_SIG_IORT, arm_smmu_acpi_init);
|
||||
#endif
|
||||
|
||||
MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
|
||||
MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -793,8 +793,7 @@ static int __init arm_v7s_do_selftests(void)
|
|||
* Distinct mappings of different granule sizes.
|
||||
*/
|
||||
iova = 0;
|
||||
i = find_first_bit(&cfg.pgsize_bitmap, BITS_PER_LONG);
|
||||
while (i != BITS_PER_LONG) {
|
||||
for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
|
||||
size = 1UL << i;
|
||||
if (ops->map(ops, iova, iova, size, IOMMU_READ |
|
||||
IOMMU_WRITE |
|
||||
|
|
@ -811,8 +810,6 @@ static int __init arm_v7s_do_selftests(void)
|
|||
return __FAIL(ops);
|
||||
|
||||
iova += SZ_16M;
|
||||
i++;
|
||||
i = find_next_bit(&cfg.pgsize_bitmap, BITS_PER_LONG, i);
|
||||
loopnr++;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -916,7 +916,7 @@ static void dummy_tlb_sync(void *cookie)
|
|||
WARN_ON(cookie != cfg_cookie);
|
||||
}
|
||||
|
||||
static struct iommu_gather_ops dummy_tlb_ops __initdata = {
|
||||
static const struct iommu_gather_ops dummy_tlb_ops __initconst = {
|
||||
.tlb_flush_all = dummy_tlb_flush_all,
|
||||
.tlb_add_flush = dummy_tlb_add_flush,
|
||||
.tlb_sync = dummy_tlb_sync,
|
||||
|
|
@ -980,8 +980,7 @@ static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
|
|||
* Distinct mappings of different granule sizes.
|
||||
*/
|
||||
iova = 0;
|
||||
j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
|
||||
while (j != BITS_PER_LONG) {
|
||||
for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) {
|
||||
size = 1UL << j;
|
||||
|
||||
if (ops->map(ops, iova, iova, size, IOMMU_READ |
|
||||
|
|
@ -999,8 +998,6 @@ static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
|
|||
return __FAIL(ops, i);
|
||||
|
||||
iova += SZ_1G;
|
||||
j++;
|
||||
j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
|
||||
}
|
||||
|
||||
/* Partial unmap */
|
||||
|
|
|
|||
|
|
@ -1615,6 +1615,46 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
struct iommu_instance {
|
||||
struct list_head list;
|
||||
struct fwnode_handle *fwnode;
|
||||
const struct iommu_ops *ops;
|
||||
};
|
||||
static LIST_HEAD(iommu_instance_list);
|
||||
static DEFINE_SPINLOCK(iommu_instance_lock);
|
||||
|
||||
void iommu_register_instance(struct fwnode_handle *fwnode,
|
||||
const struct iommu_ops *ops)
|
||||
{
|
||||
struct iommu_instance *iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
|
||||
|
||||
if (WARN_ON(!iommu))
|
||||
return;
|
||||
|
||||
of_node_get(to_of_node(fwnode));
|
||||
INIT_LIST_HEAD(&iommu->list);
|
||||
iommu->fwnode = fwnode;
|
||||
iommu->ops = ops;
|
||||
spin_lock(&iommu_instance_lock);
|
||||
list_add_tail(&iommu->list, &iommu_instance_list);
|
||||
spin_unlock(&iommu_instance_lock);
|
||||
}
|
||||
|
||||
const struct iommu_ops *iommu_get_instance(struct fwnode_handle *fwnode)
|
||||
{
|
||||
struct iommu_instance *instance;
|
||||
const struct iommu_ops *ops = NULL;
|
||||
|
||||
spin_lock(&iommu_instance_lock);
|
||||
list_for_each_entry(instance, &iommu_instance_list, list)
|
||||
if (instance->fwnode == fwnode) {
|
||||
ops = instance->ops;
|
||||
break;
|
||||
}
|
||||
spin_unlock(&iommu_instance_lock);
|
||||
return ops;
|
||||
}
|
||||
|
||||
int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode,
|
||||
const struct iommu_ops *ops)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -96,45 +96,6 @@ int of_get_dma_window(struct device_node *dn, const char *prefix, int index,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(of_get_dma_window);
|
||||
|
||||
struct of_iommu_node {
|
||||
struct list_head list;
|
||||
struct device_node *np;
|
||||
const struct iommu_ops *ops;
|
||||
};
|
||||
static LIST_HEAD(of_iommu_list);
|
||||
static DEFINE_SPINLOCK(of_iommu_lock);
|
||||
|
||||
void of_iommu_set_ops(struct device_node *np, const struct iommu_ops *ops)
|
||||
{
|
||||
struct of_iommu_node *iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
|
||||
|
||||
if (WARN_ON(!iommu))
|
||||
return;
|
||||
|
||||
of_node_get(np);
|
||||
INIT_LIST_HEAD(&iommu->list);
|
||||
iommu->np = np;
|
||||
iommu->ops = ops;
|
||||
spin_lock(&of_iommu_lock);
|
||||
list_add_tail(&iommu->list, &of_iommu_list);
|
||||
spin_unlock(&of_iommu_lock);
|
||||
}
|
||||
|
||||
const struct iommu_ops *of_iommu_get_ops(struct device_node *np)
|
||||
{
|
||||
struct of_iommu_node *node;
|
||||
const struct iommu_ops *ops = NULL;
|
||||
|
||||
spin_lock(&of_iommu_lock);
|
||||
list_for_each_entry(node, &of_iommu_list, list)
|
||||
if (node->np == np) {
|
||||
ops = node->ops;
|
||||
break;
|
||||
}
|
||||
spin_unlock(&of_iommu_lock);
|
||||
return ops;
|
||||
}
|
||||
|
||||
static int __get_pci_rid(struct pci_dev *pdev, u16 alias, void *data)
|
||||
{
|
||||
struct of_phandle_args *iommu_spec = data;
|
||||
|
|
|
|||
|
|
@ -1738,8 +1738,7 @@ static void pci_dma_configure(struct pci_dev *dev)
|
|||
if (attr == DEV_DMA_NOT_SUPPORTED)
|
||||
dev_warn(&dev->dev, "DMA not supported.\n");
|
||||
else
|
||||
arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
|
||||
attr == DEV_DMA_COHERENT);
|
||||
acpi_dma_configure(&dev->dev, attr);
|
||||
}
|
||||
|
||||
pci_put_host_bridge_device(bridge);
|
||||
|
|
|
|||
|
|
@ -573,6 +573,8 @@ struct acpi_pci_root {
|
|||
|
||||
bool acpi_dma_supported(struct acpi_device *adev);
|
||||
enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev);
|
||||
void acpi_dma_configure(struct device *dev, enum dev_dma_attr attr);
|
||||
void acpi_dma_deconfigure(struct device *dev);
|
||||
|
||||
struct acpi_device *acpi_find_child_device(struct acpi_device *parent,
|
||||
u64 address, bool check_children);
|
||||
|
|
|
|||
|
|
@ -566,6 +566,7 @@
|
|||
IRQCHIP_OF_MATCH_TABLE() \
|
||||
ACPI_PROBE_TABLE(irqchip) \
|
||||
ACPI_PROBE_TABLE(clksrc) \
|
||||
ACPI_PROBE_TABLE(iort) \
|
||||
EARLYCON_TABLE()
|
||||
|
||||
#define INIT_TEXT \
|
||||
|
|
|
|||
|
|
@ -56,6 +56,27 @@ static inline acpi_handle acpi_device_handle(struct acpi_device *adev)
|
|||
acpi_fwnode_handle(adev) : NULL)
|
||||
#define ACPI_HANDLE(dev) acpi_device_handle(ACPI_COMPANION(dev))
|
||||
|
||||
static inline struct fwnode_handle *acpi_alloc_fwnode_static(void)
|
||||
{
|
||||
struct fwnode_handle *fwnode;
|
||||
|
||||
fwnode = kzalloc(sizeof(struct fwnode_handle), GFP_KERNEL);
|
||||
if (!fwnode)
|
||||
return NULL;
|
||||
|
||||
fwnode->type = FWNODE_ACPI_STATIC;
|
||||
|
||||
return fwnode;
|
||||
}
|
||||
|
||||
static inline void acpi_free_fwnode_static(struct fwnode_handle *fwnode)
|
||||
{
|
||||
if (WARN_ON(!fwnode || fwnode->type != FWNODE_ACPI_STATIC))
|
||||
return;
|
||||
|
||||
kfree(fwnode);
|
||||
}
|
||||
|
||||
/**
|
||||
* ACPI_DEVICE_CLASS - macro used to describe an ACPI device with
|
||||
* the PCI-defined class-code information
|
||||
|
|
@ -744,6 +765,11 @@ static inline enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev)
|
|||
return DEV_DMA_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
static inline void acpi_dma_configure(struct device *dev,
|
||||
enum dev_dma_attr attr) { }
|
||||
|
||||
static inline void acpi_dma_deconfigure(struct device *dev) { }
|
||||
|
||||
#define ACPI_PTR(_ptr) (NULL)
|
||||
|
||||
static inline void acpi_device_set_enumerated(struct acpi_device *adev)
|
||||
|
|
|
|||
|
|
@ -23,20 +23,34 @@
|
|||
#include <linux/fwnode.h>
|
||||
#include <linux/irqdomain.h>
|
||||
|
||||
#define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL)
|
||||
#define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL)
|
||||
|
||||
int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node);
|
||||
void iort_deregister_domain_token(int trans_id);
|
||||
struct fwnode_handle *iort_find_domain_token(int trans_id);
|
||||
#ifdef CONFIG_ACPI_IORT
|
||||
void acpi_iort_init(void);
|
||||
bool iort_node_match(u8 type);
|
||||
u32 iort_msi_map_rid(struct device *dev, u32 req_id);
|
||||
struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id);
|
||||
/* IOMMU interface */
|
||||
const struct iommu_ops *iort_iommu_configure(struct device *dev);
|
||||
#else
|
||||
static inline void acpi_iort_init(void) { }
|
||||
static inline bool iort_node_match(u8 type) { return false; }
|
||||
static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id)
|
||||
{ return req_id; }
|
||||
static inline struct irq_domain *iort_get_device_domain(struct device *dev,
|
||||
u32 req_id)
|
||||
{ return NULL; }
|
||||
/* IOMMU interface */
|
||||
static inline
|
||||
const struct iommu_ops *iort_iommu_configure(struct device *dev)
|
||||
{ return NULL; }
|
||||
#endif
|
||||
|
||||
#define IORT_ACPI_DECLARE(name, table_id, fn) \
|
||||
ACPI_DECLARE_PROBE_ENTRY(iort, name, table_id, 0, NULL, 0, fn)
|
||||
|
||||
#endif /* __ACPI_IORT_H__ */
|
||||
|
|
|
|||
|
|
@ -17,8 +17,9 @@ enum fwnode_type {
|
|||
FWNODE_OF,
|
||||
FWNODE_ACPI,
|
||||
FWNODE_ACPI_DATA,
|
||||
FWNODE_ACPI_STATIC,
|
||||
FWNODE_PDATA,
|
||||
FWNODE_IRQCHIP,
|
||||
FWNODE_IRQCHIP
|
||||
};
|
||||
|
||||
struct fwnode_handle {
|
||||
|
|
|
|||
|
|
@ -351,6 +351,9 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode,
|
|||
const struct iommu_ops *ops);
|
||||
void iommu_fwspec_free(struct device *dev);
|
||||
int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids);
|
||||
void iommu_register_instance(struct fwnode_handle *fwnode,
|
||||
const struct iommu_ops *ops);
|
||||
const struct iommu_ops *iommu_get_instance(struct fwnode_handle *fwnode);
|
||||
|
||||
#else /* CONFIG_IOMMU_API */
|
||||
|
||||
|
|
@ -580,6 +583,17 @@ static inline int iommu_fwspec_add_ids(struct device *dev, u32 *ids,
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline void iommu_register_instance(struct fwnode_handle *fwnode,
|
||||
const struct iommu_ops *ops)
|
||||
{
|
||||
}
|
||||
|
||||
static inline
|
||||
const struct iommu_ops *iommu_get_instance(struct fwnode_handle *fwnode)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_IOMMU_API */
|
||||
|
||||
#endif /* __LINUX_IOMMU_H */
|
||||
|
|
|
|||
|
|
@ -31,8 +31,16 @@ static inline const struct iommu_ops *of_iommu_configure(struct device *dev,
|
|||
|
||||
#endif /* CONFIG_OF_IOMMU */
|
||||
|
||||
void of_iommu_set_ops(struct device_node *np, const struct iommu_ops *ops);
|
||||
const struct iommu_ops *of_iommu_get_ops(struct device_node *np);
|
||||
static inline void of_iommu_set_ops(struct device_node *np,
|
||||
const struct iommu_ops *ops)
|
||||
{
|
||||
iommu_register_instance(&np->fwnode, ops);
|
||||
}
|
||||
|
||||
static inline const struct iommu_ops *of_iommu_get_ops(struct device_node *np)
|
||||
{
|
||||
return iommu_get_instance(&np->fwnode);
|
||||
}
|
||||
|
||||
extern struct of_device_id __iommu_of_table;
|
||||
|
||||
|
|
|
|||
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