ARM: KVM: introduce per-vcpu HYP Configuration Register
So far, KVM/ARM used a fixed HCR configuration per guest, except for the VI/VF/VA bits to control the interrupt in absence of VGIC. With the upcoming need to dynamically reconfigure trapping, it becomes necessary to allow the HCR to be changed on a per-vcpu basis. The fix here is to mimic what KVM/arm64 already does: a per vcpu HCR field, initialized at setup time. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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Коммит
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@ -69,7 +69,6 @@
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#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
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HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
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HCR_TWE | HCR_SWIO | HCR_TIDCP)
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#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
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/* System Control Register (SCTLR) bits */
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#define SCTLR_TE (1 << 30)
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@ -101,6 +101,12 @@ struct kvm_vcpu_arch {
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/* The CPU type we expose to the VM */
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u32 midr;
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/* HYP trapping configuration */
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u32 hcr;
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/* Interrupt related fields */
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u32 irq_lines; /* IRQ and FIQ levels */
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/* Exception Information */
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struct kvm_vcpu_fault_info fault;
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@ -128,9 +134,6 @@ struct kvm_vcpu_arch {
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/* IO related fields */
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struct kvm_decode mmio_decode;
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/* Interrupt related fields */
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u32 irq_lines; /* IRQ and FIQ levels */
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/* Cache some mmu pages needed inside spinlock regions */
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struct kvm_mmu_memory_cache mmu_page_cache;
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@ -174,6 +174,7 @@ int main(void)
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DEFINE(VCPU_FIQ_REGS, offsetof(struct kvm_vcpu, arch.regs.fiq_regs));
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DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
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DEFINE(VCPU_CPSR, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
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DEFINE(VCPU_HCR, offsetof(struct kvm_vcpu, arch.hcr));
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DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines));
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DEFINE(VCPU_HSR, offsetof(struct kvm_vcpu, arch.fault.hsr));
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DEFINE(VCPU_HxFAR, offsetof(struct kvm_vcpu, arch.fault.hxfar));
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@ -38,6 +38,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
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int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr = HCR_GUEST_MASK;
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return 0;
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}
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@ -597,17 +597,14 @@ vcpu .req r0 @ vcpu pointer always in r0
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/* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */
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.macro configure_hyp_role operation
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mrc p15, 4, r2, c1, c1, 0 @ HCR
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bic r2, r2, #HCR_VIRT_EXCP_MASK
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ldr r3, =HCR_GUEST_MASK
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.if \operation == vmentry
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orr r2, r2, r3
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ldr r2, [vcpu, #VCPU_HCR]
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ldr r3, [vcpu, #VCPU_IRQ_LINES]
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orr r2, r2, r3
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.else
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bic r2, r2, r3
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mov r2, #0
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.endif
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mcr p15, 4, r2, c1, c1, 0
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mcr p15, 4, r2, c1, c1, 0 @ HCR
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.endm
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.macro load_vcpu
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