ARM: i.MX1 clk: Add devicetree support
This patch adds devicetree support CCM module for i.MX1 (MC9328MX1) CPUs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit is contained in:
Alexander Shiyan
Shawn Guo
Родитель
cd973e1cab
Коммит
ac36187b37
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* Clock bindings for Freescale i.MX1 CPUs
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Required properties:
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- compatible: Should be "fsl,imx1-ccm".
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- reg: Address and length of the register set.
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- #clock-cells: Should be <1>.
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
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for the full list of i.MX1 clock IDs.
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Examples:
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clks: ccm@0021b000 {
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#clock-cells = <1>;
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compatible = "fsl,imx1-ccm";
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reg = <0x0021b000 0x1000>;
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};
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pwm: pwm@00208000 {
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#pwm-cells = <2>;
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compatible = "fsl,imx1-pwm";
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reg = <0x00208000 0x1000>;
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interrupts = <34>;
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clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
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clock-names = "ipg", "per";
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};
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@ -15,100 +15,111 @@
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/imx1-clock.h>
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#include "clk.h"
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#include "common.h"
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#include "hardware.h"
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/* CCM register addresses */
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#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
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#define CCM_CSCR IO_ADDR_CCM(0x0)
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#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
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#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
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#define CCM_PCDR IO_ADDR_CCM(0x20)
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/* SCM register addresses */
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#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
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#define SCM_GCCR IO_ADDR_SCM(0xc)
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static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
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static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
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"prem", "fclk", };
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enum imx1_clks {
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dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate,
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spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko,
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uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate,
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usbd_gate, clk_max
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};
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static struct clk *clk[IMX1_CLK_MAX];
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static struct clk_onecell_data clk_data;
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static struct clk *clk[clk_max];
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static void __iomem *ccm __initdata;
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#define CCM_CSCR (ccm + 0x0000)
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#define CCM_MPCTL0 (ccm + 0x0004)
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#define CCM_SPCTL0 (ccm + 0x000c)
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#define CCM_PCDR (ccm + 0x0020)
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#define SCM_GCCR (ccm + 0x0810)
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int __init mx1_clocks_init(unsigned long fref)
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static void __init _mx1_clocks_init(unsigned long fref)
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{
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int i;
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unsigned i;
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[clk32] = imx_clk_fixed("clk32", fref);
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clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
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clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
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clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
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clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
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ARRAY_SIZE(prem_sel_clks));
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clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
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clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
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clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
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clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
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clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
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clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
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clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
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clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
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clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
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clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
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clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
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clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
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ARRAY_SIZE(clko_sel_clks));
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clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
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clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
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clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
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clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
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clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
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clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
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clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
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clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
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clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
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clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
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clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
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clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
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clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
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clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
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clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
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clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
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clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
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clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
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clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
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clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
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clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
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clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
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clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
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clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
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clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
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clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
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clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
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clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
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clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
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clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
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clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
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for (i = 0; i < ARRAY_SIZE(clk); i++)
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if (IS_ERR(clk[i]))
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pr_err("imx1 clk %d: register failed with %ld\n",
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i, PTR_ERR(clk[i]));
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clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
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clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
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clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
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clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
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clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
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clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
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clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
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clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
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clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
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clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2");
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clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
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clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
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clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
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clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
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clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
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clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
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clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
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clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
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clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
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clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
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}
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int __init mx1_clocks_init(unsigned long fref)
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{
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ccm = MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR);
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_mx1_clocks_init(fref);
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clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
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clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
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clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
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clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");
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clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");
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clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");
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clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");
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clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");
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clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");
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clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");
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clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");
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clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");
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clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");
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clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");
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clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
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clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
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mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
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return 0;
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}
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static void __init mx1_clocks_init_dt(struct device_node *np)
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{
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ccm = of_iomap(np, 0);
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BUG_ON(!ccm);
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_mx1_clocks_init(32768);
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));
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}
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CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);
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@ -0,0 +1,40 @@
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/*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX1_H
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#define __DT_BINDINGS_CLOCK_IMX1_H
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#define IMX1_CLK_DUMMY 0
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#define IMX1_CLK_CLK32 1
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#define IMX1_CLK_CLK16M_EXT 2
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#define IMX1_CLK_CLK16M 3
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#define IMX1_CLK_CLK32_PREMULT 4
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#define IMX1_CLK_PREM 5
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#define IMX1_CLK_MPLL 6
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#define IMX1_CLK_MPLL_GATE 7
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#define IMX1_CLK_SPLL 8
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#define IMX1_CLK_SPLL_GATE 9
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#define IMX1_CLK_MCU 10
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#define IMX1_CLK_FCLK 11
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#define IMX1_CLK_HCLK 12
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#define IMX1_CLK_CLK48M 13
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#define IMX1_CLK_PER1 14
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#define IMX1_CLK_PER2 15
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#define IMX1_CLK_PER3 16
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#define IMX1_CLK_CLKO 17
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#define IMX1_CLK_UART3_GATE 18
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#define IMX1_CLK_SSI2_GATE 19
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#define IMX1_CLK_BROM_GATE 20
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#define IMX1_CLK_DMA_GATE 21
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#define IMX1_CLK_CSI_GATE 22
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#define IMX1_CLK_MMA_GATE 23
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#define IMX1_CLK_USBD_GATE 24
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#define IMX1_CLK_MAX 25
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#endif
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