MIPS: OCTEON: More OCTEONIII support
Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII. Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8945/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Chandrakala Chavva
Ralf Baechle
Родитель
920cda3870
Коммит
ac6d9b3a03
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@ -18,7 +18,7 @@
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-ipd-defs.h>
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#include <asm/octeon/cvmx-mio-defs.h>
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#include <asm/octeon/cvmx-rst-defs.h>
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static u64 f;
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static u64 rdiv;
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@ -39,11 +39,20 @@ void __init octeon_setup_delays(void)
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if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
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union cvmx_mio_rst_boot rst_boot;
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rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
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rdiv = rst_boot.s.c_mul; /* CPU clock */
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sdiv = rst_boot.s.pnr_mul; /* I/O clock */
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f = (0x8000000000000000ull / sdiv) * 2;
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} else if (current_cpu_type() == CPU_CAVIUM_OCTEON3) {
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union cvmx_rst_boot rst_boot;
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rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
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rdiv = rst_boot.s.c_mul; /* CPU clock */
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sdiv = rst_boot.s.pnr_mul; /* I/O clock */
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f = (0x8000000000000000ull / sdiv) * 2;
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}
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}
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/*
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@ -41,6 +41,7 @@
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/pci-octeon.h>
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#include <asm/octeon/cvmx-mio-defs.h>
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#include <asm/octeon/cvmx-rst-defs.h>
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extern struct plat_smp_ops octeon_smp_ops;
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@ -653,11 +654,16 @@ void __init prom_init(void)
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sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
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sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
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if (OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) {
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if (OCTEON_IS_OCTEON2()) {
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/* I/O clock runs at a different rate than the CPU. */
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union cvmx_mio_rst_boot rst_boot;
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rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
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octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
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} else if (OCTEON_IS_OCTEON3()) {
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/* I/O clock runs at a different rate than the CPU. */
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union cvmx_rst_boot rst_boot;
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rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
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octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
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} else {
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octeon_io_clock_rate = sysinfo->cpu_clock_hz;
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}
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@ -80,6 +80,9 @@
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mfc0 v0, CP0_PRID_REG
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bbit0 v0, 15, 1f
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# OCTEON II or better have bit 15 set. Clear the error bits.
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and t1, v0, 0xff00
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dli v0, 0x9500
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bge t1, v0, 1f # OCTEON III has no DCACHE_ERR_REG COP0
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dli v0, 0x27
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dmtc0 v0, CP0_DCACHE_ERR_REG
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1:
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@ -0,0 +1,306 @@
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/***********************license start***************
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* Author: Cavium Inc.
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*
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* Contact: support@cavium.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2014 Cavium Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Inc. for more information
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***********************license end**************************************/
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#ifndef __CVMX_RST_DEFS_H__
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#define __CVMX_RST_DEFS_H__
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#define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull))
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#define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull))
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#define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull))
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#define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8)
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#define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull))
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#define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull))
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#define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull))
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#define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull))
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#define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull))
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#define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull))
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#define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8)
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#define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull))
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union cvmx_rst_boot {
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uint64_t u64;
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struct cvmx_rst_boot_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t chipkill:1;
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uint64_t jtcsrdis:1;
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uint64_t ejtagdis:1;
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uint64_t romen:1;
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uint64_t ckill_ppdis:1;
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uint64_t jt_tstmode:1;
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uint64_t vrm_err:1;
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uint64_t reserved_37_56:20;
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uint64_t c_mul:7;
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uint64_t pnr_mul:6;
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uint64_t reserved_21_23:3;
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uint64_t lboot_oci:3;
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uint64_t lboot_ext:6;
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uint64_t lboot:10;
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uint64_t rboot:1;
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uint64_t rboot_pin:1;
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#else
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uint64_t rboot_pin:1;
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uint64_t rboot:1;
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uint64_t lboot:10;
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uint64_t lboot_ext:6;
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uint64_t lboot_oci:3;
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uint64_t reserved_21_23:3;
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uint64_t pnr_mul:6;
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uint64_t c_mul:7;
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uint64_t reserved_37_56:20;
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uint64_t vrm_err:1;
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uint64_t jt_tstmode:1;
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uint64_t ckill_ppdis:1;
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uint64_t romen:1;
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uint64_t ejtagdis:1;
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uint64_t jtcsrdis:1;
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uint64_t chipkill:1;
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#endif
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} s;
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struct cvmx_rst_boot_s cn70xx;
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struct cvmx_rst_boot_s cn70xxp1;
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struct cvmx_rst_boot_s cn78xx;
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};
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union cvmx_rst_cfg {
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uint64_t u64;
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struct cvmx_rst_cfg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t bist_delay:58;
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uint64_t reserved_3_5:3;
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uint64_t cntl_clr_bist:1;
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uint64_t warm_clr_bist:1;
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uint64_t soft_clr_bist:1;
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#else
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uint64_t soft_clr_bist:1;
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uint64_t warm_clr_bist:1;
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uint64_t cntl_clr_bist:1;
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uint64_t reserved_3_5:3;
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uint64_t bist_delay:58;
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#endif
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} s;
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struct cvmx_rst_cfg_s cn70xx;
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struct cvmx_rst_cfg_s cn70xxp1;
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struct cvmx_rst_cfg_s cn78xx;
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};
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union cvmx_rst_ckill {
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uint64_t u64;
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struct cvmx_rst_ckill_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_47_63:17;
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uint64_t timer:47;
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#else
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uint64_t timer:47;
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uint64_t reserved_47_63:17;
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#endif
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} s;
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struct cvmx_rst_ckill_s cn70xx;
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struct cvmx_rst_ckill_s cn70xxp1;
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struct cvmx_rst_ckill_s cn78xx;
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};
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union cvmx_rst_ctlx {
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uint64_t u64;
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struct cvmx_rst_ctlx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_10_63:54;
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uint64_t prst_link:1;
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uint64_t rst_done:1;
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uint64_t rst_link:1;
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uint64_t host_mode:1;
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uint64_t reserved_4_5:2;
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uint64_t rst_drv:1;
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uint64_t rst_rcv:1;
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uint64_t rst_chip:1;
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uint64_t rst_val:1;
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#else
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uint64_t rst_val:1;
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uint64_t rst_chip:1;
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uint64_t rst_rcv:1;
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uint64_t rst_drv:1;
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uint64_t reserved_4_5:2;
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uint64_t host_mode:1;
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uint64_t rst_link:1;
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uint64_t rst_done:1;
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uint64_t prst_link:1;
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uint64_t reserved_10_63:54;
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#endif
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} s;
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struct cvmx_rst_ctlx_s cn70xx;
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struct cvmx_rst_ctlx_s cn70xxp1;
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struct cvmx_rst_ctlx_s cn78xx;
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};
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union cvmx_rst_delay {
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uint64_t u64;
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struct cvmx_rst_delay_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63:32;
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uint64_t warm_rst_dly:16;
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uint64_t soft_rst_dly:16;
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#else
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uint64_t soft_rst_dly:16;
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uint64_t warm_rst_dly:16;
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uint64_t reserved_32_63:32;
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#endif
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} s;
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struct cvmx_rst_delay_s cn70xx;
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struct cvmx_rst_delay_s cn70xxp1;
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struct cvmx_rst_delay_s cn78xx;
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};
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union cvmx_rst_eco {
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uint64_t u64;
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struct cvmx_rst_eco_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63:32;
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uint64_t eco_rw:32;
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#else
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uint64_t eco_rw:32;
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uint64_t reserved_32_63:32;
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#endif
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} s;
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struct cvmx_rst_eco_s cn78xx;
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};
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union cvmx_rst_int {
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uint64_t u64;
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struct cvmx_rst_int_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_12_63:52;
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uint64_t perst:4;
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uint64_t reserved_4_7:4;
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uint64_t rst_link:4;
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#else
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uint64_t rst_link:4;
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uint64_t reserved_4_7:4;
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uint64_t perst:4;
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uint64_t reserved_12_63:52;
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#endif
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} s;
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struct cvmx_rst_int_cn70xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_11_63:53;
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uint64_t perst:3;
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uint64_t reserved_3_7:5;
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uint64_t rst_link:3;
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#else
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uint64_t rst_link:3;
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uint64_t reserved_3_7:5;
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uint64_t perst:3;
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uint64_t reserved_11_63:53;
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#endif
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} cn70xx;
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struct cvmx_rst_int_cn70xx cn70xxp1;
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struct cvmx_rst_int_s cn78xx;
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};
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union cvmx_rst_ocx {
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uint64_t u64;
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struct cvmx_rst_ocx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_3_63:61;
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uint64_t rst_link:3;
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#else
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uint64_t rst_link:3;
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uint64_t reserved_3_63:61;
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#endif
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} s;
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struct cvmx_rst_ocx_s cn78xx;
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};
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union cvmx_rst_power_dbg {
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uint64_t u64;
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struct cvmx_rst_power_dbg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_3_63:61;
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uint64_t str:3;
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#else
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uint64_t str:3;
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uint64_t reserved_3_63:61;
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#endif
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} s;
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struct cvmx_rst_power_dbg_s cn78xx;
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};
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union cvmx_rst_pp_power {
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uint64_t u64;
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struct cvmx_rst_pp_power_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_48_63:16;
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uint64_t gate:48;
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#else
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uint64_t gate:48;
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uint64_t reserved_48_63:16;
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#endif
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} s;
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struct cvmx_rst_pp_power_cn70xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_4_63:60;
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uint64_t gate:4;
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#else
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uint64_t gate:4;
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uint64_t reserved_4_63:60;
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#endif
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} cn70xx;
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struct cvmx_rst_pp_power_cn70xx cn70xxp1;
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struct cvmx_rst_pp_power_s cn78xx;
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};
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union cvmx_rst_soft_prstx {
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uint64_t u64;
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struct cvmx_rst_soft_prstx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_1_63:63;
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uint64_t soft_prst:1;
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#else
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uint64_t soft_prst:1;
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uint64_t reserved_1_63:63;
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#endif
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} s;
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struct cvmx_rst_soft_prstx_s cn70xx;
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struct cvmx_rst_soft_prstx_s cn70xxp1;
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struct cvmx_rst_soft_prstx_s cn78xx;
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};
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union cvmx_rst_soft_rst {
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uint64_t u64;
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struct cvmx_rst_soft_rst_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_1_63:63;
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uint64_t soft_rst:1;
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#else
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uint64_t soft_rst:1;
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uint64_t reserved_1_63:63;
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#endif
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} s;
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struct cvmx_rst_soft_rst_s cn70xx;
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struct cvmx_rst_soft_rst_s cn70xxp1;
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struct cvmx_rst_soft_rst_s cn78xx;
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};
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#endif
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