mt8173:
- use assinged-clocks and assigned-clock-parents - fix compatible for SoC to a72 - add pmu nodes mt8183: - add sysirq binding - add pinctrl dt header file mt7629: - update bindings description fo sysirq, uart and scpsys mt8516: - add binding description for watchdog, timer, uart and sysirq -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAly/N3cXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00MgsQ/+PJskV7y1fW26XPg/fu7EkzMZ fxEfgvHncadJGz10B9UF4t5+B+WW3HyY1kklzOhVsBSk3psMCYIu/J09MSPFtAgX yZ8Xeo8inwKakOwn3jY4a8sloilNFaJX5zJZLVLWHMoBPMugvy2ROBquMxFHdM7r yde6ZoKxR0XPyRr1abbma8cmGS2UZA9pD9Vakawk34NcmADKNwwtl23LXAitevCR xfa8Ln0vsRUpz9JZSQ32yYGnE4OsxkOFn8dwtiKlKd8wzxExGRU+8E5kVZlX9P3f oe5EsRW+3whCEzF+rW9udjAOeYrdDBckR3vsho34TVWOkdGpunj/duvNOLLKD0sl +mzEty+tWDEc6IK0aEJT6SK87WfLOLIOYIWLA2eSd3kjoB48XmxQ+WUB2ogAgZzQ AsUWjGKwbse1xKjMTV1A8AJsDLN8lMwURyVmaSjA3HOhC3BC2X25XGBQ+srogSzj U6h128D5OKiXqp+n2EwCmfX+NKlWgT6IPENgRiaALfahGelWhpdhKRMF5v4jOgXO 6ev/djagiqpLz4zIO7RnisbdqcObhxRobWOwmnHBa6BkdHxs+8EH7X8jnVXoIN2/ 43plOEn7Wt7sMBdRdzrSM6m7PaRn1ttefHq4YQx2TaNJj3AGBYwS7rCCVlwtgXck HtYZ4FCkNeqOhTq7/EY= =KVpr -----END PGP SIGNATURE----- Merge tag 'v5.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt mt8173: - use assinged-clocks and assigned-clock-parents - fix compatible for SoC to a72 - add pmu nodes mt8183: - add sysirq binding - add pinctrl dt header file mt7629: - update bindings description fo sysirq, uart and scpsys mt8516: - add binding description for watchdog, timer, uart and sysirq * tag 'v5.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm64: dts: mt8173: add pmu nodes for mt8173 arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72 dt-bindings: irq: mtk,sysirq: add support for MT8516 dt-bindings: serial: mtk-uart: add support for MT8516 dt-bindings: timer: mtk-timer: add support for MT8516 dt-bindings: wdog: mtk-wdt: add support for MT851 dt-bindings: soc: fix a typo for MT7623A dt-bindings: mediatek: update bindings for MT7629 SoC arm64: dts: mt8183: add pinctrl file dt-bindings: mtk-sysirq: Add compatible for Mediatek MT8183 arm64: dts: Using standard CCF interface to set vcodec clk Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
ad88400145
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@ -1,15 +1,18 @@
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+Mediatek MT65xx/MT67xx/MT81xx sysirq
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MediaTek sysirq
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Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
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MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
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interrupt.
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Required properties:
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- compatible: should be
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"mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
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"mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
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"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
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"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
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"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
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"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
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"mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
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"mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
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"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
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"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
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"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
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@ -1,4 +1,4 @@
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* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
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* MediaTek Universal Asynchronous Receiver/Transmitter (UART)
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Required properties:
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- compatible should contain:
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@ -13,10 +13,12 @@ Required properties:
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* "mediatek,mt6797-uart" for MT6797 compatible UARTS
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* "mediatek,mt7622-uart" for MT7622 compatible UARTS
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* "mediatek,mt7623-uart" for MT7623 compatible UARTS
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* "mediatek,mt7629-uart" for MT7629 compatible UARTS
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* "mediatek,mt8127-uart" for MT8127 compatible UARTS
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* "mediatek,mt8135-uart" for MT8135 compatible UARTS
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* "mediatek,mt8173-uart" for MT8173 compatible UARTS
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* "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
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* "mediatek,mt8516-uart" for MT8516 compatible UARTS
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* "mediatek,mt6577-uart" for MT6577 and all of the above
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- reg: The base address of the UART register bank.
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@ -23,6 +23,7 @@ Required properties:
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- "mediatek,mt7622-scpsys"
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- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
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- "mediatek,mt7623a-scpsys": For MT7623A SoC
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- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
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- "mediatek,mt8173-scpsys"
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- #power-domain-cells: Must be 1
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- reg: Address range of the SCPSYS unit
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@ -33,8 +34,8 @@ Required properties:
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Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
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Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
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Required clocks for MT6797: "mm", "mfg", "vdec"
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Required clocks for MT7622: "hif_sel"
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Required clocks for MT7622A: "ethif"
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Required clocks for MT7622 or MT7629: "hif_sel"
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Required clocks for MT7623A: "ethif"
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Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
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Optional properties:
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@ -17,6 +17,7 @@ Required properties:
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* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
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* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
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* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
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* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
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* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
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For those SoCs that use SYST
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@ -9,6 +9,7 @@ Required properties:
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"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
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"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
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"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
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"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
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- reg : Specifies base physical address and size of the registers.
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@ -178,12 +178,12 @@
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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compatible = "arm,cortex-a72";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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#cooling-cells = <2>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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clocks = <&infracfg CLK_INFRA_CA72SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster1_opp>;
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@ -191,12 +191,12 @@
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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compatible = "arm,cortex-a72";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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#cooling-cells = <2>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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clocks = <&infracfg CLK_INFRA_CA72SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster1_opp>;
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@ -216,6 +216,20 @@
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};
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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pmu_a72 {
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compatible = "arm,cortex-a72-pmu";
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
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interrupt-affinity = <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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@ -1307,6 +1321,15 @@
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"vencpll",
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"venc_lt_sel",
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"vdec_bus_clk_src";
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assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
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<&topckgen CLK_TOP_CCI400_SEL>,
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<&topckgen CLK_TOP_VDEC_SEL>,
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<&apmixedsys CLK_APMIXED_VCODECPLL>,
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<&apmixedsys CLK_APMIXED_VENCPLL>;
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assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
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<&topckgen CLK_TOP_UNIVPLL_D2>,
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<&topckgen CLK_TOP_VCODECPLL>;
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assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
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};
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larb1: larb@16010000 {
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@ -1372,6 +1395,10 @@
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"venc_sel",
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"venc_lt_sel_src",
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"venc_lt_sel";
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assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
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<&topckgen CLK_TOP_UNIVPLL1_D2>;
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};
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vencltsys: clock-controller@19000000 {
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