usb: gadget: net2280: Add support for PLX USB338X
This patch adds support for the PLX USB3380 and USB3382. This driver is based on the driver from the manufacturer. Since USB338X is register compatible with NET2280, I thought that it would be better to include this hardware into net2280 driver. Manufacturer's driver only supported the USB33X, did not follow the Kernel Style and contain some trivial errors. This patch has tried to address this issues. This patch has only been tested on USB338x hardware, but the merge has been done trying to not affect the behaviour of NET2280. Tested-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Ricardo Ribalda Delgado
Felipe Balbi
Родитель
dad833823f
Коммит
adc82f77be
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@ -409,7 +409,7 @@ config USB_NET2272_DMA
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If unsure, say "N" here. The driver works fine in PIO mode.
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config USB_NET2280
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tristate "NetChip 228x"
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tristate "NetChip 228x / PLX USB338x"
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depends on PCI
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help
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NetChip 2280 / 2282 is a PCI based USB peripheral controller which
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@ -419,6 +419,14 @@ config USB_NET2280
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(for control transfers) and several endpoints with dedicated
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functions.
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PLX 3380 / 3382 is a PCIe based USB peripheral controller which
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supports full, high speed USB 2.0 and super speed USB 3.0
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data transfers.
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It has eight configurable endpoints, as well as endpoint zero
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(for control transfers) and several endpoints with dedicated
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functions.
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Say "y" to link the driver statically, or "m" to build a
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dynamically linked module called "net2280" and force all
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gadget drivers to also be dynamically linked.
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -6,6 +6,7 @@
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/*
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* Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
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* Copyright (C) 2003 David Brownell
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* Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -14,6 +15,7 @@
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*/
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#include <linux/usb/net2280.h>
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#include <linux/usb/usb338x.h>
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/*-------------------------------------------------------------------------*/
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@ -59,13 +61,14 @@ set_idx_reg (struct net2280_regs __iomem *regs, u32 index, u32 value)
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#define CHIPREV_1 0x0100
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#define CHIPREV_1A 0x0110
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#ifdef __KERNEL__
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/* DEFECT 7374 */
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#define DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS 200
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#define DEFECT_7374_PROCESSOR_WAIT_TIME 10
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/* ep a-f highspeed and fullspeed maxpacket, addresses
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* computed from ep->num
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*/
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#define REG_EP_MAXPKT(dev,num) (((num) + 1) * 0x10 + \
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(((dev)->gadget.speed == USB_SPEED_HIGH) ? 0 : 1))
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/* ep0 max packet size */
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#define EP0_SS_MAX_PACKET_SIZE 0x200
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#define EP0_HS_MAX_PACKET_SIZE 0x40
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#ifdef __KERNEL__
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/*-------------------------------------------------------------------------*/
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@ -85,12 +88,15 @@ struct net2280_dma {
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struct net2280_ep {
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struct usb_ep ep;
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struct net2280_ep_regs __iomem *cfg;
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struct net2280_ep_regs __iomem *regs;
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struct net2280_dma_regs __iomem *dma;
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struct net2280_dma *dummy;
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struct usb338x_fifo_regs __iomem *fiforegs;
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dma_addr_t td_dma; /* of dummy */
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struct net2280 *dev;
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unsigned long irqs;
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unsigned is_halt:1, dma_started:1;
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/* analogous to a host-side qh */
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struct list_head queue;
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@ -116,10 +122,19 @@ static inline void allow_status (struct net2280_ep *ep)
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ep->stopped = 1;
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}
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/* count (<= 4) bytes in the next fifo write will be valid */
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static inline void set_fifo_bytecount (struct net2280_ep *ep, unsigned count)
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static void allow_status_338x(struct net2280_ep *ep)
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{
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writeb (count, 2 + (u8 __iomem *) &ep->regs->ep_cfg);
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/*
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* Control Status Phase Handshake was set by the chip when the setup
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* packet arrived. While set, the chip automatically NAKs the host's
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* Status Phase tokens.
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*/
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writel(1 << CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE, &ep->regs->ep_rsp);
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ep->stopped = 1;
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/* TD 9.9 Halt Endpoint test. TD 9.22 set feature test. */
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ep->responded = 0;
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}
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struct net2280_request {
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@ -135,23 +150,38 @@ struct net2280 {
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/* each pci device provides one gadget, several endpoints */
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struct usb_gadget gadget;
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spinlock_t lock;
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struct net2280_ep ep [7];
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struct net2280_ep ep[9];
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struct usb_gadget_driver *driver;
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unsigned enabled : 1,
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protocol_stall : 1,
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softconnect : 1,
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got_irq : 1,
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region : 1;
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region:1,
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u1_enable:1,
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u2_enable:1,
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ltm_enable:1,
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wakeup_enable:1,
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selfpowered:1,
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addressed_state:1;
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u16 chiprev;
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int enhanced_mode;
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int n_ep;
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/* pci state used to access those endpoints */
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struct pci_dev *pdev;
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struct net2280_regs __iomem *regs;
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struct net2280_usb_regs __iomem *usb;
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struct usb338x_usb_ext_regs __iomem *usb_ext;
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struct net2280_pci_regs __iomem *pci;
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struct net2280_dma_regs __iomem *dma;
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struct net2280_dep_regs __iomem *dep;
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struct net2280_ep_regs __iomem *epregs;
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struct usb338x_fifo_regs __iomem *fiforegs;
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struct usb338x_ll_regs __iomem *llregs;
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struct usb338x_ll_lfps_regs __iomem *ll_lfps_regs;
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struct usb338x_ll_tsn_regs __iomem *ll_tsn_regs;
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struct usb338x_ll_chi_regs __iomem *ll_chicken_reg;
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struct usb338x_pl_regs __iomem *plregs;
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struct pci_pool *requests;
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// statistics...
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@ -179,6 +209,43 @@ static inline void clear_halt (struct net2280_ep *ep)
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, &ep->regs->ep_rsp);
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}
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/*
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* FSM value for Defect 7374 (U1U2 Test) is managed in
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* chip's SCRATCH register:
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*/
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#define DEFECT7374_FSM_FIELD 28
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/* Waiting for Control Read:
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* - A transition to this state indicates a fresh USB connection,
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* before the first Setup Packet. The connection speed is not
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* known. Firmware is waiting for the first Control Read.
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* - Starting state: This state can be thought of as the FSM's typical
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* starting state.
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* - Tip: Upon the first SS Control Read the FSM never
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* returns to this state.
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*/
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#define DEFECT7374_FSM_WAITING_FOR_CONTROL_READ (1 << DEFECT7374_FSM_FIELD)
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/* Non-SS Control Read:
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* - A transition to this state indicates detection of the first HS
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* or FS Control Read.
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* - Tip: Upon the first SS Control Read the FSM never
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* returns to this state.
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*/
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#define DEFECT7374_FSM_NON_SS_CONTROL_READ (2 << DEFECT7374_FSM_FIELD)
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/* SS Control Read:
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* - A transition to this state indicates detection of the
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* first SS Control Read.
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* - This state indicates workaround completion. Workarounds no longer
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* need to be applied (as long as the chip remains powered up).
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* - Tip: Once in this state the FSM state does not change (until
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* the chip's power is lost and restored).
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* - This can be thought of as the final state of the FSM;
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* the FSM 'locks-up' in this state until the chip loses power.
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*/
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#define DEFECT7374_FSM_SS_CONTROL_READ (3 << DEFECT7374_FSM_FIELD)
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#ifdef USE_RDK_LEDS
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static inline void net2280_led_init (struct net2280 *dev)
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@ -198,6 +265,9 @@ void net2280_led_speed (struct net2280 *dev, enum usb_device_speed speed)
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{
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u32 val = readl (&dev->regs->gpioctl);
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switch (speed) {
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case USB_SPEED_SUPER: /* green + red */
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val |= (1 << GPIO0_DATA) | (1 << GPIO1_DATA);
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break;
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case USB_SPEED_HIGH: /* green */
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val &= ~(1 << GPIO0_DATA);
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val |= (1 << GPIO1_DATA);
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@ -271,6 +341,17 @@ static inline void net2280_led_shutdown (struct net2280 *dev)
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/*-------------------------------------------------------------------------*/
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static inline void set_fifo_bytecount(struct net2280_ep *ep, unsigned count)
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{
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if (ep->dev->pdev->vendor == 0x17cc)
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writeb(count, 2 + (u8 __iomem *) &ep->regs->ep_cfg);
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else{
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u32 tmp = readl(&ep->cfg->ep_cfg) &
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(~(0x07 << EP_FIFO_BYTE_COUNT));
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writel(tmp | (count << EP_FIFO_BYTE_COUNT), &ep->cfg->ep_cfg);
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}
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}
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static inline void start_out_naking (struct net2280_ep *ep)
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{
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/* NOTE: hardware races lurk here, and PING protocol issues */
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@ -305,4 +386,22 @@ static inline void stop_out_naking (struct net2280_ep *ep)
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writel ((1 << CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
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}
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static inline void set_max_speed(struct net2280_ep *ep, u32 max)
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{
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u32 reg;
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static const u32 ep_enhanced[9] = { 0x10, 0x60, 0x30, 0x80,
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0x50, 0x20, 0x70, 0x40, 0x90 };
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if (ep->dev->enhanced_mode)
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reg = ep_enhanced[ep->num];
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else{
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reg = (ep->num + 1) * 0x10;
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if (ep->dev->gadget.speed != USB_SPEED_HIGH)
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reg += 1;
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}
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set_idx_reg(ep->dev->regs, reg, max);
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}
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#endif /* __KERNEL__ */
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@ -0,0 +1,199 @@
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/*
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* USB 338x super/high/full speed USB device controller.
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* Unlike many such controllers, this one talks PCI.
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*
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* Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
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* Copyright (C) 2003 David Brownell
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* Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __LINUX_USB_USB338X_H
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#define __LINUX_USB_USB338X_H
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#include <linux/usb/net2280.h>
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/*
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* Extra defined bits for net2280 registers
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*/
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#define SCRATCH 0x0b
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#define DEFECT7374_FSM_FIELD 28
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#define SUPER_SPEED 8
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#define DMA_REQUEST_OUTSTANDING 5
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#define DMA_PAUSE_DONE_INTERRUPT 26
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#define SET_ISOCHRONOUS_DELAY 24
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#define SET_SEL 22
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#define SUPER_SPEED_MODE 8
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/*ep_cfg*/
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#define MAX_BURST_SIZE 24
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#define EP_FIFO_BYTE_COUNT 16
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#define IN_ENDPOINT_ENABLE 14
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#define IN_ENDPOINT_TYPE 12
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#define OUT_ENDPOINT_ENABLE 10
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#define OUT_ENDPOINT_TYPE 8
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struct usb338x_usb_ext_regs {
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u32 usbclass;
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#define DEVICE_PROTOCOL 16
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#define DEVICE_SUB_CLASS 8
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#define DEVICE_CLASS 0
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u32 ss_sel;
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#define U2_SYSTEM_EXIT_LATENCY 8
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#define U1_SYSTEM_EXIT_LATENCY 0
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u32 ss_del;
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#define U2_DEVICE_EXIT_LATENCY 8
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#define U1_DEVICE_EXIT_LATENCY 0
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u32 usb2lpm;
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#define USB_L1_LPM_HIRD 2
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#define USB_L1_LPM_REMOTE_WAKE 1
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#define USB_L1_LPM_SUPPORT 0
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u32 usb3belt;
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#define BELT_MULTIPLIER 10
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#define BEST_EFFORT_LATENCY_TOLERANCE 0
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u32 usbctl2;
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#define LTM_ENABLE 7
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#define U2_ENABLE 6
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#define U1_ENABLE 5
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#define FUNCTION_SUSPEND 4
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#define USB3_CORE_ENABLE 3
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#define USB2_CORE_ENABLE 2
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#define SERIAL_NUMBER_STRING_ENABLE 0
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u32 in_timeout;
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#define GPEP3_TIMEOUT 19
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#define GPEP2_TIMEOUT 18
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#define GPEP1_TIMEOUT 17
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#define GPEP0_TIMEOUT 16
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#define GPEP3_TIMEOUT_VALUE 13
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#define GPEP3_TIMEOUT_ENABLE 12
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#define GPEP2_TIMEOUT_VALUE 9
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#define GPEP2_TIMEOUT_ENABLE 8
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#define GPEP1_TIMEOUT_VALUE 5
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#define GPEP1_TIMEOUT_ENABLE 4
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#define GPEP0_TIMEOUT_VALUE 1
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#define GPEP0_TIMEOUT_ENABLE 0
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u32 isodelay;
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#define ISOCHRONOUS_DELAY 0
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} __packed;
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struct usb338x_fifo_regs {
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/* offset 0x0500, 0x0520, 0x0540, 0x0560, 0x0580 */
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u32 ep_fifo_size_base;
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#define IN_FIFO_BASE_ADDRESS 22
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#define IN_FIFO_SIZE 16
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#define OUT_FIFO_BASE_ADDRESS 6
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#define OUT_FIFO_SIZE 0
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u32 ep_fifo_out_wrptr;
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u32 ep_fifo_out_rdptr;
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u32 ep_fifo_in_wrptr;
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u32 ep_fifo_in_rdptr;
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u32 unused[3];
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} __packed;
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/* Link layer */
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struct usb338x_ll_regs {
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/* offset 0x700 */
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u32 ll_ltssm_ctrl1;
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u32 ll_ltssm_ctrl2;
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u32 ll_ltssm_ctrl3;
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u32 unused[2];
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u32 ll_general_ctrl0;
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u32 ll_general_ctrl1;
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#define PM_U3_AUTO_EXIT 29
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#define PM_U2_AUTO_EXIT 28
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#define PM_U1_AUTO_EXIT 27
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#define PM_FORCE_U2_ENTRY 26
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#define PM_FORCE_U1_ENTRY 25
|
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#define PM_LGO_COLLISION_SEND_LAU 24
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#define PM_DIR_LINK_REJECT 23
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#define PM_FORCE_LINK_ACCEPT 22
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#define PM_DIR_ENTRY_U3 20
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#define PM_DIR_ENTRY_U2 19
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#define PM_DIR_ENTRY_U1 18
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#define PM_U2_ENABLE 17
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#define PM_U1_ENABLE 16
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#define SKP_THRESHOLD_ADJUST_FMW 8
|
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#define RESEND_DPP_ON_LRTY_FMW 7
|
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#define DL_BIT_VALUE_FMW 6
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#define FORCE_DL_BIT 5
|
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u32 ll_general_ctrl2;
|
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#define SELECT_INVERT_LANE_POLARITY 7
|
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#define FORCE_INVERT_LANE_POLARITY 6
|
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u32 ll_general_ctrl3;
|
||||
u32 ll_general_ctrl4;
|
||||
u32 ll_error_gen;
|
||||
} __packed;
|
||||
|
||||
struct usb338x_ll_lfps_regs {
|
||||
/* offset 0x748 */
|
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u32 ll_lfps_5;
|
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#define TIMER_LFPS_6US 16
|
||||
u32 ll_lfps_6;
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#define TIMER_LFPS_80US 0
|
||||
} __packed;
|
||||
|
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struct usb338x_ll_tsn_regs {
|
||||
/* offset 0x77C */
|
||||
u32 ll_tsn_counters_2;
|
||||
#define HOT_TX_NORESET_TS2 24
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u32 ll_tsn_counters_3;
|
||||
#define HOT_RX_RESET_TS2 0
|
||||
} __packed;
|
||||
|
||||
struct usb338x_ll_chi_regs {
|
||||
/* offset 0x79C */
|
||||
u32 ll_tsn_chicken_bit;
|
||||
#define RECOVERY_IDLE_TO_RECOVER_FMW 3
|
||||
} __packed;
|
||||
|
||||
/* protocol layer */
|
||||
struct usb338x_pl_regs {
|
||||
/* offset 0x800 */
|
||||
u32 pl_reg_1;
|
||||
u32 pl_reg_2;
|
||||
u32 pl_reg_3;
|
||||
u32 pl_reg_4;
|
||||
u32 pl_ep_ctrl;
|
||||
/* Protocol Layer Endpoint Control*/
|
||||
#define PL_EP_CTRL 0x810
|
||||
#define ENDPOINT_SELECT 0
|
||||
/* [4:0] */
|
||||
#define EP_INITIALIZED 16
|
||||
#define SEQUENCE_NUMBER_RESET 17
|
||||
#define CLEAR_ACK_ERROR_CODE 20
|
||||
u32 pl_reg_6;
|
||||
u32 pl_reg_7;
|
||||
u32 pl_reg_8;
|
||||
u32 pl_ep_status_1;
|
||||
/* Protocol Layer Endpoint Status 1*/
|
||||
#define PL_EP_STATUS_1 0x820
|
||||
#define STATE 16
|
||||
#define ACK_GOOD_NORMAL 0x11
|
||||
#define ACK_GOOD_MORE_ACKS_TO_COME 0x16
|
||||
u32 pl_ep_status_2;
|
||||
u32 pl_ep_status_3;
|
||||
/* Protocol Layer Endpoint Status 3*/
|
||||
#define PL_EP_STATUS_3 0x828
|
||||
#define SEQUENCE_NUMBER 0
|
||||
u32 pl_ep_status_4;
|
||||
/* Protocol Layer Endpoint Status 4*/
|
||||
#define PL_EP_STATUS_4 0x82c
|
||||
u32 pl_ep_cfg_4;
|
||||
/* Protocol Layer Endpoint Configuration 4*/
|
||||
#define PL_EP_CFG_4 0x830
|
||||
#define NON_CTRL_IN_TOLERATE_BAD_DIR 6
|
||||
} __packed;
|
||||
|
||||
#endif /* __LINUX_USB_USB338X_H */
|
||||
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