drm/exynos: mixer: convert booleans to flags in mixer context
The mixer context struct already has a 'flags' field, so we can use it to store the 'interlace', 'vp_enabled' and 'has_sclk' booleans. We use the non-atomic helper functions to access these bits. Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
This commit is contained in:
Tobias Jakobi
Inki Dae
Родитель
c0d656dd2d
Коммит
adeb6f4485
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@ -73,6 +73,9 @@ enum mixer_version_id {
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enum mixer_flag_bits {
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MXR_BIT_POWERED,
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MXR_BIT_VSYNC,
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MXR_BIT_INTERLACE,
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MXR_BIT_VP_ENABLED,
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MXR_BIT_HAS_SCLK,
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};
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static const uint32_t mixer_formats[] = {
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@ -98,9 +101,6 @@ struct mixer_context {
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struct exynos_drm_plane planes[MIXER_WIN_NR];
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int pipe;
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unsigned long flags;
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bool interlace;
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bool vp_enabled;
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bool has_sclk;
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struct mixer_resources mixer_res;
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enum mixer_version_id mxr_ver;
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@ -346,7 +346,7 @@ static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
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mixer_reg_writemask(res, MXR_STATUS, enable ?
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MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
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if (ctx->vp_enabled)
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if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags))
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vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
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VP_SHADOW_UPDATE_ENABLE : 0);
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}
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@ -357,8 +357,8 @@ static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
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u32 val;
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/* choosing between interlace and progressive mode */
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val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE :
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MXR_CFG_SCAN_PROGRESSIVE);
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val = test_bit(MXR_BIT_INTERLACE, &ctx->flags) ?
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MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRESSIVE;
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if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
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/* choosing between proper HD and SD mode */
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@ -436,9 +436,10 @@ static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
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mixer_reg_writemask(res, MXR_LAYER_CFG,
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MXR_LAYER_CFG_GRP1_VAL(priority),
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MXR_LAYER_CFG_GRP1_MASK);
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break;
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case VP_DEFAULT_WIN:
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if (ctx->vp_enabled) {
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if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
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vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
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mixer_reg_writemask(res, MXR_CFG, val,
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MXR_CFG_VP_ENABLE);
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@ -501,7 +502,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
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chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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ctx->interlace = true;
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__set_bit(MXR_BIT_INTERLACE, &ctx->flags);
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if (tiled_mode) {
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luma_addr[1] = luma_addr[0] + 0x40;
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chroma_addr[1] = chroma_addr[0] + 0x40;
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@ -510,7 +511,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
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chroma_addr[1] = chroma_addr[0] + fb->pitches[0];
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}
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} else {
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ctx->interlace = false;
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__clear_bit(MXR_BIT_INTERLACE, &ctx->flags);
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luma_addr[1] = 0;
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chroma_addr[1] = 0;
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}
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@ -518,7 +519,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
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spin_lock_irqsave(&res->reg_slock, flags);
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/* interlace or progressive scan mode */
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val = (ctx->interlace ? ~0 : 0);
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val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
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vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
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/* setup format */
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@ -541,7 +542,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
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vp_reg_write(res, VP_DST_WIDTH, state->crtc.w);
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vp_reg_write(res, VP_DST_H_POSITION, state->crtc.x);
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if (ctx->interlace) {
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if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
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vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h / 2);
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vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y / 2);
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} else {
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@ -636,9 +637,9 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
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src_y_offset = 0;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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ctx->interlace = true;
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__set_bit(MXR_BIT_INTERLACE, &ctx->flags);
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else
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ctx->interlace = false;
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__clear_bit(MXR_BIT_INTERLACE, &ctx->flags);
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spin_lock_irqsave(&res->reg_slock, flags);
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@ -733,7 +734,7 @@ static void mixer_win_reset(struct mixer_context *ctx)
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mixer_reg_write(res, MXR_BG_COLOR1, 0x008080);
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mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
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if (ctx->vp_enabled) {
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if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
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/* configuration of Video Processor Registers */
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vp_win_reset(ctx);
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vp_default_filter(res);
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@ -742,7 +743,7 @@ static void mixer_win_reset(struct mixer_context *ctx)
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/* disable all layers */
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mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
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mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
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if (ctx->vp_enabled)
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if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags))
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mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
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spin_unlock_irqrestore(&res->reg_slock, flags);
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@ -767,7 +768,7 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
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val &= ~MXR_INT_STATUS_VSYNC;
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/* interlace scan need to check shadow register */
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if (ctx->interlace) {
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if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
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base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
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shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
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if (base != shadow)
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@ -867,7 +868,7 @@ static int vp_resources_init(struct mixer_context *mixer_ctx)
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return -ENODEV;
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}
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if (mixer_ctx->has_sclk) {
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if (test_bit(MXR_BIT_HAS_SCLK, &mixer_ctx->flags)) {
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mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
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if (IS_ERR(mixer_res->sclk_mixer)) {
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dev_err(dev, "failed to get clock 'sclk_mixer'\n");
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@ -917,7 +918,7 @@ static int mixer_initialize(struct mixer_context *mixer_ctx,
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return ret;
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}
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if (mixer_ctx->vp_enabled) {
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if (test_bit(MXR_BIT_VP_ENABLED, &mixer_ctx->flags)) {
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/* acquire vp resources: regs, irqs, clocks */
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ret = vp_resources_init(mixer_ctx);
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if (ret) {
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@ -1160,7 +1161,8 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
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return ret;
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for (i = 0; i < MIXER_WIN_NR; i++) {
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if (i == VP_DEFAULT_WIN && !ctx->vp_enabled)
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if (i == VP_DEFAULT_WIN && !test_bit(MXR_BIT_VP_ENABLED,
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&ctx->flags))
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continue;
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ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
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@ -1215,10 +1217,13 @@ static int mixer_probe(struct platform_device *pdev)
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ctx->pdev = pdev;
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ctx->dev = dev;
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ctx->vp_enabled = drv->is_vp_enabled;
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ctx->has_sclk = drv->has_sclk;
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ctx->mxr_ver = drv->version;
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if (drv->is_vp_enabled)
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__set_bit(MXR_BIT_VP_ENABLED, &ctx->flags);
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if (drv->has_sclk)
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__set_bit(MXR_BIT_HAS_SCLK, &ctx->flags);
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platform_set_drvdata(pdev, ctx);
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ret = component_add(&pdev->dev, &mixer_component_ops);
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@ -1244,9 +1249,9 @@ static int __maybe_unused exynos_mixer_suspend(struct device *dev)
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clk_disable_unprepare(res->hdmi);
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clk_disable_unprepare(res->mixer);
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if (ctx->vp_enabled) {
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if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
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clk_disable_unprepare(res->vp);
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if (ctx->has_sclk)
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if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags))
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clk_disable_unprepare(res->sclk_mixer);
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}
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@ -1269,14 +1274,14 @@ static int __maybe_unused exynos_mixer_resume(struct device *dev)
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DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret);
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return ret;
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}
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if (ctx->vp_enabled) {
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if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
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ret = clk_prepare_enable(res->vp);
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if (ret < 0) {
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DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n",
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ret);
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return ret;
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}
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if (ctx->has_sclk) {
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if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) {
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ret = clk_prepare_enable(res->sclk_mixer);
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if (ret < 0) {
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DRM_ERROR("Failed to prepare_enable the " \
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