drm/amd/display: Fix vblank refcount in vrr transition
commit 8799c0be89
upstream.
manage_dm_interrupts disable/enable vblank using drm_crtc_vblank_off/on
which causes drm_crtc_vblank_get in vrr_transition to fail, and later
when drm_crtc_vblank_put is called the refcount on vblank will be messed
up. Therefore move the call to after manage_dm_interrupts.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1247
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1380
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Родитель
60a5174525
Коммит
adf428ae46
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@ -8860,15 +8860,15 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
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* We also need vupdate irq for the actual core vblank handling
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* at end of vblank.
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*/
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dm_set_vupdate_irq(new_state->base.crtc, true);
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drm_crtc_vblank_get(new_state->base.crtc);
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WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0);
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WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
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DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
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__func__, new_state->base.crtc->base.id);
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} else if (old_vrr_active && !new_vrr_active) {
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/* Transition VRR active -> inactive:
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* Allow vblank irq disable again for fixed refresh rate.
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*/
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dm_set_vupdate_irq(new_state->base.crtc, false);
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WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0);
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drm_crtc_vblank_put(new_state->base.crtc);
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DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
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__func__, new_state->base.crtc->base.id);
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@ -9604,23 +9604,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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mutex_unlock(&dm->dc_lock);
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}
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/* Count number of newly disabled CRTCs for dropping PM refs later. */
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for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
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new_crtc_state, i) {
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if (old_crtc_state->active && !new_crtc_state->active)
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crtc_disable_count++;
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dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
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dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
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/* For freesync config update on crtc state and params for irq */
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update_stream_irq_parameters(dm, dm_new_crtc_state);
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/* Handle vrr on->off / off->on transitions */
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amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
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dm_new_crtc_state);
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}
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/**
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* Enable interrupts for CRTCs that are newly enabled or went through
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* a modeset. It was intentionally deferred until after the front end
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@ -9630,16 +9613,29 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
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#ifdef CONFIG_DEBUG_FS
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bool configure_crc = false;
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enum amdgpu_dm_pipe_crc_source cur_crc_src;
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#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
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struct crc_rd_work *crc_rd_wrk = dm->crc_rd_wrk;
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struct crc_rd_work *crc_rd_wrk;
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#endif
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#endif
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/* Count number of newly disabled CRTCs for dropping PM refs later. */
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if (old_crtc_state->active && !new_crtc_state->active)
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crtc_disable_count++;
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dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
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dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
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/* For freesync config update on crtc state and params for irq */
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update_stream_irq_parameters(dm, dm_new_crtc_state);
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#ifdef CONFIG_DEBUG_FS
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#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
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crc_rd_wrk = dm->crc_rd_wrk;
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#endif
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spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
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cur_crc_src = acrtc->dm_irq_params.crc_src;
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spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
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#endif
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dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
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if (new_crtc_state->active &&
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(!old_crtc_state->active ||
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@ -9647,16 +9643,19 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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dc_stream_retain(dm_new_crtc_state->stream);
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acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
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manage_dm_interrupts(adev, acrtc, true);
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}
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/* Handle vrr on->off / off->on transitions */
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amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
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#ifdef CONFIG_DEBUG_FS
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if (new_crtc_state->active &&
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(!old_crtc_state->active ||
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drm_atomic_crtc_needs_modeset(new_crtc_state))) {
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/**
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* Frontend may have changed so reapply the CRC capture
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* settings for the stream.
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*/
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dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
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if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
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configure_crc = true;
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#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
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if (amdgpu_dm_crc_window_is_activated(crtc)) {
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spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
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@ -9668,12 +9667,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
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}
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#endif
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}
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if (configure_crc)
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if (amdgpu_dm_crtc_configure_crc_source(
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crtc, dm_new_crtc_state, cur_crc_src))
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DRM_DEBUG_DRIVER("Failed to configure crc source");
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}
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#endif
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}
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}
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