PCI: designware: Fold struct pcie_port_info into struct pcie_port
The struct pcie_port_info doesn't contain any exclusive information compared to other elements of struct pcie_port. So, keeping a separate structure does not seem very logical. Therefore remove this struct and embed its elements directly into struct pcie_port. Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit Kumar <mohit.kumar@st.com>
This commit is contained in:
Pratyush Anand
Bjorn Helgaas
Родитель
84a263f394
Коммит
adf70fc087
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@ -423,16 +423,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
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cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
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if (cfg_res) {
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pp->config.cfg0_size = resource_size(cfg_res)/2;
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pp->config.cfg1_size = resource_size(cfg_res)/2;
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pp->cfg0_size = resource_size(cfg_res)/2;
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pp->cfg1_size = resource_size(cfg_res)/2;
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pp->cfg0_base = cfg_res->start;
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pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
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pp->cfg1_base = cfg_res->start + pp->cfg0_size;
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/* Find the untranslated configuration space address */
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index = of_property_match_string(np, "reg-names", "config");
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addrp = of_get_address(np, index, false, false);
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pp->cfg0_mod_base = of_read_number(addrp, ns);
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pp->cfg1_mod_base = pp->cfg0_mod_base + pp->config.cfg0_size;
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pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
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} else {
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dev_err(pp->dev, "missing *config* reg space\n");
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}
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@ -455,8 +455,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
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IO_SPACE_LIMIT,
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range.pci_addr + range.size
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+ global_io_offset);
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pp->config.io_size = resource_size(&pp->io);
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pp->config.io_bus_addr = range.pci_addr;
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pp->io_size = resource_size(&pp->io);
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pp->io_bus_addr = range.pci_addr;
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pp->io_base = range.cpu_addr;
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/* Find the untranslated IO space address */
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@ -466,8 +466,8 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
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if (restype == IORESOURCE_MEM) {
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of_pci_range_to_resource(&range, np, &pp->mem);
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pp->mem.name = "MEM";
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pp->config.mem_size = resource_size(&pp->mem);
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pp->config.mem_bus_addr = range.pci_addr;
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pp->mem_size = resource_size(&pp->mem);
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pp->mem_bus_addr = range.pci_addr;
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/* Find the untranslated MEM space address */
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pp->mem_mod_base = of_read_number(parser.range -
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@ -475,16 +475,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
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}
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if (restype == 0) {
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of_pci_range_to_resource(&range, np, &pp->cfg);
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pp->config.cfg0_size = resource_size(&pp->cfg)/2;
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pp->config.cfg1_size = resource_size(&pp->cfg)/2;
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pp->cfg0_size = resource_size(&pp->cfg)/2;
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pp->cfg1_size = resource_size(&pp->cfg)/2;
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pp->cfg0_base = pp->cfg.start;
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pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
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pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
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/* Find the untranslated configuration space address */
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pp->cfg0_mod_base = of_read_number(parser.range -
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parser.np + na, ns);
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pp->cfg1_mod_base = pp->cfg0_mod_base +
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pp->config.cfg0_size;
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pp->cfg0_size;
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}
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}
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@ -512,7 +512,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
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if (!pp->va_cfg0_base) {
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pp->cfg0_base = pp->cfg.start;
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pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
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pp->config.cfg0_size);
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pp->cfg0_size);
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if (!pp->va_cfg0_base) {
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dev_err(pp->dev, "error with ioremap in function\n");
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return -ENOMEM;
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@ -520,9 +520,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
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}
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if (!pp->va_cfg1_base) {
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pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
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pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
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pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
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pp->config.cfg1_size);
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pp->cfg1_size);
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if (!pp->va_cfg1_base) {
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dev_err(pp->dev, "error with ioremap\n");
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return -ENOMEM;
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@ -583,7 +583,7 @@ static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
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PCIE_ATU_VIEWPORT);
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dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
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dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
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dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->config.cfg0_size - 1,
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dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1,
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
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@ -599,7 +599,7 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
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dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
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dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
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dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->config.cfg1_size - 1,
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dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1,
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
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@ -614,10 +614,10 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
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dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
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dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
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dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->config.mem_size - 1,
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dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1,
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
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dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr),
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PCIE_ATU_UPPER_TARGET);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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}
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@ -630,10 +630,10 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
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dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
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dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
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dw_pcie_writel_rc(pp, pp->io_mod_base + pp->config.io_size - 1,
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dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1,
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
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dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr),
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PCIE_ATU_UPPER_TARGET);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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}
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@ -768,15 +768,15 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
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pp = sys_to_pcie(sys);
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if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
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sys->io_offset = global_io_offset - pp->config.io_bus_addr;
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if (global_io_offset < SZ_1M && pp->io_size > 0) {
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sys->io_offset = global_io_offset - pp->io_bus_addr;
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pci_ioremap_io(global_io_offset, pp->io_base);
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global_io_offset += SZ_64K;
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pci_add_resource_offset(&sys->resources, &pp->io,
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sys->io_offset);
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}
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sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
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sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
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pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
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pci_add_resource(&sys->resources, &pp->busn);
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@ -833,7 +833,6 @@ static struct hw_pci dw_pci = {
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void dw_pcie_setup_rc(struct pcie_port *pp)
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{
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struct pcie_port_info *config = &pp->config;
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u32 val;
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u32 membase;
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u32 memlimit;
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@ -888,7 +887,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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/* setup memory base, memory limit */
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membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
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memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
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memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
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val = memlimit | membase;
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dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
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@ -14,15 +14,6 @@
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#ifndef _PCIE_DESIGNWARE_H
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#define _PCIE_DESIGNWARE_H
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struct pcie_port_info {
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u32 cfg0_size;
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u32 cfg1_size;
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u32 io_size;
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u32 mem_size;
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phys_addr_t io_bus_addr;
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phys_addr_t mem_bus_addr;
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};
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/*
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* Maximum number of MSI IRQs can be 256 per controller. But keep
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* it 32 as of now. Probably we will never need more than 32. If needed,
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@ -38,18 +29,23 @@ struct pcie_port {
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u64 cfg0_base;
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u64 cfg0_mod_base;
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void __iomem *va_cfg0_base;
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u32 cfg0_size;
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u64 cfg1_base;
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u64 cfg1_mod_base;
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void __iomem *va_cfg1_base;
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u32 cfg1_size;
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u64 io_base;
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u64 io_mod_base;
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phys_addr_t io_bus_addr;
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u32 io_size;
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u64 mem_base;
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u64 mem_mod_base;
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phys_addr_t mem_bus_addr;
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u32 mem_size;
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struct resource cfg;
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struct resource io;
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struct resource mem;
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struct resource busn;
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struct pcie_port_info config;
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int irq;
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u32 lanes;
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struct pcie_host_ops *ops;
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