Merge branch 'j/pinctrl' of http://github.com/at91linux/linux-at91 into at91
This commit is contained in:
Коммит
ae0407e137
|
@ -9,6 +9,10 @@ Required properties:
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|||
unused).
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
|
||||
optional properties:
|
||||
- #gpio-lines: Number of gpio if absent 32.
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||||
|
||||
|
||||
Example:
|
||||
pioA: gpio@fffff200 {
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||||
compatible = "atmel,at91rm9200-gpio";
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||||
|
@ -16,5 +20,6 @@ Example:
|
|||
interrupts = <2 4>;
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||||
#gpio-cells = <2>;
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||||
gpio-controller;
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#gpio-lines = <19>;
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};
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||||
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|
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@ -0,0 +1,136 @@
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* Atmel AT91 Pinmux Controller
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|
||||
The AT91 Pinmux Controler, enables the IC
|
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to share one PAD to several functional blocks. The sharing is done by
|
||||
multiplexing the PAD input/output signals. For each PAD there are up to
|
||||
8 muxing options (called periph modes). Since different modules require
|
||||
different PAD settings (like pull up, keeper, etc) the contoller controls
|
||||
also the PAD settings parameters.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
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common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
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|
||||
Atmel AT91 pin configuration node is a node of a group of pins which can be
|
||||
used for a specific device or function. This node represents both mux and config
|
||||
of the pins in that group. The 'pins' selects the function mode(also named pin
|
||||
mode) this pin can work on and the 'config' configures various pad settings
|
||||
such as pull-up, multi drive, etc.
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||||
|
||||
Required properties for iomux controller:
|
||||
- compatible: "atmel,at91rm9200-pinctrl"
|
||||
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
|
||||
configured in this periph mode. All the periph and bank need to be describe.
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||||
|
||||
How to create such array:
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||||
|
||||
Each column will represent the possible peripheral of the pinctrl
|
||||
Each line will represent a pio bank
|
||||
|
||||
Take an example on the 9260
|
||||
Peripheral: 2 ( A and B)
|
||||
Bank: 3 (A, B and C)
|
||||
=>
|
||||
|
||||
/* A B */
|
||||
0xffffffff 0xffc00c3b /* pioA */
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||||
0xffffffff 0x7fff3ccf /* pioB */
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||||
0xffffffff 0x007fffff /* pioC */
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|
||||
For each peripheral/bank we will descibe in a u32 if a pin can can be
|
||||
configured in it by putting 1 to the pin bit (1 << pin)
|
||||
|
||||
Let's take the pioA on peripheral B
|
||||
From the datasheet Table 10-2.
|
||||
Peripheral B
|
||||
PA0 MCDB0
|
||||
PA1 MCCDB
|
||||
PA2
|
||||
PA3 MCDB3
|
||||
PA4 MCDB2
|
||||
PA5 MCDB1
|
||||
PA6
|
||||
PA7
|
||||
PA8
|
||||
PA9
|
||||
PA10 ETX2
|
||||
PA11 ETX3
|
||||
PA12
|
||||
PA13
|
||||
PA14
|
||||
PA15
|
||||
PA16
|
||||
PA17
|
||||
PA18
|
||||
PA19
|
||||
PA20
|
||||
PA21
|
||||
PA22 ETXER
|
||||
PA23 ETX2
|
||||
PA24 ETX3
|
||||
PA25 ERX2
|
||||
PA26 ERX3
|
||||
PA27 ERXCK
|
||||
PA28 ECRS
|
||||
PA29 ECOL
|
||||
PA30 RXD4
|
||||
PA31 TXD4
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||||
|
||||
=> 0xffc00c3b
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|
||||
Required properties for pin configuration node:
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- atmel,pins: 4 integers array, represents a group of pins mux and config
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setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
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The PERIPH 0 means gpio.
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|
||||
Bits used for CONFIG:
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||||
PULL_UP(1 << 0): indicate this pin need a pull up.
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MULTIDRIVE(1 << 1): indicate this pin need to be configured as multidrive.
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||||
|
||||
NOTE:
|
||||
Some requirements for using atmel,at91rm9200-pinctrl binding:
|
||||
1. We have pin function node defined under at91 controller node to represent
|
||||
what pinmux functions this SoC supports.
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2. The driver can use the function node's name and pin configuration node's
|
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name describe the pin function and group hierarchy.
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For example, Linux at91 pinctrl driver takes the function node's name
|
||||
as the function name and pin configuration node's name as group name to
|
||||
create the map table.
|
||||
3. Each pin configuration node should have a phandle, devices can set pins
|
||||
configurations by referring to the phandle of that pin configuration node.
|
||||
4. The gpio controller must be describe in the pinctrl simple-bus.
|
||||
|
||||
Examples:
|
||||
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
reg = <0xfffff400 0x600>;
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||||
|
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atmel,mux-mask = <
|
||||
/* A B */
|
||||
0xffffffff 0xffc00c3b /* pioA */
|
||||
0xffffffff 0x7fff3ccf /* pioB */
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||||
0xffffffff 0x007fffff /* pioC */
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||||
>;
|
||||
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
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||||
atmel,pins =
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<1 14 0x1 0x0 /* PB14 periph A */
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||||
1 15 0x1 0x1>; /* PB15 periph with pullup */
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};
|
||||
};
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||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 4 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
status = "disabled";
|
||||
};
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|
@ -330,6 +330,8 @@ config ARCH_AT91
|
|||
select IRQ_DOMAIN
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||||
select NEED_MACH_GPIO_H
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select NEED_MACH_IO_H if PCCARD
|
||||
select PINCTRL
|
||||
select PINCTRL_AT91 if USE_OF
|
||||
help
|
||||
This enables support for systems based on Atmel
|
||||
AT91RM9200 and AT91SAM9* processors.
|
||||
|
|
|
@ -1,21 +1,33 @@
|
|||
ifeq ($(CONFIG_OF),y)
|
||||
|
||||
dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
|
||||
at91sam9263ek.dtb \
|
||||
at91sam9g20ek_2mmc.dtb \
|
||||
at91sam9g20ek.dtb \
|
||||
at91sam9g25ek.dtb \
|
||||
at91sam9m10g45ek.dtb \
|
||||
at91sam9n12ek.dtb \
|
||||
ethernut5.dtb \
|
||||
evk-pro3.dtb \
|
||||
kizbox.dtb \
|
||||
tny_a9260.dtb \
|
||||
tny_a9263.dtb \
|
||||
tny_a9g20.dtb \
|
||||
usb_a9260.dtb \
|
||||
usb_a9263.dtb \
|
||||
usb_a9g20.dtb
|
||||
# Keep at91 dtb files sorted alphabetically for each SoC
|
||||
# sam9260
|
||||
dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += tny_a9260.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += usb_a9260.dtb
|
||||
# sam9263
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
|
||||
# sam9g20
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
|
||||
# sam9g45
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
|
||||
# sam9n12
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
|
||||
# sam9x5
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
|
||||
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
|
||||
dove-cubox.dtb \
|
||||
|
|
|
@ -98,40 +98,161 @@
|
|||
interrupts = <26 4 0 27 4 0 28 4 0>;
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x100>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff400 0xfffff400 0x600>;
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x100>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
atmel,mux-mask = <
|
||||
/* A B */
|
||||
0xffffffff 0xffc00c3b /* pioA */
|
||||
0xffffffff 0x7fff3ccf /* pioB */
|
||||
0xffffffff 0x007fffff /* pioC */
|
||||
>;
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x100>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<1 14 0x1 0x0 /* PB14 periph A */
|
||||
1 15 0x1 0x1>; /* PB15 periph with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
pinctrl_uart0: uart0-0 {
|
||||
atmel,pins =
|
||||
<1 4 0x1 0x0 /* PB4 periph A */
|
||||
1 5 0x1 0x0>; /* PB5 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<1 26 0x1 0x0 /* PB26 periph A */
|
||||
1 27 0x1 0x0>; /* PB27 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart0_dtr_dsr: uart0_dtr_dsr-0 {
|
||||
atmel,pins =
|
||||
<1 24 0x1 0x0 /* PB24 periph A */
|
||||
1 22 0x1 0x0>; /* PB22 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart0_dcd: uart0_dcd-0 {
|
||||
atmel,pins =
|
||||
<1 23 0x1 0x0>; /* PB23 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart0_ri: uart0_ri-0 {
|
||||
atmel,pins =
|
||||
<1 25 0x1 0x0>; /* PB25 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1: uart1-0 {
|
||||
atmel,pins =
|
||||
<2 6 0x1 0x1 /* PB6 periph A with pullup */
|
||||
2 7 0x1 0x0>; /* PB7 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<1 28 0x1 0x0 /* PB28 periph A */
|
||||
1 29 0x1 0x0>; /* PB29 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2: uart2-0 {
|
||||
atmel,pins =
|
||||
<1 8 0x1 0x1 /* PB8 periph A with pullup */
|
||||
1 9 0x1 0x0>; /* PB9 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<0 4 0x1 0x0 /* PA4 periph A */
|
||||
0 5 0x1 0x0>; /* PA5 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3: uart3-0 {
|
||||
atmel,pins =
|
||||
<2 10 0x1 0x1 /* PB10 periph A with pullup */
|
||||
2 11 0x1 0x0>; /* PB11 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<3 8 0x2 0x0 /* PB8 periph B */
|
||||
3 10 0x2 0x0>; /* PB10 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
uart4 {
|
||||
pinctrl_uart4: uart4-0 {
|
||||
atmel,pins =
|
||||
<0 31 0x2 0x1 /* PA31 periph B with pullup */
|
||||
0 30 0x2 0x0>; /* PA30 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
uart5 {
|
||||
pinctrl_uart5: uart5-0 {
|
||||
atmel,pins =
|
||||
<2 12 0x1 0x1 /* PB12 periph A with pullup */
|
||||
2 13 0x1 0x0>; /* PB13 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
|
||||
2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 4 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -141,6 +262,8 @@
|
|||
interrupts = <6 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -150,6 +273,8 @@
|
|||
interrupts = <7 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -159,6 +284,8 @@
|
|||
interrupts = <8 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -168,6 +295,8 @@
|
|||
interrupts = <23 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -177,6 +306,8 @@
|
|||
interrupts = <24 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -186,6 +317,8 @@
|
|||
interrupts = <25 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -257,6 +390,8 @@
|
|||
>;
|
||||
atmel,nand-addr-offset = <21>;
|
||||
atmel,nand-cmd-offset = <22>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
gpios = <&pioC 13 0
|
||||
&pioC 14 0
|
||||
0
|
||||
|
|
|
@ -89,60 +89,137 @@
|
|||
reg = <0xfffffd10 0x10>;
|
||||
};
|
||||
|
||||
pioA: gpio@fffff200 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff200 0x100>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
pinctrl@fffff200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff200 0xfffff200 0xa00>;
|
||||
|
||||
pioB: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x100>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
atmel,mux-mask = <
|
||||
/* A B */
|
||||
0xfffffffb 0xffffe07f /* pioA */
|
||||
0x0007ffff 0x39072fff /* pioB */
|
||||
0xffffffff 0x3ffffff8 /* pioC */
|
||||
0xfffffbff 0xffffffff /* pioD */
|
||||
0xffe00fff 0xfbfcff00 /* pioE */
|
||||
>;
|
||||
|
||||
pioC: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x100>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<2 30 0x1 0x0 /* PC30 periph A */
|
||||
2 31 0x1 0x1>; /* PC31 periph with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
pioD: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x100>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
uart0 {
|
||||
pinctrl_uart0: uart0-0 {
|
||||
atmel,pins =
|
||||
<0 26 0x1 0x1 /* PA26 periph A with pullup */
|
||||
0 27 0x1 0x0>; /* PA27 periph A */
|
||||
};
|
||||
|
||||
pioE: gpio@fffffa00 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x100>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<0 28 0x1 0x0 /* PA28 periph A */
|
||||
0 29 0x1 0x0>; /* PA29 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1: uart1-0 {
|
||||
atmel,pins =
|
||||
<3 0 0x1 0x1 /* PD0 periph A with pullup */
|
||||
3 1 0x1 0x0>; /* PD1 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<3 7 0x2 0x0 /* PD7 periph B */
|
||||
3 8 0x2 0x0>; /* PD8 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2: uart2-0 {
|
||||
atmel,pins =
|
||||
<3 2 0x1 0x1 /* PD2 periph A with pullup */
|
||||
3 3 0x1 0x0>; /* PD3 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<3 5 0x2 0x0 /* PD5 periph B */
|
||||
4 6 0x2 0x0>; /* PD6 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
|
||||
3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff200 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioD: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioE: gpio@fffffa00 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x200>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xffffee00 0x200>;
|
||||
interrupts = <1 4 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -152,6 +229,8 @@
|
|||
interrupts = <7 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -161,6 +240,8 @@
|
|||
interrupts = <8 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -170,6 +251,8 @@
|
|||
interrupts = <9 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -206,6 +289,8 @@
|
|||
>;
|
||||
atmel,nand-addr-offset = <21>;
|
||||
atmel,nand-cmd-offset = <22>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
gpios = <&pioA 22 0
|
||||
&pioD 15 0
|
||||
0
|
||||
|
|
|
@ -38,6 +38,7 @@
|
|||
};
|
||||
|
||||
usart0: serial@fff8c000 {
|
||||
pinctrl-0 = <&pinctrl_uart0 &pinctrl_uart0_rts_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
/include/ "at91sam9x5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G15 SoC";
|
||||
compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe0399f 0x00000000 /* pioA */
|
||||
0x00040000 0x00047e3f 0x00000000 /* pioB */
|
||||
0xfdffffff 0x00000000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "at91sam9g15.dtsi"
|
||||
/include/ "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G25-EK";
|
||||
compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
};
|
|
@ -35,6 +35,12 @@
|
|||
};
|
||||
|
||||
usart0: serial@fffb0000 {
|
||||
pinctrl-0 =
|
||||
<&pinctrl_uart0
|
||||
&pinctrl_uart0_rts_cts
|
||||
&pinctrl_uart0_dtr_dsr
|
||||
&pinctrl_uart0_dcd
|
||||
&pinctrl_uart0_ri>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
/include/ "at91sam9x5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G25 SoC";
|
||||
compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe0399f 0xc000001c /* pioA */
|
||||
0x0007ffff 0x8000fe3f 0x00000000 /* pioB */
|
||||
0x80000000 0x07c0ffff 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -7,55 +7,10 @@
|
|||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "at91sam9x5.dtsi"
|
||||
/include/ "at91sam9x5cm.dtsi"
|
||||
/include/ "at91sam9g25.dtsi"
|
||||
/include/ "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G25-EK";
|
||||
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@f801c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f8010000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@f8014000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c2: i2c@f8018000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00600000 {
|
||||
status = "okay";
|
||||
num-ports = <2>;
|
||||
atmel,vbus-gpio = <&pioD 19 1
|
||||
&pioD 20 1
|
||||
>;
|
||||
};
|
||||
|
||||
usb1: ehci@00700000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
/include/ "at91sam9x5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G35 SoC";
|
||||
compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe0399f 0xc000000c /* pioA */
|
||||
0x000406ff 0x00047e3f 0x00000000 /* pioB */
|
||||
0xfdffffff 0x00000000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "at91sam9g35.dtsi"
|
||||
/include/ "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G35-EK";
|
||||
compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
};
|
|
@ -108,60 +108,151 @@
|
|||
interrupts = <21 4 0>;
|
||||
};
|
||||
|
||||
pioA: gpio@fffff200 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff200 0x100>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
pinctrl@fffff200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff200 0xfffff200 0xa00>;
|
||||
|
||||
pioB: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x100>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
atmel,mux-mask = <
|
||||
/* A B */
|
||||
0xffffffff 0xffc003ff /* pioA */
|
||||
0xffffffff 0x800f8f00 /* pioB */
|
||||
0xffffffff 0x00000e00 /* pioC */
|
||||
0xffffffff 0xff0c1381 /* pioD */
|
||||
0xffffffff 0x81ffff81 /* pioE */
|
||||
>;
|
||||
|
||||
pioC: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x100>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<1 12 0x1 0x0 /* PB12 periph A */
|
||||
1 13 0x1 0x0>; /* PB13 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
pioD: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x100>;
|
||||
interrupts = <5 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
uart0 {
|
||||
pinctrl_uart0: uart0-0 {
|
||||
atmel,pins =
|
||||
<1 19 0x1 0x1 /* PB19 periph A with pullup */
|
||||
1 18 0x1 0x0>; /* PB18 periph A */
|
||||
};
|
||||
|
||||
pioE: gpio@fffffa00 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x100>;
|
||||
interrupts = <5 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<1 17 0x2 0x0 /* PB17 periph B */
|
||||
1 15 0x2 0x0>; /* PB15 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1: uart1-0 {
|
||||
atmel,pins =
|
||||
<1 4 0x1 0x1 /* PB4 periph A with pullup */
|
||||
1 5 0x1 0x0>; /* PB5 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<3 16 0x1 0x0 /* PD16 periph A */
|
||||
3 17 0x1 0x0>; /* PD17 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2: uart2-0 {
|
||||
atmel,pins =
|
||||
<1 6 0x1 0x1 /* PB6 periph A with pullup */
|
||||
1 7 0x1 0x0>; /* PB7 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<2 9 0x2 0x0 /* PC9 periph B */
|
||||
2 11 0x2 0x0>; /* PC11 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3: uart3-0 {
|
||||
atmel,pins =
|
||||
<1 8 0x1 0x1 /* PB9 periph A with pullup */
|
||||
1 9 0x1 0x0>; /* PB8 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<0 23 0x2 0x0 /* PA23 periph B */
|
||||
0 24 0x2 0x0>; /* PA24 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
|
||||
2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff200 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff400 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff600 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <4 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioD: gpio@fffff800 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <5 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioE: gpio@fffffa00 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x200>;
|
||||
interrupts = <5 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xffffee00 0x200>;
|
||||
interrupts = <1 4 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -171,6 +262,8 @@
|
|||
interrupts = <7 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -180,6 +273,8 @@
|
|||
interrupts = <8 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -189,6 +284,8 @@
|
|||
interrupts = <9 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -198,6 +295,8 @@
|
|||
interrupts = <10 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -273,6 +372,8 @@
|
|||
>;
|
||||
atmel,nand-addr-offset = <21>;
|
||||
atmel,nand-cmd-offset = <22>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
gpios = <&pioC 8 0
|
||||
&pioC 14 0
|
||||
0
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
};
|
||||
|
||||
usart1: serial@fff90000 {
|
||||
pinctrl-0 = <&pinctrl_uart0 &pinctrl_uart1_rts_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -102,50 +102,150 @@
|
|||
interrupts = <20 4 0>;
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x100>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x100>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe07983 0x00000000 /* pioA */
|
||||
0x00040000 0x00047e0f 0x00000000 /* pioB */
|
||||
0xfdffffff 0x07c00000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x100>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<0 9 0x1 0x0 /* PA9 periph A */
|
||||
0 10 0x1 0x1>; /* PA10 periph with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
pioD: gpio@fffffa00 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x100>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
uart0 {
|
||||
pinctrl_uart0: uart0-0 {
|
||||
atmel,pins =
|
||||
<0 1 0x1 0x1 /* PA1 periph A with pullup */
|
||||
0 0 0x1 0x0>; /* PA0 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<0 2 0x1 0x0 /* PA2 periph A */
|
||||
0 3 0x1 0x0>; /* PA3 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1: uart1-0 {
|
||||
atmel,pins =
|
||||
<0 6 0x1 0x1 /* PA6 periph A with pullup */
|
||||
0 5 0x1 0x0>; /* PA5 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2: uart2-0 {
|
||||
atmel,pins =
|
||||
<0 8 0x1 0x1 /* PA8 periph A with pullup */
|
||||
0 7 0x1 0x0>; /* PA7 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<1 0 0x2 0x0 /* PB0 periph B */
|
||||
1 1 0x2 0x0>; /* PB1 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3: uart3-0 {
|
||||
atmel,pins =
|
||||
<2 23 0x2 0x1 /* PC23 periph B with pullup */
|
||||
2 22 0x2 0x0>; /* PC22 periph B */
|
||||
};
|
||||
|
||||
pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<2 24 0x2 0x0 /* PC24 periph B */
|
||||
2 25 0x2 0x0>; /* PC25 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<2 9 0x3 0x1 /* PC9 periph C with pullup */
|
||||
2 8 0x3 0x0>; /* PC8 periph C */
|
||||
};
|
||||
};
|
||||
|
||||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<2 16 0x3 0x1 /* PC17 periph C with pullup */
|
||||
2 17 0x3 0x0>; /* PC16 periph C */
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
|
||||
3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioD: gpio@fffffa00 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x200>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 4 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -155,6 +255,8 @@
|
|||
interrupts = <5 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -164,6 +266,8 @@
|
|||
interrupts = <6 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -173,6 +277,8 @@
|
|||
interrupts = <7 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -182,6 +288,8 @@
|
|||
interrupts = <8 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -215,6 +323,8 @@
|
|||
>;
|
||||
atmel,nand-addr-offset = <21>;
|
||||
atmel,nand-cmd-offset = <22>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
gpios = <&pioD 5 0
|
||||
&pioD 4 0
|
||||
0
|
||||
|
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
/include/ "at91sam9x5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X25 SoC";
|
||||
compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe03fff 0xc000001c /* pioA */
|
||||
0x0007ffff 0x00047e3f 0x00000000 /* pioB */
|
||||
0x80000000 0xfffd0000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "at91sam9x25.dtsi"
|
||||
/include/ "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9G25-EK";
|
||||
compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
};
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Licensed under GPLv2.
|
||||
*/
|
||||
|
||||
/include/ "at91sam9x5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X35 SoC";
|
||||
compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
atmel,mux-mask = <
|
||||
/* A B C */
|
||||
0xffffffff 0xffe03fff 0xc000000c /* pioA */
|
||||
0x000406ff 0x00047e3f 0x00000000 /* pioB */
|
||||
0xfdffffff 0x00000000 0xb83fffff /* pioC */
|
||||
0x003fffff 0x003f8000 0x00000000 /* pioD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
/include/ "at91sam9x35.dtsi"
|
||||
/include/ "at91sam9x5ek.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X35-EK";
|
||||
compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
};
|
|
@ -111,50 +111,150 @@
|
|||
interrupts = <21 4 0>;
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x100>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
pinctrl@fffff400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
|
||||
ranges = <0xfffff400 0xfffff400 0x800>;
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x100>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
/* shared pinctrl settings */
|
||||
dbgu {
|
||||
pinctrl_dbgu: dbgu-0 {
|
||||
atmel,pins =
|
||||
<0 9 0x1 0x0 /* PA9 periph A */
|
||||
0 10 0x1 0x1>; /* PA10 periph A with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x100>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
uart0 {
|
||||
pinctrl_uart0: uart0-0 {
|
||||
atmel,pins =
|
||||
<0 0 0x1 0x1 /* PA0 periph A with pullup */
|
||||
0 1 0x1 0x0>; /* PA1 periph A */
|
||||
};
|
||||
|
||||
pioD: gpio@fffffa00 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x100>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<0 2 0x1 0x0 /* PA2 periph A */
|
||||
0 3 0x1 0x0>; /* PA3 periph A */
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1: uart1-0 {
|
||||
atmel,pins =
|
||||
<0 5 0x1 0x1 /* PA5 periph A with pullup */
|
||||
0 6 0x1 0x0>; /* PA6 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<3 27 0x3 0x0 /* PC27 periph C */
|
||||
3 28 0x3 0x0>; /* PC28 periph C */
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2: uart2-0 {
|
||||
atmel,pins =
|
||||
<0 7 0x1 0x1 /* PA7 periph A with pullup */
|
||||
0 8 0x1 0x0>; /* PA8 periph A */
|
||||
};
|
||||
|
||||
pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<0 0 0x2 0x0 /* PB0 periph B */
|
||||
0 1 0x2 0x0>; /* PB1 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3: uart3-0 {
|
||||
atmel,pins =
|
||||
<3 23 0x2 0x1 /* PC22 periph B with pullup */
|
||||
3 23 0x2 0x0>; /* PC23 periph B */
|
||||
};
|
||||
|
||||
pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
|
||||
atmel,pins =
|
||||
<3 24 0x2 0x0 /* PC24 periph B */
|
||||
3 25 0x2 0x0>; /* PC25 periph B */
|
||||
};
|
||||
};
|
||||
|
||||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
<3 8 0x3 0x0 /* PC8 periph C */
|
||||
3 9 0x3 0x1>; /* PC9 periph C with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
usart1 {
|
||||
pinctrl_usart1: usart1-0 {
|
||||
atmel,pins =
|
||||
<3 16 0x3 0x0 /* PC16 periph C */
|
||||
3 17 0x3 0x1>; /* PC17 periph C with pullup */
|
||||
};
|
||||
};
|
||||
|
||||
nand {
|
||||
pinctrl_nand: nand-0 {
|
||||
atmel,pins =
|
||||
<3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
|
||||
3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff400 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff400 0x200>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioB: gpio@fffff600 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff600 0x200>;
|
||||
interrupts = <2 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-lines = <19>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioC: gpio@fffff800 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff800 0x200>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pioD: gpio@fffffa00 {
|
||||
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffffa00 0x200>;
|
||||
interrupts = <3 4 1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-lines = <22>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dbgu: serial@fffff200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0xfffff200 0x200>;
|
||||
interrupts = <1 4 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -164,6 +264,8 @@
|
|||
interrupts = <5 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -173,6 +275,8 @@
|
|||
interrupts = <6 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -182,6 +286,8 @@
|
|||
interrupts = <7 4 5>;
|
||||
atmel,use-dma-rx;
|
||||
atmel,use-dma-tx;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -273,6 +379,8 @@
|
|||
>;
|
||||
atmel,nand-addr-offset = <21>;
|
||||
atmel,nand-cmd-offset = <22>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
gpios = <&pioD 5 0
|
||||
&pioD 4 0
|
||||
0
|
||||
|
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
|
||||
*
|
||||
* Copyright (C) 2012 Atmel,
|
||||
* 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/include/ "at91sam9x5cm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X5-EK";
|
||||
compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@f801c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f8010000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@f8014000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c2: i2c@f8018000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00600000 {
|
||||
status = "okay";
|
||||
num-ports = <2>;
|
||||
atmel,vbus-gpio = <&pioD 19 1
|
||||
&pioD 20 1
|
||||
>;
|
||||
};
|
||||
|
||||
usb1: ehci@00700000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -111,6 +111,7 @@ CONFIG_I2C=y
|
|||
CONFIG_I2C_GPIO=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_ATMEL=y
|
||||
CONFIG_PINCTRL_AT91=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_AT91SAM9X_WATCHDOG=y
|
||||
|
|
|
@ -361,10 +361,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0 /* Advanced Interrupt Controller (IRQ6) */
|
||||
};
|
||||
|
||||
struct at91_init_soc __initdata at91rm9200_soc = {
|
||||
AT91_SOC_START(rm9200)
|
||||
.map_io = at91rm9200_map_io,
|
||||
.default_irq_priority = at91rm9200_default_irq_priority,
|
||||
.ioremap_registers = at91rm9200_ioremap_registers,
|
||||
.register_clocks = at91rm9200_register_clocks,
|
||||
.init = at91rm9200_initialize,
|
||||
};
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -235,6 +235,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_ID("pioA", &pioA_clk),
|
||||
CLKDEV_CON_ID("pioB", &pioB_clk),
|
||||
CLKDEV_CON_ID("pioC", &pioC_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
|
||||
};
|
||||
|
||||
static struct clk_lookup usart_clocks_lookups[] = {
|
||||
|
@ -390,10 +393,10 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller */
|
||||
};
|
||||
|
||||
struct at91_init_soc __initdata at91sam9260_soc = {
|
||||
AT91_SOC_START(sam9260)
|
||||
.map_io = at91sam9260_map_io,
|
||||
.default_irq_priority = at91sam9260_default_irq_priority,
|
||||
.ioremap_registers = at91sam9260_ioremap_registers,
|
||||
.register_clocks = at91sam9260_register_clocks,
|
||||
.init = at91sam9260_initialize,
|
||||
};
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -334,10 +334,10 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller */
|
||||
};
|
||||
|
||||
struct at91_init_soc __initdata at91sam9261_soc = {
|
||||
AT91_SOC_START(sam9261)
|
||||
.map_io = at91sam9261_map_io,
|
||||
.default_irq_priority = at91sam9261_default_irq_priority,
|
||||
.ioremap_registers = at91sam9261_ioremap_registers,
|
||||
.register_clocks = at91sam9261_register_clocks,
|
||||
.init = at91sam9261_initialize,
|
||||
};
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -212,6 +212,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
|
||||
CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
|
||||
};
|
||||
|
||||
static struct clk_lookup usart_clocks_lookups[] = {
|
||||
|
@ -365,10 +370,10 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller (IRQ1) */
|
||||
};
|
||||
|
||||
struct at91_init_soc __initdata at91sam9263_soc = {
|
||||
AT91_SOC_START(sam9263)
|
||||
.map_io = at91sam9263_map_io,
|
||||
.default_irq_priority = at91sam9263_default_irq_priority,
|
||||
.ioremap_registers = at91sam9263_ioremap_registers,
|
||||
.register_clocks = at91sam9263_register_clocks,
|
||||
.init = at91sam9263_initialize,
|
||||
};
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -260,6 +260,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
|
||||
/* fake hclk clock */
|
||||
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
|
||||
|
||||
CLKDEV_CON_ID("pioA", &pioA_clk),
|
||||
CLKDEV_CON_ID("pioB", &pioB_clk),
|
||||
CLKDEV_CON_ID("pioC", &pioC_clk),
|
||||
|
@ -409,10 +415,10 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller (IRQ0) */
|
||||
};
|
||||
|
||||
struct at91_init_soc __initdata at91sam9g45_soc = {
|
||||
AT91_SOC_START(sam9g45)
|
||||
.map_io = at91sam9g45_map_io,
|
||||
.default_irq_priority = at91sam9g45_default_irq_priority,
|
||||
.ioremap_registers = at91sam9g45_ioremap_registers,
|
||||
.register_clocks = at91sam9g45_register_clocks,
|
||||
.init = at91sam9g45_initialize,
|
||||
};
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -171,10 +171,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
|
||||
CLKDEV_CON_ID("pioA", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioB", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioC", &pioCD_clk),
|
||||
CLKDEV_CON_ID("pioD", &pioCD_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
|
||||
/* additional fake clock for macb_hclk */
|
||||
CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
|
||||
CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
|
||||
|
@ -223,13 +223,10 @@ static void __init at91sam9n12_map_io(void)
|
|||
void __init at91sam9n12_initialize(void)
|
||||
{
|
||||
at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
|
||||
|
||||
/* Register GPIO subsystem (using DT) */
|
||||
at91_gpio_init(NULL, 0);
|
||||
}
|
||||
|
||||
struct at91_init_soc __initdata at91sam9n12_soc = {
|
||||
AT91_SOC_START(sam9n12)
|
||||
.map_io = at91sam9n12_map_io,
|
||||
.register_clocks = at91sam9n12_register_clocks,
|
||||
.init = at91sam9n12_initialize,
|
||||
};
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -338,10 +338,10 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
|
|||
0, /* Advanced Interrupt Controller */
|
||||
};
|
||||
|
||||
struct at91_init_soc __initdata at91sam9rl_soc = {
|
||||
AT91_SOC_START(sam9rl)
|
||||
.map_io = at91sam9rl_map_io,
|
||||
.default_irq_priority = at91sam9rl_default_irq_priority,
|
||||
.ioremap_registers = at91sam9rl_ioremap_registers,
|
||||
.register_clocks = at91sam9rl_register_clocks,
|
||||
.init = at91sam9rl_initialize,
|
||||
};
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -234,10 +234,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
|
||||
CLKDEV_CON_ID("pioA", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioB", &pioAB_clk),
|
||||
CLKDEV_CON_ID("pioC", &pioCD_clk),
|
||||
CLKDEV_CON_ID("pioD", &pioCD_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
|
||||
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
|
||||
/* additional fake clock for macb_hclk */
|
||||
CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
|
||||
CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
|
||||
|
@ -313,18 +313,11 @@ static void __init at91sam9x5_map_io(void)
|
|||
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
|
||||
}
|
||||
|
||||
void __init at91sam9x5_initialize(void)
|
||||
{
|
||||
/* Register GPIO subsystem (using DT) */
|
||||
at91_gpio_init(NULL, 0);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Interrupt initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
struct at91_init_soc __initdata at91sam9x5_soc = {
|
||||
AT91_SOC_START(sam9x5)
|
||||
.map_io = at91sam9x5_map_io,
|
||||
.register_clocks = at91sam9x5_register_clocks,
|
||||
.init = at91sam9x5_initialize,
|
||||
};
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -30,8 +30,6 @@
|
|||
static const struct of_device_id irq_of_match[] __initconst = {
|
||||
|
||||
{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
|
||||
{ .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
|
||||
{ .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
|
||||
{ /*sentinel*/ }
|
||||
};
|
||||
|
||||
|
|
|
@ -23,8 +23,6 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_gpio.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
|
@ -33,6 +31,8 @@
|
|||
|
||||
#include "generic.h"
|
||||
|
||||
#define MAX_NB_GPIO_PER_BANK 32
|
||||
|
||||
struct at91_gpio_chip {
|
||||
struct gpio_chip chip;
|
||||
struct at91_gpio_chip *next; /* Bank sharing same clock */
|
||||
|
@ -46,6 +46,7 @@ struct at91_gpio_chip {
|
|||
|
||||
#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
|
||||
|
||||
static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
|
||||
static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
|
||||
static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
|
||||
static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
|
||||
|
@ -55,26 +56,27 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
|
|||
unsigned offset);
|
||||
static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
|
||||
|
||||
#define AT91_GPIO_CHIP(name, nr_gpio) \
|
||||
#define AT91_GPIO_CHIP(name) \
|
||||
{ \
|
||||
.chip = { \
|
||||
.label = name, \
|
||||
.request = at91_gpiolib_request, \
|
||||
.direction_input = at91_gpiolib_direction_input, \
|
||||
.direction_output = at91_gpiolib_direction_output, \
|
||||
.get = at91_gpiolib_get, \
|
||||
.set = at91_gpiolib_set, \
|
||||
.dbg_show = at91_gpiolib_dbg_show, \
|
||||
.to_irq = at91_gpiolib_to_irq, \
|
||||
.ngpio = nr_gpio, \
|
||||
.ngpio = MAX_NB_GPIO_PER_BANK, \
|
||||
}, \
|
||||
}
|
||||
|
||||
static struct at91_gpio_chip gpio_chip[] = {
|
||||
AT91_GPIO_CHIP("pioA", 32),
|
||||
AT91_GPIO_CHIP("pioB", 32),
|
||||
AT91_GPIO_CHIP("pioC", 32),
|
||||
AT91_GPIO_CHIP("pioD", 32),
|
||||
AT91_GPIO_CHIP("pioE", 32),
|
||||
AT91_GPIO_CHIP("pioA"),
|
||||
AT91_GPIO_CHIP("pioB"),
|
||||
AT91_GPIO_CHIP("pioC"),
|
||||
AT91_GPIO_CHIP("pioD"),
|
||||
AT91_GPIO_CHIP("pioE"),
|
||||
};
|
||||
|
||||
static int gpio_banks;
|
||||
|
@ -89,7 +91,7 @@ static unsigned long at91_gpio_caps;
|
|||
|
||||
static inline void __iomem *pin_to_controller(unsigned pin)
|
||||
{
|
||||
pin /= 32;
|
||||
pin /= MAX_NB_GPIO_PER_BANK;
|
||||
if (likely(pin < gpio_banks))
|
||||
return gpio_chip[pin].regbase;
|
||||
|
||||
|
@ -98,7 +100,7 @@ static inline void __iomem *pin_to_controller(unsigned pin)
|
|||
|
||||
static inline unsigned pin_to_mask(unsigned pin)
|
||||
{
|
||||
return 1 << (pin % 32);
|
||||
return 1 << (pin % MAX_NB_GPIO_PER_BANK);
|
||||
}
|
||||
|
||||
|
||||
|
@ -713,80 +715,6 @@ postcore_initcall(at91_gpio_debugfs_init);
|
|||
*/
|
||||
static struct lock_class_key gpio_lock_class;
|
||||
|
||||
#if defined(CONFIG_OF)
|
||||
static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct at91_gpio_chip *at91_gpio = h->host_data;
|
||||
|
||||
irq_set_lockdep_class(virq, &gpio_lock_class);
|
||||
|
||||
/*
|
||||
* Can use the "simple" and not "edge" handler since it's
|
||||
* shorter, and the AIC handles interrupts sanely.
|
||||
*/
|
||||
irq_set_chip_and_handler(virq, &gpio_irqchip,
|
||||
handle_simple_irq);
|
||||
set_irq_flags(virq, IRQF_VALID);
|
||||
irq_set_chip_data(virq, at91_gpio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_domain_ops at91_gpio_ops = {
|
||||
.map = at91_gpio_irq_map,
|
||||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
||||
int __init at91_gpio_of_irq_setup(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct at91_gpio_chip *prev = NULL;
|
||||
int alias_idx = of_alias_get_id(node, "gpio");
|
||||
struct at91_gpio_chip *at91_gpio = &gpio_chip[alias_idx];
|
||||
|
||||
/* Setup proper .irq_set_type function */
|
||||
if (has_pio3())
|
||||
gpio_irqchip.irq_set_type = alt_gpio_irq_type;
|
||||
else
|
||||
gpio_irqchip.irq_set_type = gpio_irq_type;
|
||||
|
||||
/* Disable irqs of this PIO controller */
|
||||
__raw_writel(~0, at91_gpio->regbase + PIO_IDR);
|
||||
|
||||
/* Setup irq domain */
|
||||
at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
|
||||
&at91_gpio_ops, at91_gpio);
|
||||
if (!at91_gpio->domain)
|
||||
panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
|
||||
at91_gpio->pioc_idx);
|
||||
|
||||
/* Setup chained handler */
|
||||
if (at91_gpio->pioc_idx)
|
||||
prev = &gpio_chip[at91_gpio->pioc_idx - 1];
|
||||
|
||||
/* The toplevel handler handles one bank of GPIOs, except
|
||||
* on some SoC it can handles up to three...
|
||||
* We only set up the handler for the first of the list.
|
||||
*/
|
||||
if (prev && prev->next == at91_gpio)
|
||||
return 0;
|
||||
|
||||
at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
|
||||
at91_gpio->pioc_hwirq);
|
||||
irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
|
||||
irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int __init at91_gpio_of_irq_setup(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* irqdomain initialization: pile up irqdomains on top of AIC range
|
||||
*/
|
||||
|
@ -862,6 +790,16 @@ void __init at91_gpio_irq_setup(void)
|
|||
}
|
||||
|
||||
/* gpiolib support */
|
||||
static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
||||
void __iomem *pio = at91_gpio->regbase;
|
||||
unsigned mask = 1 << offset;
|
||||
|
||||
__raw_writel(mask, pio + PIO_PER);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int at91_gpiolib_direction_input(struct gpio_chip *chip,
|
||||
unsigned offset)
|
||||
{
|
||||
|
@ -975,81 +913,11 @@ err:
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_GPIO
|
||||
static void __init of_at91_gpio_init_one(struct device_node *np)
|
||||
{
|
||||
int alias_idx;
|
||||
struct at91_gpio_chip *at91_gpio;
|
||||
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
alias_idx = of_alias_get_id(np, "gpio");
|
||||
if (alias_idx >= MAX_GPIO_BANKS) {
|
||||
pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
|
||||
alias_idx, MAX_GPIO_BANKS);
|
||||
return;
|
||||
}
|
||||
|
||||
at91_gpio = &gpio_chip[alias_idx];
|
||||
at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
|
||||
|
||||
at91_gpio->regbase = of_iomap(np, 0);
|
||||
if (!at91_gpio->regbase) {
|
||||
pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
|
||||
alias_idx);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Get the interrupts property */
|
||||
if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
|
||||
pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
|
||||
alias_idx);
|
||||
goto ioremap_err;
|
||||
}
|
||||
|
||||
/* Get capabilities from compatibility property */
|
||||
if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
|
||||
at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
|
||||
|
||||
/* Setup clock */
|
||||
if (at91_gpio_setup_clk(alias_idx))
|
||||
goto ioremap_err;
|
||||
|
||||
at91_gpio->chip.of_node = np;
|
||||
gpio_banks = max(gpio_banks, alias_idx + 1);
|
||||
at91_gpio->pioc_idx = alias_idx;
|
||||
return;
|
||||
|
||||
ioremap_err:
|
||||
iounmap(at91_gpio->regbase);
|
||||
}
|
||||
|
||||
static int __init of_at91_gpio_init(void)
|
||||
{
|
||||
struct device_node *np = NULL;
|
||||
|
||||
/*
|
||||
* This isn't ideal, but it gets things hooked up until this
|
||||
* driver is converted into a platform_device
|
||||
*/
|
||||
for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
|
||||
of_at91_gpio_init_one(np);
|
||||
|
||||
return gpio_banks > 0 ? 0 : -EINVAL;
|
||||
}
|
||||
#else
|
||||
static int __init of_at91_gpio_init(void)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
|
||||
{
|
||||
struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
|
||||
|
||||
at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
|
||||
at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
|
||||
at91_gpio->pioc_hwirq = pioc_hwirq;
|
||||
at91_gpio->pioc_idx = idx;
|
||||
|
||||
|
@ -1079,11 +947,11 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
|
|||
|
||||
BUG_ON(nr_banks > MAX_GPIO_BANKS);
|
||||
|
||||
if (of_at91_gpio_init() < 0) {
|
||||
/* No GPIO controller found in device tree */
|
||||
for (i = 0; i < nr_banks; i++)
|
||||
at91_gpio_init_one(i, data[i].regbase, data[i].id);
|
||||
}
|
||||
if (of_have_populated_dt())
|
||||
return;
|
||||
|
||||
for (i = 0; i < nr_banks; i++)
|
||||
at91_gpio_init_one(i, data[i].regbase, data[i].id);
|
||||
|
||||
for (i = 0; i < gpio_banks; i++) {
|
||||
at91_gpio = &gpio_chip[i];
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -448,7 +449,8 @@ void __init at91_dt_initialize(void)
|
|||
/* Register the processor-specific clocks */
|
||||
at91_boot_soc.register_clocks();
|
||||
|
||||
at91_boot_soc.init();
|
||||
if (at91_boot_soc.init)
|
||||
at91_boot_soc.init();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -463,4 +465,6 @@ void __init at91_initialize(unsigned long main_clock)
|
|||
at91_boot_soc.register_clocks();
|
||||
|
||||
at91_boot_soc.init();
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
|
|
@ -5,6 +5,7 @@
|
|||
*/
|
||||
|
||||
struct at91_init_soc {
|
||||
int builtin;
|
||||
unsigned int *default_irq_priority;
|
||||
void (*map_io)(void);
|
||||
void (*ioremap_registers)(void);
|
||||
|
@ -22,9 +23,18 @@ extern struct at91_init_soc at91sam9rl_soc;
|
|||
extern struct at91_init_soc at91sam9x5_soc;
|
||||
extern struct at91_init_soc at91sam9n12_soc;
|
||||
|
||||
#define AT91_SOC_START(_name) \
|
||||
struct at91_init_soc __initdata at91##_name##_soc \
|
||||
__used \
|
||||
= { \
|
||||
.builtin = 1, \
|
||||
|
||||
#define AT91_SOC_END \
|
||||
};
|
||||
|
||||
static inline int at91_soc_is_enabled(void)
|
||||
{
|
||||
return at91_boot_soc.init != NULL;
|
||||
return at91_boot_soc.builtin;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SOC_AT91RM9200)
|
||||
|
|
|
@ -41,6 +41,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/atmel.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <mach/cpu.h>
|
||||
|
||||
|
@ -1370,6 +1371,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
|
|||
struct resource *mem;
|
||||
struct mtd_part_parser_data ppdata = {};
|
||||
int res;
|
||||
struct pinctrl *pinctrl;
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
|
@ -1414,6 +1416,13 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
|
|||
nand_chip->IO_ADDR_W = host->io_base;
|
||||
nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
dev_err(host->dev, "Failed to request pinctrl\n");
|
||||
res = PTR_ERR(pinctrl);
|
||||
goto err_ecc_ioremap;
|
||||
}
|
||||
|
||||
if (gpio_is_valid(host->board.rdy_pin)) {
|
||||
res = gpio_request(host->board.rdy_pin, "nand_rdy");
|
||||
if (res < 0) {
|
||||
|
|
|
@ -26,6 +26,15 @@ config DEBUG_PINCTRL
|
|||
help
|
||||
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
|
||||
|
||||
config PINCTRL_AT91
|
||||
bool "AT91 pinctrl driver"
|
||||
depends on OF
|
||||
depends on ARCH_AT91
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
help
|
||||
Say Y here to enable the at91 pinctrl driver
|
||||
|
||||
config PINCTRL_BCM2835
|
||||
bool
|
||||
select PINMUX
|
||||
|
|
|
@ -9,6 +9,7 @@ ifeq ($(CONFIG_OF),y)
|
|||
obj-$(CONFIG_PINCTRL) += devicetree.o
|
||||
endif
|
||||
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
|
||||
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
|
||||
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
|
||||
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
|
||||
|
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -39,6 +39,7 @@
|
|||
#include <linux/atmel_pdc.h>
|
||||
#include <linux/atmel_serial.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/ioctls.h>
|
||||
|
@ -1773,6 +1774,7 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev)
|
|||
struct atmel_uart_data *pdata = pdev->dev.platform_data;
|
||||
void *data;
|
||||
int ret = -ENODEV;
|
||||
struct pinctrl *pinctrl;
|
||||
|
||||
BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
|
||||
|
||||
|
@ -1805,6 +1807,12 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev)
|
|||
|
||||
atmel_init_port(port, pdev);
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
ret = PTR_ERR(pinctrl);
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (!atmel_use_dma_rx(&port->uart)) {
|
||||
ret = -ENOMEM;
|
||||
data = kmalloc(sizeof(struct atmel_uart_char)
|
||||
|
|
Загрузка…
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