kvm: nVMX: support EPT accessed/dirty bits
Now use bit 6 of EPTP to optionally enable A/D bits for EPTP. Another thing to change is that, when EPT accessed and dirty bits are not in use, VMX treats accesses to guest paging structures as data reads. When they are in use (bit 6 of EPTP is set), they are treated as writes and the corresponding EPT dirty bit is set. The MMU didn't know this detail, so this patch adds it. We also have to fix up the exit qualification. It may be wrong because KVM sets bit 6 but the guest might not. L1 emulates EPT A/D bits using write permissions, so in principle it may be possible for EPT A/D bits to be used by L1 even though not available in hardware. The problem is that guest page-table walks will be treated as reads rather than writes, so they would not cause an EPT violation. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [Fixed typo in walk_addr_generic() comment and changed bit clear + conditional-set pattern in handle_ept_violation() to conditional-clear] Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
This commit is contained in:
Paolo Bonzini
Radim Krčmář
Родитель
86407bcb5c
Коммит
ae1e2d1082
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@ -343,9 +343,10 @@ struct kvm_mmu {
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void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
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u64 *spte, const void *pte);
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hpa_t root_hpa;
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int root_level;
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int shadow_root_level;
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union kvm_mmu_page_role base_role;
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u8 root_level;
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u8 shadow_root_level;
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u8 ept_ad;
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bool direct_map;
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/*
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@ -516,12 +516,14 @@ struct vmx_msr_entry {
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#define EPT_VIOLATION_READABLE_BIT 3
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#define EPT_VIOLATION_WRITABLE_BIT 4
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#define EPT_VIOLATION_EXECUTABLE_BIT 5
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#define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
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#define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT)
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#define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT)
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#define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT)
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#define EPT_VIOLATION_READABLE (1 << EPT_VIOLATION_READABLE_BIT)
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#define EPT_VIOLATION_WRITABLE (1 << EPT_VIOLATION_WRITABLE_BIT)
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#define EPT_VIOLATION_EXECUTABLE (1 << EPT_VIOLATION_EXECUTABLE_BIT)
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#define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
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/*
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* VM-instruction error numbers
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@ -4340,7 +4340,8 @@ void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
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}
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EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
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void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
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void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
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bool accessed_dirty)
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{
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struct kvm_mmu *context = &vcpu->arch.mmu;
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@ -4349,6 +4350,7 @@ void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
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context->shadow_root_level = kvm_x86_ops->get_tdp_level();
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context->nx = true;
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context->ept_ad = accessed_dirty;
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context->page_fault = ept_page_fault;
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context->gva_to_gpa = ept_gva_to_gpa;
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context->sync_page = ept_sync_page;
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@ -74,7 +74,8 @@ enum {
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int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct);
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void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu);
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void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly);
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void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
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bool accessed_dirty);
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static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
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{
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@ -23,13 +23,6 @@
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* so the code in this file is compiled twice, once per pte size.
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*/
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/*
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* This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro
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* uses for EPT without A/D paging type.
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*/
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extern u64 __pure __using_nonexistent_pte_bit(void)
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__compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT");
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#if PTTYPE == 64
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#define pt_element_t u64
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#define guest_walker guest_walker64
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@ -39,8 +32,6 @@ extern u64 __pure __using_nonexistent_pte_bit(void)
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#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
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#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
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#define PT_LEVEL_BITS PT64_LEVEL_BITS
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#define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
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#define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
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#define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
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#define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
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#define PT_HAVE_ACCESSED_DIRTY(mmu) true
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@ -61,8 +52,6 @@ extern u64 __pure __using_nonexistent_pte_bit(void)
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#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
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#define PT_LEVEL_BITS PT32_LEVEL_BITS
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#define PT_MAX_FULL_LEVELS 2
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#define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
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#define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
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#define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
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#define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
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#define PT_HAVE_ACCESSED_DIRTY(mmu) true
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@ -76,17 +65,18 @@ extern u64 __pure __using_nonexistent_pte_bit(void)
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#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
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#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
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#define PT_LEVEL_BITS PT64_LEVEL_BITS
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#define PT_GUEST_ACCESSED_MASK 0
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#define PT_GUEST_DIRTY_MASK 0
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#define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit()
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#define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit()
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#define PT_HAVE_ACCESSED_DIRTY(mmu) false
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#define PT_GUEST_DIRTY_SHIFT 9
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#define PT_GUEST_ACCESSED_SHIFT 8
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#define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
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#define CMPXCHG cmpxchg64
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#define PT_MAX_FULL_LEVELS 4
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#else
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#error Invalid PTTYPE value
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#endif
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#define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
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#define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
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#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
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#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
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@ -290,6 +280,7 @@ static int FNAME(walk_addr_generic)(struct guest_walker *walker,
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pt_element_t __user *uninitialized_var(ptep_user);
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gfn_t table_gfn;
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unsigned index, pt_access, pte_access, accessed_dirty, pte_pkey;
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unsigned nested_access;
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gpa_t pte_gpa;
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bool have_ad;
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int offset;
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@ -319,6 +310,14 @@ retry_walk:
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ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
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accessed_dirty = have_ad ? PT_GUEST_ACCESSED_MASK : 0;
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/*
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* FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
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* by the MOV to CR instruction are treated as reads and do not cause the
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* processor to set the dirty flag in any EPT paging-structure entry.
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*/
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nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
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pt_access = pte_access = ACC_ALL;
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++walker->level;
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@ -338,7 +337,7 @@ retry_walk:
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walker->pte_gpa[walker->level - 1] = pte_gpa;
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real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
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PFERR_USER_MASK|PFERR_WRITE_MASK,
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nested_access,
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&walker->fault);
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/*
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@ -2767,6 +2767,8 @@ static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
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vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
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VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
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VMX_EPT_1GB_PAGE_BIT;
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if (enable_ept_ad_bits)
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vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
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} else
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vmx->nested.nested_vmx_ept_caps = 0;
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@ -6211,6 +6213,17 @@ static int handle_ept_violation(struct kvm_vcpu *vcpu)
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exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
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if (is_guest_mode(vcpu)
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&& !(exit_qualification & EPT_VIOLATION_GVA_TRANSLATED)) {
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/*
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* Fix up exit_qualification according to whether guest
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* page table accesses are reads or writes.
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*/
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u64 eptp = nested_ept_get_cr3(vcpu);
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if (eptp & VMX_EPT_AD_ENABLE_BIT)
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exit_qualification &= ~EPT_VIOLATION_ACC_WRITE;
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}
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/*
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* EPT violation happened while executing iret from NMI,
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* "blocked by NMI" bit has to be set before next VM entry.
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@ -9416,17 +9429,26 @@ static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
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return get_vmcs12(vcpu)->ept_pointer;
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}
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static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
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static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
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{
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u64 eptp;
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WARN_ON(mmu_is_nested(vcpu));
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eptp = nested_ept_get_cr3(vcpu);
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if ((eptp & VMX_EPT_AD_ENABLE_BIT) && !enable_ept_ad_bits)
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return 1;
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kvm_mmu_unload(vcpu);
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kvm_init_shadow_ept_mmu(vcpu,
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to_vmx(vcpu)->nested.nested_vmx_ept_caps &
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VMX_EPT_EXECUTE_ONLY_BIT);
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VMX_EPT_EXECUTE_ONLY_BIT,
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eptp & VMX_EPT_AD_ENABLE_BIT);
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vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
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vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
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vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
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vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
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return 0;
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}
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static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
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@ -10188,8 +10210,10 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
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}
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if (nested_cpu_has_ept(vmcs12)) {
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kvm_mmu_unload(vcpu);
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nested_ept_init_mmu_context(vcpu);
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if (nested_ept_init_mmu_context(vcpu)) {
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*entry_failure_code = ENTRY_FAIL_DEFAULT;
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return 1;
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}
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} else if (nested_cpu_has2(vmcs12,
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SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
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vmx_flush_tlb_ept_only(vcpu);
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