spi: Fixes for v5.6
A selection of small fixes, mostly for drivers, that have arrived since the merge window. None of them are earth shattering in themselves but all useful for affected systems. -----BEGIN PGP SIGNATURE----- iQFHBAABCgAxFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAl5iiroTHGJyb29uaWVA a2VybmVsLm9yZwAKCRAk1otyXVSH0ALxB/0TAEys4X1IxDku7N4E9vivlTQP+Yy5 LmJ7Oc+z1aCWX3LrpMa3M9JInnY44iahjariaZgcQ9GXXTO4rEoOSTVL99fXzj0h wRS23p+h8GNFQ0s6Bzni8HSITz+vzCUJjYQe4i8iJIpQBRIErFSrqzB4uRGd7SPI PIgYeTSA3rFuVvdAgijRg3hPTW2rpn328G/k35JpUNo9OdZ/v6NDQl1Sbg/FedFu iY0feUaQ1FafHGkja/+OYN43bCraDo7Fo4COyF9cHGIJ8nBzMZJumhjgei26nviM OQ15zRewFpnLGlK8ffPykrnynOhqo3GF7JbFWvI5pga/G5XzzLY8mi19 =bFsu -----END PGP SIGNATURE----- Merge tag 'spi-fix-v5.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A selection of small fixes, mostly for drivers, that have arrived since the merge window. None of them are earth shattering in themselves but all useful for affected systems" * tag 'spi-fix-v5.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: spi_register_controller(): free bus id on error paths spi: bcm63xx-hsspi: Really keep pll clk enabled spi: atmel-quadspi: fix possible MMIO window size overrun spi/zynqmp: remove entry that causes a cs glitch spi: pxa2xx: Add CS control clock quirk spi: spidev: Fix CS polarity if GPIO descriptors are used spi: qup: call spi_qup_pm_resume_runtime before suspending spi: spi-omap2-mcspi: Support probe deferral for DMA channels spi: spi-omap2-mcspi: Handle DMA size restriction on AM65x
This commit is contained in:
Linus Torvalds
Коммит
ae24a21bbd
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@ -149,6 +149,7 @@ struct atmel_qspi {
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struct clk *qspick;
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struct platform_device *pdev;
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const struct atmel_qspi_caps *caps;
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resource_size_t mmap_size;
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u32 pending;
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u32 mr;
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u32 scr;
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@ -329,6 +330,14 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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u32 sr, offset;
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int err;
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/*
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* Check if the address exceeds the MMIO window size. An improvement
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* would be to add support for regular SPI mode and fall back to it
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* when the flash memories overrun the controller's memory space.
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*/
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if (op->addr.val + op->data.nbytes > aq->mmap_size)
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return -ENOTSUPP;
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err = atmel_qspi_set_cfg(aq, op, &offset);
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if (err)
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return err;
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@ -480,6 +489,8 @@ static int atmel_qspi_probe(struct platform_device *pdev)
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goto exit;
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}
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aq->mmap_size = resource_size(res);
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/* Get the peripheral clock */
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aq->pclk = devm_clk_get(&pdev->dev, "pclk");
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if (IS_ERR(aq->pclk))
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@ -366,7 +366,6 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
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goto out_disable_clk;
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rate = clk_get_rate(pll_clk);
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clk_disable_unprepare(pll_clk);
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if (!rate) {
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ret = -EINVAL;
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goto out_disable_pll_clk;
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@ -130,6 +130,7 @@ struct omap2_mcspi {
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int fifo_depth;
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bool slave_aborted;
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unsigned int pin_dir:1;
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size_t max_xfer_len;
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};
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struct omap2_mcspi_cs {
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@ -974,20 +975,12 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
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* Note that we currently allow DMA only if we get a channel
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* for both rx and tx. Otherwise we'll do PIO for both rx and tx.
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*/
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static int omap2_mcspi_request_dma(struct spi_device *spi)
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static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
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struct omap2_mcspi_dma *mcspi_dma)
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{
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struct spi_master *master = spi->master;
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struct omap2_mcspi *mcspi;
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struct omap2_mcspi_dma *mcspi_dma;
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int ret = 0;
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mcspi = spi_master_get_devdata(master);
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mcspi_dma = mcspi->dma_channels + spi->chip_select;
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init_completion(&mcspi_dma->dma_rx_completion);
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init_completion(&mcspi_dma->dma_tx_completion);
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mcspi_dma->dma_rx = dma_request_chan(&master->dev,
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mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
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mcspi_dma->dma_rx_ch_name);
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if (IS_ERR(mcspi_dma->dma_rx)) {
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ret = PTR_ERR(mcspi_dma->dma_rx);
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@ -995,7 +988,7 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
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goto no_dma;
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}
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mcspi_dma->dma_tx = dma_request_chan(&master->dev,
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mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
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mcspi_dma->dma_tx_ch_name);
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if (IS_ERR(mcspi_dma->dma_tx)) {
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ret = PTR_ERR(mcspi_dma->dma_tx);
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@ -1004,20 +997,40 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
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mcspi_dma->dma_rx = NULL;
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}
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init_completion(&mcspi_dma->dma_rx_completion);
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init_completion(&mcspi_dma->dma_tx_completion);
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no_dma:
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return ret;
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}
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static void omap2_mcspi_release_dma(struct spi_master *master)
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{
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struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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struct omap2_mcspi_dma *mcspi_dma;
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int i;
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for (i = 0; i < master->num_chipselect; i++) {
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mcspi_dma = &mcspi->dma_channels[i];
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if (mcspi_dma->dma_rx) {
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dma_release_channel(mcspi_dma->dma_rx);
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mcspi_dma->dma_rx = NULL;
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}
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if (mcspi_dma->dma_tx) {
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dma_release_channel(mcspi_dma->dma_tx);
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mcspi_dma->dma_tx = NULL;
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}
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}
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}
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static int omap2_mcspi_setup(struct spi_device *spi)
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{
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int ret;
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struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
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struct omap2_mcspi_regs *ctx = &mcspi->ctx;
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struct omap2_mcspi_dma *mcspi_dma;
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struct omap2_mcspi_cs *cs = spi->controller_state;
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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if (!cs) {
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cs = kzalloc(sizeof *cs, GFP_KERNEL);
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if (!cs)
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@ -1042,13 +1055,6 @@ static int omap2_mcspi_setup(struct spi_device *spi)
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}
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}
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if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
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ret = omap2_mcspi_request_dma(spi);
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if (ret)
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dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
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ret);
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}
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ret = pm_runtime_get_sync(mcspi->dev);
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if (ret < 0) {
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pm_runtime_put_noidle(mcspi->dev);
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@ -1065,12 +1071,8 @@ static int omap2_mcspi_setup(struct spi_device *spi)
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static void omap2_mcspi_cleanup(struct spi_device *spi)
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{
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struct omap2_mcspi *mcspi;
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struct omap2_mcspi_dma *mcspi_dma;
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struct omap2_mcspi_cs *cs;
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mcspi = spi_master_get_devdata(spi->master);
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if (spi->controller_state) {
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/* Unlink controller state from context save list */
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cs = spi->controller_state;
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@ -1079,19 +1081,6 @@ static void omap2_mcspi_cleanup(struct spi_device *spi)
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kfree(cs);
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}
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if (spi->chip_select < spi->master->num_chipselect) {
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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if (mcspi_dma->dma_rx) {
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dma_release_channel(mcspi_dma->dma_rx);
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mcspi_dma->dma_rx = NULL;
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}
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if (mcspi_dma->dma_tx) {
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dma_release_channel(mcspi_dma->dma_tx);
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mcspi_dma->dma_tx = NULL;
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}
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}
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if (gpio_is_valid(spi->cs_gpio))
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gpio_free(spi->cs_gpio);
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}
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@ -1302,9 +1291,24 @@ static bool omap2_mcspi_can_dma(struct spi_master *master,
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if (spi_controller_is_slave(master))
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return true;
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master->dma_rx = mcspi_dma->dma_rx;
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master->dma_tx = mcspi_dma->dma_tx;
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return (xfer->len >= DMA_MIN_BYTES);
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}
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static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
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{
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struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
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struct omap2_mcspi_dma *mcspi_dma =
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&mcspi->dma_channels[spi->chip_select];
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if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
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return mcspi->max_xfer_len;
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return SIZE_MAX;
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}
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static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
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{
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struct spi_master *master = mcspi->master;
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@ -1373,6 +1377,11 @@ static struct omap2_mcspi_platform_config omap4_pdata = {
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.regs_offset = OMAP4_MCSPI_REG_OFFSET,
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};
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static struct omap2_mcspi_platform_config am654_pdata = {
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.regs_offset = OMAP4_MCSPI_REG_OFFSET,
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.max_xfer_len = SZ_4K - 1,
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};
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static const struct of_device_id omap_mcspi_of_match[] = {
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{
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.compatible = "ti,omap2-mcspi",
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@ -1382,6 +1391,10 @@ static const struct of_device_id omap_mcspi_of_match[] = {
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.compatible = "ti,omap4-mcspi",
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.data = &omap4_pdata,
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},
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{
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.compatible = "ti,am654-mcspi",
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.data = &am654_pdata,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
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@ -1439,6 +1452,10 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
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mcspi->pin_dir = pdata->pin_dir;
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}
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regs_offset = pdata->regs_offset;
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if (pdata->max_xfer_len) {
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mcspi->max_xfer_len = pdata->max_xfer_len;
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master->max_transfer_size = omap2_mcspi_max_xfer_size;
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mcspi->base = devm_ioremap_resource(&pdev->dev, r);
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@ -1464,6 +1481,11 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
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for (i = 0; i < master->num_chipselect; i++) {
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sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
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sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
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status = omap2_mcspi_request_dma(mcspi,
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&mcspi->dma_channels[i]);
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if (status == -EPROBE_DEFER)
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goto free_master;
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}
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status = platform_get_irq(pdev, 0);
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@ -1501,6 +1523,7 @@ disable_pm:
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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free_master:
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omap2_mcspi_release_dma(master);
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spi_master_put(master);
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return status;
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}
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@ -1510,6 +1533,8 @@ static int omap2_mcspi_remove(struct platform_device *pdev)
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struct spi_master *master = platform_get_drvdata(pdev);
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struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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omap2_mcspi_release_dma(master);
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pm_runtime_dont_use_autosuspend(mcspi->dev);
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pm_runtime_put_sync(mcspi->dev);
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pm_runtime_disable(&pdev->dev);
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@ -70,6 +70,10 @@ MODULE_ALIAS("platform:pxa2xx-spi");
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#define LPSS_CAPS_CS_EN_SHIFT 9
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#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
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#define LPSS_PRIV_CLOCK_GATE 0x38
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#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
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#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
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struct lpss_config {
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/* LPSS offset from drv_data->ioaddr */
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unsigned offset;
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@ -86,6 +90,8 @@ struct lpss_config {
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unsigned cs_sel_shift;
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unsigned cs_sel_mask;
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unsigned cs_num;
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/* Quirks */
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unsigned cs_clk_stays_gated : 1;
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};
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/* Keep these sorted with enum pxa_ssp_type */
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@ -156,6 +162,7 @@ static const struct lpss_config lpss_platforms[] = {
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.tx_threshold_hi = 56,
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.cs_sel_shift = 8,
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.cs_sel_mask = 3 << 8,
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.cs_clk_stays_gated = true,
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},
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};
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@ -383,6 +390,22 @@ static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
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else
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value |= LPSS_CS_CONTROL_CS_HIGH;
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__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
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if (config->cs_clk_stays_gated) {
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u32 clkgate;
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/*
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* Changing CS alone when dynamic clock gating is on won't
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* actually flip CS at that time. This ruins SPI transfers
|
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* that specify delays, or have no data. Toggle the clock mode
|
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* to force on briefly to poke the CS pin to move.
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*/
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clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
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value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
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LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON;
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__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
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__lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
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}
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}
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static void cs_assert(struct spi_device *spi)
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|
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@ -1217,6 +1217,11 @@ static int spi_qup_suspend(struct device *device)
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struct spi_qup *controller = spi_master_get_devdata(master);
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int ret;
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if (pm_runtime_suspended(device)) {
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ret = spi_qup_pm_resume_runtime(device);
|
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if (ret)
|
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return ret;
|
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}
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ret = spi_master_suspend(master);
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if (ret)
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return ret;
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@ -1225,10 +1230,8 @@ static int spi_qup_suspend(struct device *device)
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if (ret)
|
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return ret;
|
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|
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if (!pm_runtime_suspended(device)) {
|
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clk_disable_unprepare(controller->cclk);
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clk_disable_unprepare(controller->iclk);
|
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}
|
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clk_disable_unprepare(controller->cclk);
|
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clk_disable_unprepare(controller->iclk);
|
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return 0;
|
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}
|
||||
|
||||
|
|
|
|||
|
|
@ -401,9 +401,6 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
|
|||
|
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zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
|
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|
||||
/* Dummy generic FIFO entry */
|
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zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
|
||||
|
||||
/* Manually start the generic FIFO command */
|
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zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
|
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zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
|
||||
|
|
|
|||
|
|
@ -2639,7 +2639,7 @@ int spi_register_controller(struct spi_controller *ctlr)
|
|||
if (ctlr->use_gpio_descriptors) {
|
||||
status = spi_get_gpio_descs(ctlr);
|
||||
if (status)
|
||||
return status;
|
||||
goto free_bus_id;
|
||||
/*
|
||||
* A controller using GPIO descriptors always
|
||||
* supports SPI_CS_HIGH if need be.
|
||||
|
|
@ -2649,7 +2649,7 @@ int spi_register_controller(struct spi_controller *ctlr)
|
|||
/* Legacy code path for GPIOs from DT */
|
||||
status = of_spi_get_gpio_numbers(ctlr);
|
||||
if (status)
|
||||
return status;
|
||||
goto free_bus_id;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2657,17 +2657,14 @@ int spi_register_controller(struct spi_controller *ctlr)
|
|||
* Even if it's just one always-selected device, there must
|
||||
* be at least one chipselect.
|
||||
*/
|
||||
if (!ctlr->num_chipselect)
|
||||
return -EINVAL;
|
||||
if (!ctlr->num_chipselect) {
|
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status = -EINVAL;
|
||||
goto free_bus_id;
|
||||
}
|
||||
|
||||
status = device_add(&ctlr->dev);
|
||||
if (status < 0) {
|
||||
/* free bus id */
|
||||
mutex_lock(&board_lock);
|
||||
idr_remove(&spi_master_idr, ctlr->bus_num);
|
||||
mutex_unlock(&board_lock);
|
||||
goto done;
|
||||
}
|
||||
if (status < 0)
|
||||
goto free_bus_id;
|
||||
dev_dbg(dev, "registered %s %s\n",
|
||||
spi_controller_is_slave(ctlr) ? "slave" : "master",
|
||||
dev_name(&ctlr->dev));
|
||||
|
|
@ -2683,11 +2680,7 @@ int spi_register_controller(struct spi_controller *ctlr)
|
|||
status = spi_controller_initialize_queue(ctlr);
|
||||
if (status) {
|
||||
device_del(&ctlr->dev);
|
||||
/* free bus id */
|
||||
mutex_lock(&board_lock);
|
||||
idr_remove(&spi_master_idr, ctlr->bus_num);
|
||||
mutex_unlock(&board_lock);
|
||||
goto done;
|
||||
goto free_bus_id;
|
||||
}
|
||||
}
|
||||
/* add statistics */
|
||||
|
|
@ -2702,7 +2695,12 @@ int spi_register_controller(struct spi_controller *ctlr)
|
|||
/* Register devices from the device tree and ACPI */
|
||||
of_register_spi_devices(ctlr);
|
||||
acpi_register_spi_devices(ctlr);
|
||||
done:
|
||||
return status;
|
||||
|
||||
free_bus_id:
|
||||
mutex_lock(&board_lock);
|
||||
idr_remove(&spi_master_idr, ctlr->bus_num);
|
||||
mutex_unlock(&board_lock);
|
||||
return status;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(spi_register_controller);
|
||||
|
|
|
|||
|
|
@ -396,6 +396,7 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
|||
else
|
||||
retval = get_user(tmp, (u32 __user *)arg);
|
||||
if (retval == 0) {
|
||||
struct spi_controller *ctlr = spi->controller;
|
||||
u32 save = spi->mode;
|
||||
|
||||
if (tmp & ~SPI_MODE_MASK) {
|
||||
|
|
@ -403,6 +404,10 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
|||
break;
|
||||
}
|
||||
|
||||
if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&
|
||||
ctlr->cs_gpiods[spi->chip_select])
|
||||
tmp |= SPI_CS_HIGH;
|
||||
|
||||
tmp |= spi->mode & ~SPI_MODE_MASK;
|
||||
spi->mode = (u16)tmp;
|
||||
retval = spi_setup(spi);
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ struct omap2_mcspi_platform_config {
|
|||
unsigned short num_cs;
|
||||
unsigned int regs_offset;
|
||||
unsigned int pin_dir:1;
|
||||
size_t max_xfer_len;
|
||||
};
|
||||
|
||||
struct omap2_mcspi_device_config {
|
||||
|
|
|
|||
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Ссылка в новой задаче