clk/samsung updates for v4.15, part 2
- An addition of separate driver for the Exynos 4412 ISP CMU, needed
to model and properly handle the clock controller's dependencies
on the ISP power domain.
- Adding __maybe_unused attributes to the exynos5433_cmu_{suspend,
resume} ops to suppress compiler warnings with CONFIG_PM disabled.
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Merge tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next
Pull Samsung clk driver updates from Sylwester Nawrocki:
- An addition of separate driver for the Exynos 4412 ISP CMU, needed
to model and properly handle the clock controller's dependencies
on the ISP power domain.
- Adding __maybe_unused attributes to the exynos5433_cmu_{suspend,
resume} ops to suppress compiler warnings with CONFIG_PM disabled.
* tag 'clk-v4.15-exynos-pm' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Add a separate driver for Exynos4412 ISP clocks
clk: samsung: Add dt bindings for Exynos4412 ISP clock controller
clk: samsung: Instantiate Exynos4412 ISP clocks only when available
clk: samsung: exynos5433: mark PM functions as __maybe_unused
This commit is contained in:
Stephen Boyd
Коммит
ae74ac0828
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@ -41,3 +41,46 @@ Example 2: UART controller node that consumes the clock generated by the clock
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clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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};
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Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
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subsystem. Registers for those clocks are located in the ISP power domain.
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Because those registers are also located in a different memory region than
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the main clock controller, a separate clock controller has to be defined for
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handling them.
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Required Properties:
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- compatible: should be "samsung,exynos4412-isp-clock".
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- reg: physical base address of the ISP clock controller and length of memory
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mapped region.
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- #clock-cells: should be 1.
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- clocks: list of the clock controller input clock identifiers,
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from common clock bindings, should point to CLK_ACLK200 and
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CLK_ACLK400_MCUISP clocks from the main clock controller.
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- clock-names: list of the clock controller input clock names,
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as described in clock-bindings.txt, should be "aclk200" and
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"aclk400_mcuisp".
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- power-domains: a phandle to ISP power domain node as described by
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generic PM domain bindings.
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Example 3: The clock controllers bindings for Exynos4412 SoCs.
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clock: clock-controller@10030000 {
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compatible = "samsung,exynos4412-clock";
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reg = <0x10030000 0x18000>;
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#clock-cells = <1>;
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};
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isp_clock: clock-controller@10048000 {
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compatible = "samsung,exynos4412-isp-clock";
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reg = <0x10048000 0x1000>;
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#clock-cells = <1>;
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power-domains = <&pd_isp>;
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clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
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clock-names = "aclk200", "aclk400_mcuisp";
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};
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@ -5,6 +5,7 @@
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obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
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obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4412-isp.o
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obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
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obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
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obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
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@ -836,6 +836,12 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
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DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
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DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
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DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
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DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
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DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
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DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
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};
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static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
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DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
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CLK_GET_RATE_NOCACHE, 0),
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DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
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@ -845,9 +851,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
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4, 3, CLK_GET_RATE_NOCACHE, 0),
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DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
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8, 3, CLK_GET_RATE_NOCACHE, 0),
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DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
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DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
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DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
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};
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/* list of gate clocks supported in all exynos4 soc's */
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@ -1141,6 +1144,13 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
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0, 0),
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GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
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0, 0),
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GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
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GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
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GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
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0),
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};
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static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
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GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
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@ -1193,10 +1203,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
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GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
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GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
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0),
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};
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/*
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@ -1497,6 +1503,8 @@ static void __init exynos4_clk_init(struct device_node *np,
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e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
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CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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} else {
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struct resource res;
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samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
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ARRAY_SIZE(exynos4x12_mux_clks));
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samsung_clk_register_div(ctx, exynos4x12_div_clks,
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@ -1506,6 +1514,15 @@ static void __init exynos4_clk_init(struct device_node *np,
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samsung_clk_register_fixed_factor(ctx,
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exynos4x12_fixed_factor_clks,
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ARRAY_SIZE(exynos4x12_fixed_factor_clks));
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of_address_to_resource(np, 0, &res);
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if (resource_size(&res) > 0x18000) {
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samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
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ARRAY_SIZE(exynos4x12_isp_div_clks));
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samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
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ARRAY_SIZE(exynos4x12_isp_gate_clks));
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}
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
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@ -0,0 +1,179 @@
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/*
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* Copyright (c) 2017 Samsung Electronics Co., Ltd.
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* Author: Marek Szyprowski <m.szyprowski@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for Exynos4412 ISP module.
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*/
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#include <dt-bindings/clock/exynos4.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "clk.h"
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/* Exynos4x12 specific registers, which belong to ISP power domain */
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#define E4X12_DIV_ISP0 0x0300
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#define E4X12_DIV_ISP1 0x0304
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#define E4X12_GATE_ISP0 0x0800
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#define E4X12_GATE_ISP1 0x0804
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/*
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* Support for CMU save/restore across system suspends
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*/
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static struct samsung_clk_reg_dump *exynos4x12_save_isp;
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static const unsigned long exynos4x12_clk_isp_save[] __initconst = {
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E4X12_DIV_ISP0,
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E4X12_DIV_ISP1,
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E4X12_GATE_ISP0,
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E4X12_GATE_ISP1,
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};
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PNAME(mout_user_aclk400_mcuisp_p4x12) = { "fin_pll", "div_aclk400_mcuisp", };
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static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
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DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
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DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
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DIV(CLK_ISP_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp",
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E4X12_DIV_ISP1, 4, 3),
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DIV(CLK_ISP_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0",
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E4X12_DIV_ISP1, 8, 3),
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DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
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};
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static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
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GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
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GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
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GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
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GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
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GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
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GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
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GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0),
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GATE(CLK_ISP_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 0, 0),
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GATE(CLK_ISP_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 0, 0),
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GATE(CLK_ISP_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 0, 0),
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GATE(CLK_ISP_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
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0, 0),
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GATE(CLK_ISP_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
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0, 0),
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GATE(CLK_ISP_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
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0, 0),
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GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
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0, 0),
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GATE(CLK_ISP_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
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0, 0),
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GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
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0, 0),
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GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
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0, 0),
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GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
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0, 0),
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GATE(CLK_ISP_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
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0, 0),
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GATE(CLK_ISP_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 0, 0),
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GATE(CLK_ISP_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 0, 0),
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GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
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0, 0),
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GATE(CLK_ISP_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
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0, 0),
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GATE(CLK_ISP_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
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0, 0),
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GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
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0, 0),
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GATE(CLK_ISP_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
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0, 0),
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};
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static int __maybe_unused exynos4x12_isp_clk_suspend(struct device *dev)
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{
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struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
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samsung_clk_save(ctx->reg_base, exynos4x12_save_isp,
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ARRAY_SIZE(exynos4x12_clk_isp_save));
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return 0;
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}
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static int __maybe_unused exynos4x12_isp_clk_resume(struct device *dev)
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{
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struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
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samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp,
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ARRAY_SIZE(exynos4x12_clk_isp_save));
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return 0;
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}
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static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
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{
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struct samsung_clk_provider *ctx;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct resource *res;
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void __iomem *reg_base;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(reg_base)) {
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dev_err(dev, "failed to map registers\n");
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return PTR_ERR(reg_base);
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}
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|
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exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save,
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ARRAY_SIZE(exynos4x12_clk_isp_save));
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if (!exynos4x12_save_isp)
|
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return -ENOMEM;
|
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|
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ctx = samsung_clk_init(np, reg_base, CLK_NR_ISP_CLKS);
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ctx->dev = dev;
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platform_set_drvdata(pdev, ctx);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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pm_runtime_get_sync(dev);
|
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samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
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ARRAY_SIZE(exynos4x12_isp_div_clks));
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samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
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ARRAY_SIZE(exynos4x12_isp_gate_clks));
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samsung_clk_of_add_provider(np, ctx);
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pm_runtime_put(dev);
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return 0;
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}
|
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|
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static const struct of_device_id exynos4x12_isp_clk_of_match[] = {
|
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{ .compatible = "samsung,exynos4412-isp-clock", },
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{ },
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};
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|
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static const struct dev_pm_ops exynos4x12_isp_pm_ops = {
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SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend,
|
||||
exynos4x12_isp_clk_resume, NULL)
|
||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver exynos4x12_isp_clk_driver __refdata = {
|
||||
.driver = {
|
||||
.name = "exynos4x12-isp-clk",
|
||||
.of_match_table = exynos4x12_isp_clk_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
.pm = &exynos4x12_isp_pm_ops,
|
||||
},
|
||||
.probe = exynos4x12_isp_clk_probe,
|
||||
};
|
||||
|
||||
static int __init exynos4x12_isp_clk_init(void)
|
||||
{
|
||||
return platform_driver_register(&exynos4x12_isp_clk_driver);
|
||||
}
|
||||
core_initcall(exynos4x12_isp_clk_init);
|
||||
|
|
@ -5450,7 +5450,7 @@ struct exynos5433_cmu_data {
|
|||
struct samsung_clk_provider ctx;
|
||||
};
|
||||
|
||||
static int exynos5433_cmu_suspend(struct device *dev)
|
||||
static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
|
||||
{
|
||||
struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
|
||||
int i;
|
||||
|
|
@ -5473,7 +5473,7 @@ static int exynos5433_cmu_suspend(struct device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int exynos5433_cmu_resume(struct device *dev)
|
||||
static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
|
||||
{
|
||||
struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
|
||||
int i;
|
||||
|
|
|
|||
|
|
@ -272,4 +272,39 @@
|
|||
/* must be greater than maximal clock id */
|
||||
#define CLK_NR_CLKS 461
|
||||
|
||||
/* Exynos4x12 ISP clocks */
|
||||
#define CLK_ISP_FIMC_ISP 1
|
||||
#define CLK_ISP_FIMC_DRC 2
|
||||
#define CLK_ISP_FIMC_FD 3
|
||||
#define CLK_ISP_FIMC_LITE0 4
|
||||
#define CLK_ISP_FIMC_LITE1 5
|
||||
#define CLK_ISP_MCUISP 6
|
||||
#define CLK_ISP_GICISP 7
|
||||
#define CLK_ISP_SMMU_ISP 8
|
||||
#define CLK_ISP_SMMU_DRC 9
|
||||
#define CLK_ISP_SMMU_FD 10
|
||||
#define CLK_ISP_SMMU_LITE0 11
|
||||
#define CLK_ISP_SMMU_LITE1 12
|
||||
#define CLK_ISP_PPMUISPMX 13
|
||||
#define CLK_ISP_PPMUISPX 14
|
||||
#define CLK_ISP_MCUCTL_ISP 15
|
||||
#define CLK_ISP_MPWM_ISP 16
|
||||
#define CLK_ISP_I2C0_ISP 17
|
||||
#define CLK_ISP_I2C1_ISP 18
|
||||
#define CLK_ISP_MTCADC_ISP 19
|
||||
#define CLK_ISP_PWM_ISP 20
|
||||
#define CLK_ISP_WDT_ISP 21
|
||||
#define CLK_ISP_UART_ISP 22
|
||||
#define CLK_ISP_ASYNCAXIM 23
|
||||
#define CLK_ISP_SMMU_ISPCX 24
|
||||
#define CLK_ISP_SPI0_ISP 25
|
||||
#define CLK_ISP_SPI1_ISP 26
|
||||
|
||||
#define CLK_ISP_DIV_ISP0 27
|
||||
#define CLK_ISP_DIV_ISP1 28
|
||||
#define CLK_ISP_DIV_MCUISP0 29
|
||||
#define CLK_ISP_DIV_MCUISP1 30
|
||||
|
||||
#define CLK_NR_ISP_CLKS 31
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
|
||||
|
|
|
|||
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