ARM: dts: ixp4xx: Add Gateworks Avila GW2348 device tree
This adds a device tree file for the Gateworks Avila GW2348 platform supporting all the features of the in-kernel boardfiles. There are more boards in the Avila family, but this is the one that is supported out-of-the-box by the current boardfiles. Some extra features have been folded in from the upstream OpenWrt sources, such as proper ethernet setup for both ethernet ports. More variants can be added based on this device tree. Some of those have DSA switches, multiple LEDs, multiple serial ports and similar and would need some more elaborate work. Cc: Michael-Luke Jones <mlj28@cam.ac.uk> Cc: Deepak Saxena <dsaxena@plexity.net> Cc: Tom Billman <kernel@giantshoulderinc.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij
Родитель
36eb2640d3
Коммит
ae751e6325
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@ -244,6 +244,7 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
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intel-ixp42x-welltech-epbx100.dtb \
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intel-ixp42x-iomega-nas100d.dtb \
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intel-ixp42x-dlink-dsm-g600.dtb \
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intel-ixp42x-gateworks-gw2348.dtb \
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intel-ixp43x-gateworks-gw2358.dtb \
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intel-ixp42x-netgear-wg302v2.dtb \
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intel-ixp42x-arcom-vulcan.dtb
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@ -0,0 +1,172 @@
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// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for the Gateworks Avila GW2348 board.
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* This machine is based on IXP425.
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*/
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/dts-v1/;
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#include "intel-ixp42x.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Gateworks Avila GW2348";
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compatible = "gateworks,gw2348", "intel,ixp42x";
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#address-cells = <1>;
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#size-cells = <1>;
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x4000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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stdout-path = "uart0:115200n8";
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};
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aliases {
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serial0 = &uart0;
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};
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leds {
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compatible = "gpio-leds";
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led-user {
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label = "gw2348:green:user";
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gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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};
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i2c {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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hwmon@28 {
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compatible = "adi,ad7418";
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reg = <0x28>;
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};
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rtc: ds1672@68 {
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compatible = "dallas,ds1672";
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reg = <0x68>;
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};
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eeprom@51 {
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compatible = "atmel,24c08";
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reg = <0x51>;
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pagesize = <16>;
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size = <1024>;
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read-only;
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};
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};
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soc {
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bus@c4000000 {
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/* Enable writes on the expansion bus */
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intel,ixp4xx-eb-write-enable = <1>;
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/* 16 MB of Flash mapped in at CS0 */
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reg = <0 0x00000000 0x1000000>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x0fe0000 */
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fis-index-block = <0x7f>;
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};
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};
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ide@1,0 {
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compatible = "intel,ixp4xx-compact-flash";
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/*
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* Set up expansion bus config to a really slow timing.
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* The CF driver will dynamically reconfigure these timings
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* depending on selected PIO mode (0-4).
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*/
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intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
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intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
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intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
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intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
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intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
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intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
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intel,ixp4xx-eb-byte-access-on-halfword = <1>;
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intel,ixp4xx-eb-mux-address-and-data = <0>;
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intel,ixp4xx-eb-ahb-split-transfers = <0>;
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <1>;
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/* First register set is CMD second is CTL (notice it uses CS2) */
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reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>;
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interrupt-parent = <&gpio0>;
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interrupts = <12 IRQ_TYPE_EDGE_RISING>;
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};
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/*
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* FIXME: Latch LEDs or extra UARTs at CS4
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*/
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};
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pci@c0000000 {
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status = "ok";
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/*
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* Taken from Avila PCI boardfile.
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*
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* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
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*/
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interrupt-map =
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/* IDSEL 1 */
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<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
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<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
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<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
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<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
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/* IDSEL 2 */
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<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
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<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
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<0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
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<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
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/* IDSEL 3 */
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<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
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<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
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<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
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<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
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/* IDSEL 4 */
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<0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
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<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
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<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
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<0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
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};
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/* EthB */
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ethernet@c8009000 {
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status = "ok";
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 20>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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/* EthC */
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ethernet@c800a000 {
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status = "ok";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 21>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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};
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};
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