crypto: keembay-ocs-hcu - Add HMAC support
Add HMAC support to the Keem Bay OCS HCU driver, thus making it provide the following additional transformations: - hmac(sha256) - hmac(sha384) - hmac(sha512) - hmac(sm3) The Keem Bay OCS HCU hardware does not allow "context-switch" for HMAC operations, i.e., it does not support computing a partial HMAC, save its state and then continue it later. Therefore, full hardware acceleration is provided only when possible (e.g., when crypto_ahash_digest() is called); in all other cases hardware acceleration is only partial (OPAD and IPAD calculation is done in software, while hashing is hardware accelerated). Co-developed-by: Declan Murphy <declan.murphy@intel.com> Signed-off-by: Declan Murphy <declan.murphy@intel.com> Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Daniele Alessandrelli
Herbert Xu
Родитель
472b04444c
Коммит
ae832e329a
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@ -49,7 +49,7 @@ config CRYPTO_DEV_KEEMBAY_OCS_HCU
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Control Unit (HCU) hardware acceleration for use with Crypto API.
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Provides OCS HCU hardware acceleration of sha256, sha384, sha512, and
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sm3.
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sm3, as well as the HMAC variant of these algorithms.
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Say Y or M if you're building for the Intel Keem Bay SoC. If compiled
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as a module, the module will be called keembay-ocs-hcu.
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@ -16,6 +16,7 @@
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#include <crypto/scatterwalk.h>
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#include <crypto/sha2.h>
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#include <crypto/sm3.h>
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#include <crypto/hmac.h>
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#include <crypto/internal/hash.h>
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#include "ocs-hcu.h"
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@ -24,17 +25,29 @@
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/* Flag marking a final request. */
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#define REQ_FINAL BIT(0)
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/* Flag marking a HMAC request. */
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#define REQ_FLAGS_HMAC BIT(1)
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/* Flag set when HW HMAC is being used. */
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#define REQ_FLAGS_HMAC_HW BIT(2)
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/* Flag set when SW HMAC is being used. */
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#define REQ_FLAGS_HMAC_SW BIT(3)
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/**
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* struct ocs_hcu_ctx: OCS HCU Transform context.
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* @engine_ctx: Crypto Engine context.
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* @hcu_dev: The OCS HCU device used by the transformation.
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* @key: The key (used only for HMAC transformations).
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* @key_len: The length of the key.
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* @is_sm3_tfm: Whether or not this is an SM3 transformation.
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* @is_hmac_tfm: Whether or not this is a HMAC transformation.
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*/
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struct ocs_hcu_ctx {
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struct crypto_engine_ctx engine_ctx;
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struct ocs_hcu_dev *hcu_dev;
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u8 key[SHA512_BLOCK_SIZE];
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size_t key_len;
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bool is_sm3_tfm;
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bool is_hmac_tfm;
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};
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/**
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@ -46,7 +59,8 @@ struct ocs_hcu_ctx {
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* @dig_sz: Digest size of the transformation / request.
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* @dma_list: OCS DMA linked list.
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* @hash_ctx: OCS HCU hashing context.
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* @buffer: Buffer to store partial block of data.
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* @buffer: Buffer to store: partial block of data and SW HMAC
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* artifacts (ipad, opad, etc.).
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* @buf_cnt: Number of bytes currently stored in the buffer.
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* @buf_dma_addr: The DMA address of @buffer (when mapped).
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* @buf_dma_count: The number of bytes in @buffer currently DMA-mapped.
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@ -63,7 +77,13 @@ struct ocs_hcu_rctx {
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size_t dig_sz;
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struct ocs_hcu_dma_list *dma_list;
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struct ocs_hcu_hash_ctx hash_ctx;
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u8 buffer[SHA512_BLOCK_SIZE];
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/*
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* Buffer is double the block size because we need space for SW HMAC
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* artifacts, i.e:
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* - ipad (1 block) + a possible partial block of data.
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* - opad (1 block) + digest of H(k ^ ipad || m)
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*/
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u8 buffer[2 * SHA512_BLOCK_SIZE];
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size_t buf_cnt;
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dma_addr_t buf_dma_addr;
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size_t buf_dma_count;
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@ -352,19 +372,82 @@ static int kmb_ocs_hcu_handle_queue(struct ahash_request *req)
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return crypto_transfer_hash_request_to_engine(hcu_dev->engine, req);
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}
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static int prepare_ipad(struct ahash_request *req)
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{
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struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct ocs_hcu_ctx *ctx = crypto_ahash_ctx(tfm);
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int i;
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WARN(rctx->buf_cnt, "%s: Context buffer is not empty\n", __func__);
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WARN(!(rctx->flags & REQ_FLAGS_HMAC_SW),
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"%s: HMAC_SW flag is not set\n", __func__);
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/*
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* Key length must be equal to block size. If key is shorter,
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* we pad it with zero (note: key cannot be longer, since
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* longer keys are hashed by kmb_ocs_hcu_setkey()).
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*/
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if (ctx->key_len > rctx->blk_sz) {
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WARN("%s: Invalid key length in tfm context\n", __func__);
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return -EINVAL;
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}
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memzero_explicit(&ctx->key[ctx->key_len],
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rctx->blk_sz - ctx->key_len);
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ctx->key_len = rctx->blk_sz;
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/*
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* Prepare IPAD for HMAC. Only done for first block.
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* HMAC(k,m) = H(k ^ opad || H(k ^ ipad || m))
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* k ^ ipad will be first hashed block.
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* k ^ opad will be calculated in the final request.
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* Only needed if not using HW HMAC.
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*/
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for (i = 0; i < rctx->blk_sz; i++)
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rctx->buffer[i] = ctx->key[i] ^ HMAC_IPAD_VALUE;
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rctx->buf_cnt = rctx->blk_sz;
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return 0;
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}
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static int kmb_ocs_hcu_do_one_request(struct crypto_engine *engine, void *areq)
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{
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struct ahash_request *req = container_of(areq, struct ahash_request,
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base);
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struct ocs_hcu_dev *hcu_dev = kmb_ocs_hcu_find_dev(req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
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struct ocs_hcu_ctx *tctx = crypto_ahash_ctx(tfm);
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int rc;
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int i;
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if (!hcu_dev) {
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rc = -ENOENT;
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goto error;
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}
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/*
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* If hardware HMAC flag is set, perform HMAC in hardware.
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*
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* NOTE: this flag implies REQ_FINAL && kmb_get_total_data(rctx)
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*/
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if (rctx->flags & REQ_FLAGS_HMAC_HW) {
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/* Map input data into the HCU DMA linked list. */
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rc = kmb_ocs_dma_prepare(req);
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if (rc)
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goto error;
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rc = ocs_hcu_hmac(hcu_dev, rctx->algo, tctx->key, tctx->key_len,
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rctx->dma_list, req->result, rctx->dig_sz);
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/* Unmap data and free DMA list regardless of return code. */
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kmb_ocs_hcu_dma_cleanup(req, rctx);
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/* Process previous return code. */
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if (rc)
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goto error;
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goto done;
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}
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/* Handle update request case. */
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if (!(rctx->flags & REQ_FINAL)) {
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/* Update should always have input data. */
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@ -433,6 +516,36 @@ static int kmb_ocs_hcu_do_one_request(struct crypto_engine *engine, void *areq)
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goto error;
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}
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/*
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* If we are finalizing a SW HMAC request, we just computed the result
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* of: H(k ^ ipad || m).
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*
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* We now need to complete the HMAC calculation with the OPAD step,
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* that is, we need to compute H(k ^ opad || digest), where digest is
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* the digest we just obtained, i.e., H(k ^ ipad || m).
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*/
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if (rctx->flags & REQ_FLAGS_HMAC_SW) {
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/*
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* Compute k ^ opad and store it in the request buffer (which
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* is not used anymore at this point).
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* Note: key has been padded / hashed already (so keylen ==
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* blksz) .
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*/
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WARN_ON(tctx->key_len != rctx->blk_sz);
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for (i = 0; i < rctx->blk_sz; i++)
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rctx->buffer[i] = tctx->key[i] ^ HMAC_OPAD_VALUE;
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/* Now append the digest to the rest of the buffer. */
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for (i = 0; (i < rctx->dig_sz); i++)
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rctx->buffer[rctx->blk_sz + i] = req->result[i];
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/* Now hash the buffer to obtain the final HMAC. */
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rc = ocs_hcu_digest(hcu_dev, rctx->algo, rctx->buffer,
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rctx->blk_sz + rctx->dig_sz, req->result,
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rctx->dig_sz);
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if (rc)
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goto error;
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}
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/* Perform secure clean-up. */
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kmb_ocs_hcu_secure_cleanup(req);
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done:
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@ -486,12 +599,17 @@ static int kmb_ocs_hcu_init(struct ahash_request *req)
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/* Initialize intermediate data. */
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ocs_hcu_hash_init(&rctx->hash_ctx, rctx->algo);
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/* If this a HMAC request, set HMAC flag. */
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if (ctx->is_hmac_tfm)
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rctx->flags |= REQ_FLAGS_HMAC;
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return 0;
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}
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static int kmb_ocs_hcu_update(struct ahash_request *req)
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{
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struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
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int rc;
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if (!req->nbytes)
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return 0;
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@ -500,6 +618,19 @@ static int kmb_ocs_hcu_update(struct ahash_request *req)
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rctx->sg_data_offset = 0;
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rctx->sg = req->src;
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/*
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* If we are doing HMAC, then we must use SW-assisted HMAC, since HW
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* HMAC does not support context switching (there it can only be used
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* with finup() or digest()).
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*/
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if (rctx->flags & REQ_FLAGS_HMAC &&
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!(rctx->flags & REQ_FLAGS_HMAC_SW)) {
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rctx->flags |= REQ_FLAGS_HMAC_SW;
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rc = prepare_ipad(req);
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if (rc)
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return rc;
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}
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/*
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* If remaining sg_data fits into ctx buffer, just copy it there; we'll
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* process it at the next update() or final().
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@ -510,6 +641,44 @@ static int kmb_ocs_hcu_update(struct ahash_request *req)
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return kmb_ocs_hcu_handle_queue(req);
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}
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/* Common logic for kmb_ocs_hcu_final() and kmb_ocs_hcu_finup(). */
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static int kmb_ocs_hcu_fin_common(struct ahash_request *req)
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{
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struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct ocs_hcu_ctx *ctx = crypto_ahash_ctx(tfm);
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int rc;
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rctx->flags |= REQ_FINAL;
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/*
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* If this is a HMAC request and, so far, we didn't have to switch to
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* SW HMAC, check if we can use HW HMAC.
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*/
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if (rctx->flags & REQ_FLAGS_HMAC &&
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!(rctx->flags & REQ_FLAGS_HMAC_SW)) {
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/*
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* If we are here, it means we never processed any data so far,
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* so we can use HW HMAC, but only if there is some data to
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* process (since OCS HW MAC does not support zero-length
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* messages) and the key length is supported by the hardware
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* (OCS HCU HW only supports length <= 64); if HW HMAC cannot
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* be used, fall back to SW-assisted HMAC.
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*/
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if (kmb_get_total_data(rctx) &&
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ctx->key_len <= OCS_HCU_HW_KEY_LEN) {
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rctx->flags |= REQ_FLAGS_HMAC_HW;
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} else {
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rctx->flags |= REQ_FLAGS_HMAC_SW;
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rc = prepare_ipad(req);
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if (rc)
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return rc;
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}
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}
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return kmb_ocs_hcu_handle_queue(req);
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}
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static int kmb_ocs_hcu_final(struct ahash_request *req)
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{
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struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
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@ -518,9 +687,7 @@ static int kmb_ocs_hcu_final(struct ahash_request *req)
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rctx->sg_data_offset = 0;
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rctx->sg = NULL;
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rctx->flags |= REQ_FINAL;
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return kmb_ocs_hcu_handle_queue(req);
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return kmb_ocs_hcu_fin_common(req);
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}
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static int kmb_ocs_hcu_finup(struct ahash_request *req)
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@ -531,9 +698,7 @@ static int kmb_ocs_hcu_finup(struct ahash_request *req)
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rctx->sg_data_offset = 0;
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rctx->sg = req->src;
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rctx->flags |= REQ_FINAL;
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return kmb_ocs_hcu_handle_queue(req);
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return kmb_ocs_hcu_fin_common(req);
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}
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static int kmb_ocs_hcu_digest(struct ahash_request *req)
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@ -573,6 +738,76 @@ static int kmb_ocs_hcu_import(struct ahash_request *req, const void *in)
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return 0;
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}
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static int kmb_ocs_hcu_setkey(struct crypto_ahash *tfm, const u8 *key,
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unsigned int keylen)
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{
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unsigned int digestsize = crypto_ahash_digestsize(tfm);
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struct ocs_hcu_ctx *ctx = crypto_ahash_ctx(tfm);
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size_t blk_sz = crypto_ahash_blocksize(tfm);
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struct crypto_ahash *ahash_tfm;
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struct ahash_request *req;
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struct crypto_wait wait;
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struct scatterlist sg;
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const char *alg_name;
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int rc;
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/*
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* Key length must be equal to block size:
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* - If key is shorter, we are done for now (the key will be padded
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* later on); this is to maximize the use of HW HMAC (which works
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* only for keys <= 64 bytes).
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* - If key is longer, we hash it.
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*/
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if (keylen <= blk_sz) {
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memcpy(ctx->key, key, keylen);
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ctx->key_len = keylen;
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return 0;
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}
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switch (digestsize) {
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case SHA256_DIGEST_SIZE:
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alg_name = ctx->is_sm3_tfm ? "sm3-keembay-ocs" :
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"sha256-keembay-ocs";
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break;
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case SHA384_DIGEST_SIZE:
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alg_name = "sha384-keembay-ocs";
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break;
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case SHA512_DIGEST_SIZE:
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alg_name = "sha512-keembay-ocs";
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break;
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default:
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return -EINVAL;
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}
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ahash_tfm = crypto_alloc_ahash(alg_name, 0, 0);
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if (IS_ERR(ahash_tfm))
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return PTR_ERR(ahash_tfm);
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req = ahash_request_alloc(ahash_tfm, GFP_KERNEL);
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if (!req) {
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rc = -ENOMEM;
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goto err_free_ahash;
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}
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crypto_init_wait(&wait);
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ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
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crypto_req_done, &wait);
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crypto_ahash_clear_flags(ahash_tfm, ~0);
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sg_init_one(&sg, key, keylen);
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ahash_request_set_crypt(req, &sg, ctx->key, keylen);
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rc = crypto_wait_req(crypto_ahash_digest(req), &wait);
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if (rc == 0)
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ctx->key_len = digestsize;
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ahash_request_free(req);
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err_free_ahash:
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crypto_free_ahash(ahash_tfm);
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return rc;
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}
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/* Set request size and initialize tfm context. */
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static void __cra_init(struct crypto_tfm *tfm, struct ocs_hcu_ctx *ctx)
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{
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@ -605,6 +840,38 @@ static int kmb_ocs_hcu_sm3_cra_init(struct crypto_tfm *tfm)
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return 0;
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}
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static int kmb_ocs_hcu_hmac_sm3_cra_init(struct crypto_tfm *tfm)
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{
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struct ocs_hcu_ctx *ctx = crypto_tfm_ctx(tfm);
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__cra_init(tfm, ctx);
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ctx->is_sm3_tfm = true;
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ctx->is_hmac_tfm = true;
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return 0;
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}
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static int kmb_ocs_hcu_hmac_cra_init(struct crypto_tfm *tfm)
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{
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struct ocs_hcu_ctx *ctx = crypto_tfm_ctx(tfm);
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__cra_init(tfm, ctx);
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ctx->is_hmac_tfm = true;
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return 0;
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}
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/* Function called when 'tfm' is de-initialized. */
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static void kmb_ocs_hcu_hmac_cra_exit(struct crypto_tfm *tfm)
|
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{
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struct ocs_hcu_ctx *ctx = crypto_tfm_ctx(tfm);
|
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|
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/* Clear the key. */
|
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memzero_explicit(ctx->key, sizeof(ctx->key));
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}
|
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static struct ahash_alg ocs_hcu_algs[] = {
|
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{
|
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.init = kmb_ocs_hcu_init,
|
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|
|
@ -630,6 +897,32 @@ static struct ahash_alg ocs_hcu_algs[] = {
|
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}
|
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}
|
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},
|
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{
|
||||
.init = kmb_ocs_hcu_init,
|
||||
.update = kmb_ocs_hcu_update,
|
||||
.final = kmb_ocs_hcu_final,
|
||||
.finup = kmb_ocs_hcu_finup,
|
||||
.digest = kmb_ocs_hcu_digest,
|
||||
.export = kmb_ocs_hcu_export,
|
||||
.import = kmb_ocs_hcu_import,
|
||||
.setkey = kmb_ocs_hcu_setkey,
|
||||
.halg = {
|
||||
.digestsize = SHA256_DIGEST_SIZE,
|
||||
.statesize = sizeof(struct ocs_hcu_rctx),
|
||||
.base = {
|
||||
.cra_name = "hmac(sha256)",
|
||||
.cra_driver_name = "hmac-sha256-keembay-ocs",
|
||||
.cra_priority = 255,
|
||||
.cra_flags = CRYPTO_ALG_ASYNC,
|
||||
.cra_blocksize = SHA256_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct ocs_hcu_ctx),
|
||||
.cra_alignmask = 0,
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_init = kmb_ocs_hcu_hmac_cra_init,
|
||||
.cra_exit = kmb_ocs_hcu_hmac_cra_exit,
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
.init = kmb_ocs_hcu_init,
|
||||
.update = kmb_ocs_hcu_update,
|
||||
|
|
@ -654,6 +947,32 @@ static struct ahash_alg ocs_hcu_algs[] = {
|
|||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
.init = kmb_ocs_hcu_init,
|
||||
.update = kmb_ocs_hcu_update,
|
||||
.final = kmb_ocs_hcu_final,
|
||||
.finup = kmb_ocs_hcu_finup,
|
||||
.digest = kmb_ocs_hcu_digest,
|
||||
.export = kmb_ocs_hcu_export,
|
||||
.import = kmb_ocs_hcu_import,
|
||||
.setkey = kmb_ocs_hcu_setkey,
|
||||
.halg = {
|
||||
.digestsize = SM3_DIGEST_SIZE,
|
||||
.statesize = sizeof(struct ocs_hcu_rctx),
|
||||
.base = {
|
||||
.cra_name = "hmac(sm3)",
|
||||
.cra_driver_name = "hmac-sm3-keembay-ocs",
|
||||
.cra_priority = 255,
|
||||
.cra_flags = CRYPTO_ALG_ASYNC,
|
||||
.cra_blocksize = SM3_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct ocs_hcu_ctx),
|
||||
.cra_alignmask = 0,
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_init = kmb_ocs_hcu_hmac_sm3_cra_init,
|
||||
.cra_exit = kmb_ocs_hcu_hmac_cra_exit,
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
.init = kmb_ocs_hcu_init,
|
||||
.update = kmb_ocs_hcu_update,
|
||||
|
|
@ -678,6 +997,32 @@ static struct ahash_alg ocs_hcu_algs[] = {
|
|||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
.init = kmb_ocs_hcu_init,
|
||||
.update = kmb_ocs_hcu_update,
|
||||
.final = kmb_ocs_hcu_final,
|
||||
.finup = kmb_ocs_hcu_finup,
|
||||
.digest = kmb_ocs_hcu_digest,
|
||||
.export = kmb_ocs_hcu_export,
|
||||
.import = kmb_ocs_hcu_import,
|
||||
.setkey = kmb_ocs_hcu_setkey,
|
||||
.halg = {
|
||||
.digestsize = SHA384_DIGEST_SIZE,
|
||||
.statesize = sizeof(struct ocs_hcu_rctx),
|
||||
.base = {
|
||||
.cra_name = "hmac(sha384)",
|
||||
.cra_driver_name = "hmac-sha384-keembay-ocs",
|
||||
.cra_priority = 255,
|
||||
.cra_flags = CRYPTO_ALG_ASYNC,
|
||||
.cra_blocksize = SHA384_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct ocs_hcu_ctx),
|
||||
.cra_alignmask = 0,
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_init = kmb_ocs_hcu_hmac_cra_init,
|
||||
.cra_exit = kmb_ocs_hcu_hmac_cra_exit,
|
||||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
.init = kmb_ocs_hcu_init,
|
||||
.update = kmb_ocs_hcu_update,
|
||||
|
|
@ -702,6 +1047,32 @@ static struct ahash_alg ocs_hcu_algs[] = {
|
|||
}
|
||||
}
|
||||
},
|
||||
{
|
||||
.init = kmb_ocs_hcu_init,
|
||||
.update = kmb_ocs_hcu_update,
|
||||
.final = kmb_ocs_hcu_final,
|
||||
.finup = kmb_ocs_hcu_finup,
|
||||
.digest = kmb_ocs_hcu_digest,
|
||||
.export = kmb_ocs_hcu_export,
|
||||
.import = kmb_ocs_hcu_import,
|
||||
.setkey = kmb_ocs_hcu_setkey,
|
||||
.halg = {
|
||||
.digestsize = SHA512_DIGEST_SIZE,
|
||||
.statesize = sizeof(struct ocs_hcu_rctx),
|
||||
.base = {
|
||||
.cra_name = "hmac(sha512)",
|
||||
.cra_driver_name = "hmac-sha512-keembay-ocs",
|
||||
.cra_priority = 255,
|
||||
.cra_flags = CRYPTO_ALG_ASYNC,
|
||||
.cra_blocksize = SHA512_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct ocs_hcu_ctx),
|
||||
.cra_alignmask = 0,
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_init = kmb_ocs_hcu_hmac_cra_init,
|
||||
.cra_exit = kmb_ocs_hcu_hmac_cra_exit,
|
||||
}
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
/* Device tree driver match. */
|
||||
|
|
|
|||
|
|
@ -367,6 +367,69 @@ static int ocs_hcu_hw_cfg(struct ocs_hcu_dev *hcu_dev, enum ocs_hcu_algo algo,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ocs_hcu_clear_key() - Clear key stored in OCS HMAC KEY registers.
|
||||
* @hcu_dev: The OCS HCU device whose key registers should be cleared.
|
||||
*/
|
||||
static void ocs_hcu_clear_key(struct ocs_hcu_dev *hcu_dev)
|
||||
{
|
||||
int reg_off;
|
||||
|
||||
/* Clear OCS_HCU_KEY_[0..15] */
|
||||
for (reg_off = 0; reg_off < OCS_HCU_HW_KEY_LEN; reg_off += sizeof(u32))
|
||||
writel(0, hcu_dev->io_base + OCS_HCU_KEY_0 + reg_off);
|
||||
}
|
||||
|
||||
/**
|
||||
* ocs_hcu_write_key() - Write key to OCS HMAC KEY registers.
|
||||
* @hcu_dev: The OCS HCU device the key should be written to.
|
||||
* @key: The key to be written.
|
||||
* @len: The size of the key to write. It must be OCS_HCU_HW_KEY_LEN.
|
||||
*
|
||||
* Return: 0 on success, negative error code otherwise.
|
||||
*/
|
||||
static int ocs_hcu_write_key(struct ocs_hcu_dev *hcu_dev, const u8 *key, size_t len)
|
||||
{
|
||||
u32 key_u32[OCS_HCU_HW_KEY_LEN_U32];
|
||||
int i;
|
||||
|
||||
if (len > OCS_HCU_HW_KEY_LEN)
|
||||
return -EINVAL;
|
||||
|
||||
/* Copy key into temporary u32 array. */
|
||||
memcpy(key_u32, key, len);
|
||||
|
||||
/*
|
||||
* Hardware requires all the bytes of the HW Key vector to be
|
||||
* written. So pad with zero until we reach OCS_HCU_HW_KEY_LEN.
|
||||
*/
|
||||
memzero_explicit((u8 *)key_u32 + len, OCS_HCU_HW_KEY_LEN - len);
|
||||
|
||||
/*
|
||||
* OCS hardware expects the MSB of the key to be written at the highest
|
||||
* address of the HCU Key vector; in other word, the key must be
|
||||
* written in reverse order.
|
||||
*
|
||||
* Therefore, we first enable byte swapping for the HCU key vector;
|
||||
* so that bytes of 32-bit word written to OCS_HCU_KEY_[0..15] will be
|
||||
* swapped:
|
||||
* 3 <---> 0, 2 <---> 1.
|
||||
*/
|
||||
writel(HCU_BYTE_ORDER_SWAP,
|
||||
hcu_dev->io_base + OCS_HCU_KEY_BYTE_ORDER_CFG);
|
||||
/*
|
||||
* And then we write the 32-bit words composing the key starting from
|
||||
* the end of the key.
|
||||
*/
|
||||
for (i = 0; i < OCS_HCU_HW_KEY_LEN_U32; i++)
|
||||
writel(key_u32[OCS_HCU_HW_KEY_LEN_U32 - 1 - i],
|
||||
hcu_dev->io_base + OCS_HCU_KEY_0 + (sizeof(u32) * i));
|
||||
|
||||
memzero_explicit(key_u32, OCS_HCU_HW_KEY_LEN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ocs_hcu_ll_dma_start() - Start OCS HCU hashing via DMA
|
||||
* @hcu_dev: The OCS HCU device to use.
|
||||
|
|
@ -649,6 +712,99 @@ int ocs_hcu_hash_final(struct ocs_hcu_dev *hcu_dev,
|
|||
return ocs_hcu_get_digest(hcu_dev, ctx->algo, dgst, dgst_len);
|
||||
}
|
||||
|
||||
/**
|
||||
* ocs_hcu_digest() - Compute hash digest.
|
||||
* @hcu_dev: The OCS HCU device to use.
|
||||
* @algo: The hash algorithm to use.
|
||||
* @data: The input data to process.
|
||||
* @data_len: The length of @data.
|
||||
* @dgst: The buffer where to save the computed digest.
|
||||
* @dgst_len: The length of @dgst.
|
||||
*
|
||||
* Return: 0 on success; negative error code otherwise.
|
||||
*/
|
||||
int ocs_hcu_digest(struct ocs_hcu_dev *hcu_dev, enum ocs_hcu_algo algo,
|
||||
void *data, size_t data_len, u8 *dgst, size_t dgst_len)
|
||||
{
|
||||
struct device *dev = hcu_dev->dev;
|
||||
dma_addr_t dma_handle;
|
||||
u32 reg;
|
||||
int rc;
|
||||
|
||||
/* Configure the hardware for the current request. */
|
||||
rc = ocs_hcu_hw_cfg(hcu_dev, algo, false);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
dma_handle = dma_map_single(dev, data, data_len, DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(dev, dma_handle))
|
||||
return -EIO;
|
||||
|
||||
reg = HCU_DMA_SNOOP_MASK | HCU_DMA_EN;
|
||||
|
||||
ocs_hcu_done_irq_en(hcu_dev);
|
||||
|
||||
reinit_completion(&hcu_dev->irq_done);
|
||||
|
||||
writel(dma_handle, hcu_dev->io_base + OCS_HCU_DMA_SRC_ADDR);
|
||||
writel(data_len, hcu_dev->io_base + OCS_HCU_DMA_SRC_SIZE);
|
||||
writel(OCS_HCU_START, hcu_dev->io_base + OCS_HCU_OPERATION);
|
||||
writel(reg, hcu_dev->io_base + OCS_HCU_DMA_DMA_MODE);
|
||||
|
||||
writel(OCS_HCU_TERMINATE, hcu_dev->io_base + OCS_HCU_OPERATION);
|
||||
|
||||
rc = ocs_hcu_wait_and_disable_irq(hcu_dev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
dma_unmap_single(dev, dma_handle, data_len, DMA_TO_DEVICE);
|
||||
|
||||
return ocs_hcu_get_digest(hcu_dev, algo, dgst, dgst_len);
|
||||
}
|
||||
|
||||
/**
|
||||
* ocs_hcu_hmac() - Compute HMAC.
|
||||
* @hcu_dev: The OCS HCU device to use.
|
||||
* @algo: The hash algorithm to use with HMAC.
|
||||
* @key: The key to use.
|
||||
* @dma_list: The OCS DMA list mapping the input data to process.
|
||||
* @key_len: The length of @key.
|
||||
* @dgst: The buffer where to save the computed HMAC.
|
||||
* @dgst_len: The length of @dgst.
|
||||
*
|
||||
* Return: 0 on success; negative error code otherwise.
|
||||
*/
|
||||
int ocs_hcu_hmac(struct ocs_hcu_dev *hcu_dev, enum ocs_hcu_algo algo,
|
||||
const u8 *key, size_t key_len,
|
||||
const struct ocs_hcu_dma_list *dma_list,
|
||||
u8 *dgst, size_t dgst_len)
|
||||
{
|
||||
int rc;
|
||||
|
||||
/* Ensure 'key' is not NULL. */
|
||||
if (!key || key_len == 0)
|
||||
return -EINVAL;
|
||||
|
||||
/* Configure the hardware for the current request. */
|
||||
rc = ocs_hcu_hw_cfg(hcu_dev, algo, true);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = ocs_hcu_write_key(hcu_dev, key, key_len);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = ocs_hcu_ll_dma_start(hcu_dev, dma_list, true);
|
||||
|
||||
/* Clear HW key before processing return code. */
|
||||
ocs_hcu_clear_key(hcu_dev);
|
||||
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
return ocs_hcu_get_digest(hcu_dev, algo, dgst, dgst_len);
|
||||
}
|
||||
|
||||
irqreturn_t ocs_hcu_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct ocs_hcu_dev *hcu_dev = dev_id;
|
||||
|
|
|
|||
|
|
@ -95,4 +95,12 @@ int ocs_hcu_hash_final(struct ocs_hcu_dev *hcu_dev,
|
|||
const struct ocs_hcu_hash_ctx *ctx, u8 *dgst,
|
||||
size_t dgst_len);
|
||||
|
||||
int ocs_hcu_digest(struct ocs_hcu_dev *hcu_dev, enum ocs_hcu_algo algo,
|
||||
void *data, size_t data_len, u8 *dgst, size_t dgst_len);
|
||||
|
||||
int ocs_hcu_hmac(struct ocs_hcu_dev *hcu_dev, enum ocs_hcu_algo algo,
|
||||
const u8 *key, size_t key_len,
|
||||
const struct ocs_hcu_dma_list *dma_list,
|
||||
u8 *dgst, size_t dgst_len);
|
||||
|
||||
#endif /* _CRYPTO_OCS_HCU_H */
|
||||
|
|
|
|||
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