ncr5380: Enable PDMA for DTC chips
Add I/O register mapping for DTC chips and enable PDMA mode. These chips have 16-bit wide HOST BUFFER register and it must be read by 16-bit accesses (we lose data otherwise). Large PIO transfers crash at least the DTCT-436P chip (all reads result in 0xFF) so this patch actually makes it work. The chip also crashes when we bang on the C400 host status register too heavily after PDMA write - a small udelay is needed. Tested on DTCT-436P and verified that it does not break 53C400A. Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Ondrej Zary
Martin K. Petersen
Родитель
cecf3beef0
Коммит
aeb51152bb
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@ -327,7 +327,7 @@ static int __init generic_NCR5380_detect(struct scsi_host_template *tpnt)
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ports = ncr_53c400a_ports;
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break;
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case BOARD_DTC3181E:
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flags = FLAG_NO_PSEUDO_DMA;
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flags = FLAG_NO_DMA_FIXUP;
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ports = dtc_3181e_ports;
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break;
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}
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@ -400,6 +400,7 @@ static int __init generic_NCR5380_detect(struct scsi_host_template *tpnt)
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#ifndef SCSI_G_NCR5380_MEM
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instance->io_port = overrides[current_override].NCR5380_map_name;
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instance->n_io_port = region_size;
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hostdata->io_width = 1; /* 8-bit PDMA by default */
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/*
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* On NCR53C400 boards, NCR5380 registers are mapped 8 past
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@ -412,6 +413,9 @@ static int __init generic_NCR5380_detect(struct scsi_host_template *tpnt)
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hostdata->c400_blk_cnt = 1;
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hostdata->c400_host_buf = 4;
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break;
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case BOARD_DTC3181E:
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hostdata->io_width = 2; /* 16-bit PDMA */
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/* fall through */
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case BOARD_NCR53C400A:
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hostdata->c400_ctl_status = 9;
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hostdata->c400_blk_cnt = 10;
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@ -427,6 +431,7 @@ static int __init generic_NCR5380_detect(struct scsi_host_template *tpnt)
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hostdata->c400_blk_cnt = 0x101;
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hostdata->c400_host_buf = 0x104;
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break;
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case BOARD_DTC3181E:
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case BOARD_NCR53C400A:
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pr_err(DRV_MODULE_NAME ": unknown register offsets\n");
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goto out_unregister;
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@ -438,6 +443,7 @@ static int __init generic_NCR5380_detect(struct scsi_host_template *tpnt)
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switch (overrides[current_override].board) {
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case BOARD_NCR53C400:
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case BOARD_DTC3181E:
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case BOARD_NCR53C400A:
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NCR5380_write(hostdata->c400_ctl_status, CSR_BASE);
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}
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@ -565,7 +571,11 @@ static inline int NCR5380_pread(struct Scsi_Host *instance, unsigned char *dst,
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; /* FIXME - no timeout */
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#ifndef SCSI_G_NCR5380_MEM
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insb(instance->io_port + hostdata->c400_host_buf,
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if (hostdata->io_width == 2)
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insw(instance->io_port + hostdata->c400_host_buf,
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dst + start, 64);
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else
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insb(instance->io_port + hostdata->c400_host_buf,
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dst + start, 128);
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#else
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/* implies SCSI_G_NCR5380_MEM */
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@ -581,7 +591,11 @@ static inline int NCR5380_pread(struct Scsi_Host *instance, unsigned char *dst,
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; /* FIXME - no timeout */
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#ifndef SCSI_G_NCR5380_MEM
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insb(instance->io_port + hostdata->c400_host_buf,
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if (hostdata->io_width == 2)
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insw(instance->io_port + hostdata->c400_host_buf,
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dst + start, 64);
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else
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insb(instance->io_port + hostdata->c400_host_buf,
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dst + start, 128);
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#else
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/* implies SCSI_G_NCR5380_MEM */
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@ -639,7 +653,11 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src,
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while (NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY)
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; // FIXME - timeout
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#ifndef SCSI_G_NCR5380_MEM
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outsb(instance->io_port + hostdata->c400_host_buf,
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if (hostdata->io_width == 2)
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outsw(instance->io_port + hostdata->c400_host_buf,
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src + start, 64);
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else
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outsb(instance->io_port + hostdata->c400_host_buf,
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src + start, 128);
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#else
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/* implies SCSI_G_NCR5380_MEM */
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@ -654,7 +672,11 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src,
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; // FIXME - no timeout
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#ifndef SCSI_G_NCR5380_MEM
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outsb(instance->io_port + hostdata->c400_host_buf,
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if (hostdata->io_width == 2)
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outsw(instance->io_port + hostdata->c400_host_buf,
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src + start, 64);
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else
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outsb(instance->io_port + hostdata->c400_host_buf,
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src + start, 128);
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#else
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/* implies SCSI_G_NCR5380_MEM */
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@ -675,8 +697,10 @@ static inline int NCR5380_pwrite(struct Scsi_Host *instance, unsigned char *src,
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/* All documentation says to check for this. Maybe my hardware is too
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* fast. Waiting for it seems to work fine! KLL
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*/
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while (!(i = NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ))
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; // FIXME - no timeout
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while (!(i = NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ)) {
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udelay(4); /* DTC436 chip hangs without this */
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/* FIXME - no timeout */
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}
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/*
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* I know. i is certainly != 0 here but the loop is new. See previous
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@ -44,7 +44,8 @@
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#define NCR5380_implementation_fields \
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int c400_ctl_status; \
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int c400_blk_cnt; \
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int c400_host_buf;
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int c400_host_buf; \
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int io_width;
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#else
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/* therefore SCSI_G_NCR5380_MEM */
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