pinctrl: sunxi: Implement multiple interrupt banks support
The A23 and A31 support multiple interrupt banks. Support it by adding a linear domain covering all the banks. It's trickier than it should because there's an interrupt per bank, so we have multiple interrupts using the same domain. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Maxime Ripard
Linus Walleij
Родитель
c11a33c15e
Коммит
aebdc8abc9
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@ -636,17 +636,28 @@ static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_get_chip(irq);
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struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
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const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
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unsigned long bank, reg, val;
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for (bank = 0; bank < pctl->desc->irq_banks; bank++)
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if (irq == pctl->irq[bank])
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break;
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if (bank == pctl->desc->irq_banks)
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return;
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reg = sunxi_irq_status_reg_from_bank(bank);
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val = readl(pctl->membase + reg);
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/* Clear all interrupts */
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writel(reg, pctl->membase + IRQ_STATUS_REG);
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writel(val, pctl->membase + reg);
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if (reg) {
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if (val) {
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int irqoffset;
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chained_irq_enter(chip, desc);
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for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) {
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int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
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for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
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int pin_irq = irq_find_mapping(pctl->domain,
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bank * IRQ_PER_BANK + irqoffset);
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generic_handle_irq(pin_irq);
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}
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chained_irq_exit(chip, desc);
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@ -714,8 +725,11 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev)
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while (func->name) {
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/* Create interrupt mapping while we're at it */
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if (!strcmp(func->name, "irq"))
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pctl->irq_array[func->irqnum] = pin->pin.number;
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if (!strcmp(func->name, "irq")) {
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int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
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pctl->irq_array[irqnum] = pin->pin.number;
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}
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sunxi_pinctrl_add_function(pctl, func->name);
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func++;
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}
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@ -785,6 +799,13 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
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pctl->dev = &pdev->dev;
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pctl->desc = desc;
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pctl->irq_array = devm_kcalloc(&pdev->dev,
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IRQ_PER_BANK * pctl->desc->irq_banks,
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sizeof(*pctl->irq_array),
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GFP_KERNEL);
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if (!pctl->irq_array)
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return -ENOMEM;
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ret = sunxi_pinctrl_build_state(pdev);
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if (ret) {
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dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
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@ -869,21 +890,34 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
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if (ret)
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goto gpiochip_error;
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pctl->irq = irq_of_parse_and_map(node, 0);
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pctl->irq = devm_kcalloc(&pdev->dev,
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pctl->desc->irq_banks,
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sizeof(*pctl->irq),
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GFP_KERNEL);
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if (!pctl->irq) {
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ret = -EINVAL;
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ret = -ENOMEM;
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goto clk_error;
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}
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pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
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&irq_domain_simple_ops, NULL);
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for (i = 0; i < pctl->desc->irq_banks; i++) {
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pctl->irq[i] = platform_get_irq(pdev, i);
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if (pctl->irq[i] < 0) {
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ret = pctl->irq[i];
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goto clk_error;
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}
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}
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pctl->domain = irq_domain_add_linear(node,
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pctl->desc->irq_banks * IRQ_PER_BANK,
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&irq_domain_simple_ops,
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NULL);
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if (!pctl->domain) {
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dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
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ret = -ENOMEM;
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goto clk_error;
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}
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for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
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for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
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int irqno = irq_create_mapping(pctl->domain, i);
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irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
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@ -891,8 +925,11 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
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irq_set_chip_data(irqno, pctl);
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};
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irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
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irq_set_handler_data(pctl->irq, pctl);
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for (i = 0; i < pctl->desc->irq_banks; i++) {
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irq_set_chained_handler(pctl->irq[i],
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sunxi_pinctrl_irq_handler);
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irq_set_handler_data(pctl->irq[i], pctl);
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}
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dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
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@ -53,7 +53,7 @@
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#define PULL_PINS_BITS 2
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#define PULL_PINS_MASK 0x03
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#define SUNXI_IRQ_NUMBER 32
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#define IRQ_PER_BANK 32
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#define IRQ_CFG_REG 0x200
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#define IRQ_CFG_IRQ_PER_REG 8
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@ -68,6 +68,8 @@
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#define IRQ_STATUS_IRQ_BITS 1
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#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
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#define IRQ_MEM_SIZE 0x20
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#define IRQ_EDGE_RISING 0x00
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#define IRQ_EDGE_FALLING 0x01
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#define IRQ_LEVEL_HIGH 0x02
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@ -115,8 +117,8 @@ struct sunxi_pinctrl {
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unsigned nfunctions;
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struct sunxi_pinctrl_group *groups;
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unsigned ngroups;
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int irq;
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int irq_array[SUNXI_IRQ_NUMBER];
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int *irq;
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unsigned *irq_array;
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spinlock_t lock;
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struct pinctrl_dev *pctl_dev;
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};
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@ -228,8 +230,10 @@ static inline u32 sunxi_pull_offset(u16 pin)
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static inline u32 sunxi_irq_cfg_reg(u16 irq)
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{
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u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
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return reg + IRQ_CFG_REG;
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u8 bank = irq / IRQ_PER_BANK;
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u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
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return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
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}
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static inline u32 sunxi_irq_cfg_offset(u16 irq)
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@ -238,10 +242,16 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
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return irq_num * IRQ_CFG_IRQ_BITS;
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}
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static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
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{
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return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
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}
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static inline u32 sunxi_irq_ctrl_reg(u16 irq)
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{
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u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
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return reg + IRQ_CTRL_REG;
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u8 bank = irq / IRQ_PER_BANK;
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return sunxi_irq_ctrl_reg_from_bank(bank);
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}
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static inline u32 sunxi_irq_ctrl_offset(u16 irq)
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@ -250,10 +260,16 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
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return irq_num * IRQ_CTRL_IRQ_BITS;
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}
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static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
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{
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return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
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}
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static inline u32 sunxi_irq_status_reg(u16 irq)
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{
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u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
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return reg + IRQ_STATUS_REG;
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u8 bank = irq / IRQ_PER_BANK;
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return sunxi_irq_status_reg_from_bank(bank);
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}
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static inline u32 sunxi_irq_status_offset(u16 irq)
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