[PATCH] powerpc: fix various sparse warnings
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Родитель
7c92943c7b
Коммит
af308377e2
|
@ -37,7 +37,7 @@ static int legacy_serial_console = -1;
|
|||
static int __init add_legacy_port(struct device_node *np, int want_index,
|
||||
int iotype, phys_addr_t base,
|
||||
phys_addr_t taddr, unsigned long irq,
|
||||
unsigned int flags)
|
||||
upf_t flags)
|
||||
{
|
||||
u32 *clk, *spd, clock = BASE_BAUD * 16;
|
||||
int index;
|
||||
|
@ -113,7 +113,7 @@ static int __init add_legacy_soc_port(struct device_node *np,
|
|||
{
|
||||
phys_addr_t addr;
|
||||
u32 *addrp;
|
||||
unsigned int flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
|
||||
upf_t flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
|
||||
|
||||
/* We only support ports that have a clock frequency properly
|
||||
* encoded in the device-tree.
|
||||
|
|
|
@ -174,8 +174,9 @@ static int dev_nvram_ioctl(struct inode *inode, struct file *file,
|
|||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PPC_PMAC */
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
struct file_operations nvram_fops = {
|
||||
|
|
|
@ -362,7 +362,11 @@ static void show_instructions(struct pt_regs *regs)
|
|||
if (!(i % 8))
|
||||
printk("\n");
|
||||
|
||||
if (BAD_PC(pc) || __get_user(instr, (unsigned int *)pc)) {
|
||||
/* We use __get_user here *only* to avoid an OOPS on a
|
||||
* bad address because the pc *should* only be a
|
||||
* kernel address.
|
||||
*/
|
||||
if (BAD_PC(pc) || __get_user(instr, (unsigned int __user *)pc)) {
|
||||
printk("XXXXXXXX ");
|
||||
} else {
|
||||
if (regs->nip == pc)
|
||||
|
|
|
@ -111,7 +111,7 @@ unsigned long __init early_init(unsigned long dt_ptr)
|
|||
|
||||
/* First zero the BSS -- use memset_io, some platforms don't have
|
||||
* caches on yet */
|
||||
memset_io(PTRRELOC(&__bss_start), 0, _end - __bss_start);
|
||||
memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, _end - __bss_start);
|
||||
|
||||
/*
|
||||
* Identify the CPU type and fix up code sections
|
||||
|
|
|
@ -18,7 +18,7 @@ extern char system_call_common[];
|
|||
|
||||
#ifdef CONFIG_PPC64
|
||||
/* Bits in SRR1 that are copied from MSR */
|
||||
#define MSR_MASK 0xffffffff87c0ffff
|
||||
#define MSR_MASK 0xffffffff87c0ffffUL
|
||||
#else
|
||||
#define MSR_MASK 0x87c0ffff
|
||||
#endif
|
||||
|
|
|
@ -493,7 +493,7 @@ void __init bootx_init(unsigned long r3, unsigned long r4)
|
|||
&& (strcmp(model, "iMac,1") == 0
|
||||
|| strcmp(model, "PowerMac1,1") == 0)) {
|
||||
bootx_printf("iMac,1 detected, shutting down USB \n");
|
||||
out_le32((unsigned *)0x80880008, 1); /* XXX */
|
||||
out_le32((unsigned __iomem *)0x80880008, 1); /* XXX */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -74,7 +74,7 @@ struct core99_header {
|
|||
* Read and write the non-volatile RAM on PowerMacs and CHRP machines.
|
||||
*/
|
||||
static int nvram_naddrs;
|
||||
static volatile unsigned char *nvram_data;
|
||||
static volatile unsigned char __iomem *nvram_data;
|
||||
static int is_core_99;
|
||||
static int core99_bank = 0;
|
||||
static int nvram_partitions[3];
|
||||
|
@ -148,7 +148,7 @@ static ssize_t core99_nvram_size(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_PPC32
|
||||
static volatile unsigned char *nvram_addr;
|
||||
static volatile unsigned char __iomem *nvram_addr;
|
||||
static int nvram_mult;
|
||||
|
||||
static unsigned char direct_nvram_read_byte(int addr)
|
||||
|
@ -285,7 +285,7 @@ static int sm_erase_bank(int bank)
|
|||
int stat, i;
|
||||
unsigned long timeout;
|
||||
|
||||
u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
|
||||
u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
|
||||
|
||||
DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
|
||||
|
||||
|
@ -317,7 +317,7 @@ static int sm_write_bank(int bank, u8* datas)
|
|||
int i, stat = 0;
|
||||
unsigned long timeout;
|
||||
|
||||
u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
|
||||
u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
|
||||
|
||||
DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
|
||||
|
||||
|
@ -352,7 +352,7 @@ static int amd_erase_bank(int bank)
|
|||
int i, stat = 0;
|
||||
unsigned long timeout;
|
||||
|
||||
u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
|
||||
u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
|
||||
|
||||
DBG("nvram: AMD Erasing bank %d...\n", bank);
|
||||
|
||||
|
@ -399,7 +399,7 @@ static int amd_write_bank(int bank, u8* datas)
|
|||
int i, stat = 0;
|
||||
unsigned long timeout;
|
||||
|
||||
u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
|
||||
u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
|
||||
|
||||
DBG("nvram: AMD Writing bank %d...\n", bank);
|
||||
|
||||
|
|
|
@ -116,7 +116,7 @@ void udbg_scc_init(int force_scc)
|
|||
/* Setup for 57600 8N1 */
|
||||
if (ch == ch_a)
|
||||
addr += 0x20;
|
||||
sccc = (volatile u8 * __iomem) ioremap(addr & PAGE_MASK, PAGE_SIZE) ;
|
||||
sccc = ioremap(addr & PAGE_MASK, PAGE_SIZE) ;
|
||||
sccc += addr & ~PAGE_MASK;
|
||||
sccd = sccc + 0x10;
|
||||
|
||||
|
|
Загрузка…
Ссылка в новой задаче