[media] MFC: Add MFC 5.1 V4L2 driver
Multi Format Codec 5.1 is a hardware video coding acceleration module found in the S5PV210 and Exynos4 Samsung SoCs. It is capable of handling a range of video codecs and this driver provides a V4L2 interface for video decoding and encoding. Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Jeongtae Park <jtp.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Kamil Debski
Mauro Carvalho Chehab
Родитель
c53f9f00e5
Коммит
af93574678
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@ -1066,4 +1066,12 @@ config VIDEO_MEM2MEM_TESTDEV
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framework.
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config VIDEO_SAMSUNG_S5P_MFC
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tristate "Samsung S5P MFC 5.1 Video Codec"
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depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
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select VIDEOBUF2_DMA_CONTIG
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default n
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help
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MFC 5.1 driver for V4L2.
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endif # V4L_MEM2MEM_DRIVERS
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@ -171,6 +171,7 @@ obj-$(CONFIG_VIDEO_OMAP1) += omap1_camera.o
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obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc/
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) += s5p-mfc/
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obj-$(CONFIG_ARCH_DAVINCI) += davinci/
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@ -0,0 +1,5 @@
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) := s5p-mfc.o
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s5p-mfc-y += s5p_mfc.o s5p_mfc_intr.o s5p_mfc_opr.o
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s5p-mfc-y += s5p_mfc_dec.o s5p_mfc_enc.o
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s5p-mfc-y += s5p_mfc_ctrl.o s5p_mfc_cmd.o
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s5p-mfc-y += s5p_mfc_pm.o s5p_mfc_shm.o
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@ -0,0 +1,413 @@
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/*
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* Register definition file for Samsung MFC V5.1 Interface (FIMV) driver
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*
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* Kamil Debski, Copyright (c) 2010 Samsung Electronics
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _REGS_FIMV_H
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#define _REGS_FIMV_H
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#define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
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#define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
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/* Number of bits that the buffer address should be shifted for particular
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* MFC buffers. */
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#define S5P_FIMV_START_ADDR 0x0000
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#define S5P_FIMV_END_ADDR 0xe008
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#define S5P_FIMV_SW_RESET 0x0000
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#define S5P_FIMV_RISC_HOST_INT 0x0008
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/* Command from HOST to RISC */
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#define S5P_FIMV_HOST2RISC_CMD 0x0030
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#define S5P_FIMV_HOST2RISC_ARG1 0x0034
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#define S5P_FIMV_HOST2RISC_ARG2 0x0038
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#define S5P_FIMV_HOST2RISC_ARG3 0x003c
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#define S5P_FIMV_HOST2RISC_ARG4 0x0040
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/* Command from RISC to HOST */
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#define S5P_FIMV_RISC2HOST_CMD 0x0044
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#define S5P_FIMV_RISC2HOST_CMD_MASK 0x1FFFF
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#define S5P_FIMV_RISC2HOST_ARG1 0x0048
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#define S5P_FIMV_RISC2HOST_ARG2 0x004c
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#define S5P_FIMV_RISC2HOST_ARG3 0x0050
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#define S5P_FIMV_RISC2HOST_ARG4 0x0054
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#define S5P_FIMV_FW_VERSION 0x0058
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#define S5P_FIMV_SYS_MEM_SZ 0x005c
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#define S5P_FIMV_FW_STATUS 0x0080
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/* Memory controller register */
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#define S5P_FIMV_MC_DRAMBASE_ADR_A 0x0508
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#define S5P_FIMV_MC_DRAMBASE_ADR_B 0x050c
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#define S5P_FIMV_MC_STATUS 0x0510
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/* Common register */
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#define S5P_FIMV_COMMON_BASE_A 0x0600
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#define S5P_FIMV_COMMON_BASE_B 0x0700
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/* Decoder */
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#define S5P_FIMV_DEC_CHROMA_ADR (S5P_FIMV_COMMON_BASE_A)
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#define S5P_FIMV_DEC_LUMA_ADR (S5P_FIMV_COMMON_BASE_B)
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/* H.264 decoding */
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#define S5P_FIMV_H264_VERT_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
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/* vertical neighbor motion vector */
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#define S5P_FIMV_H264_NB_IP_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
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/* neighbor pixels for intra pred */
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#define S5P_FIMV_H264_MV_ADR (S5P_FIMV_COMMON_BASE_B + 0x80)
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/* H264 motion vector */
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/* MPEG4 decoding */
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#define S5P_FIMV_MPEG4_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
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/* neighbor AC/DC coeff. */
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#define S5P_FIMV_MPEG4_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
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/* upper neighbor motion vector */
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#define S5P_FIMV_MPEG4_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
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/* subseq. anchor motion vector */
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#define S5P_FIMV_MPEG4_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
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/* overlap transform line */
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#define S5P_FIMV_MPEG4_SP_ADR (S5P_FIMV_COMMON_BASE_A + 0xa8)
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/* syntax parser */
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/* H.263 decoding */
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#define S5P_FIMV_H263_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
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#define S5P_FIMV_H263_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
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#define S5P_FIMV_H263_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
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#define S5P_FIMV_H263_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
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/* VC-1 decoding */
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#define S5P_FIMV_VC1_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)
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#define S5P_FIMV_VC1_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)
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#define S5P_FIMV_VC1_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)
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#define S5P_FIMV_VC1_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)
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#define S5P_FIMV_VC1_BITPLANE3_ADR (S5P_FIMV_COMMON_BASE_A + 0x9c)
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/* bitplane3 */
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#define S5P_FIMV_VC1_BITPLANE2_ADR (S5P_FIMV_COMMON_BASE_A + 0xa0)
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/* bitplane2 */
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#define S5P_FIMV_VC1_BITPLANE1_ADR (S5P_FIMV_COMMON_BASE_A + 0xa4)
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/* bitplane1 */
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/* Encoder */
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#define S5P_FIMV_ENC_REF0_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x1c)
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#define S5P_FIMV_ENC_REF1_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x20)
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/* reconstructed luma */
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#define S5P_FIMV_ENC_REF0_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B)
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#define S5P_FIMV_ENC_REF1_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x04)
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/* reconstructed chroma */
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#define S5P_FIMV_ENC_REF2_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x10)
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#define S5P_FIMV_ENC_REF2_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x08)
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#define S5P_FIMV_ENC_REF3_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x14)
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#define S5P_FIMV_ENC_REF3_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x0c)
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/* H.264 encoding */
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#define S5P_FIMV_H264_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)
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/* upper motion vector */
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#define S5P_FIMV_H264_NBOR_INFO_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
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/* entropy engine's neighbor info. */
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#define S5P_FIMV_H264_UP_INTRA_MD_ADR (S5P_FIMV_COMMON_BASE_A + 0x08)
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/* upper intra MD */
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#define S5P_FIMV_H264_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)
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/* direct cozero flag */
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#define S5P_FIMV_H264_UP_INTRA_PRED_ADR (S5P_FIMV_COMMON_BASE_B + 0x40)
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/* upper intra PRED */
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/* H.263 encoding */
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#define S5P_FIMV_H263_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)
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/* upper motion vector */
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#define S5P_FIMV_H263_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
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/* upper Q coeff. */
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/* MPEG4 encoding */
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#define S5P_FIMV_MPEG4_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)
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/* upper motion vector */
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#define S5P_FIMV_MPEG4_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)
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/* upper Q coeff. */
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#define S5P_FIMV_MPEG4_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)
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/* direct cozero flag */
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#define S5P_FIMV_ENC_REF_B_LUMA_ADR 0x062c /* ref B Luma addr */
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#define S5P_FIMV_ENC_REF_B_CHROMA_ADR 0x0630 /* ref B Chroma addr */
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#define S5P_FIMV_ENC_CUR_LUMA_ADR 0x0718 /* current Luma addr */
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#define S5P_FIMV_ENC_CUR_CHROMA_ADR 0x071C /* current Chroma addr */
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/* Codec common register */
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#define S5P_FIMV_ENC_HSIZE_PX 0x0818 /* frame width at encoder */
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#define S5P_FIMV_ENC_VSIZE_PX 0x081c /* frame height at encoder */
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#define S5P_FIMV_ENC_PROFILE 0x0830 /* profile register */
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#define S5P_FIMV_ENC_PROFILE_H264_MAIN 0
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#define S5P_FIMV_ENC_PROFILE_H264_HIGH 1
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#define S5P_FIMV_ENC_PROFILE_H264_BASELINE 2
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#define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE 0
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#define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE 1
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#define S5P_FIMV_ENC_PIC_STRUCT 0x083c /* picture field/frame flag */
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#define S5P_FIMV_ENC_LF_CTRL 0x0848 /* loop filter control */
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#define S5P_FIMV_ENC_ALPHA_OFF 0x084c /* loop filter alpha offset */
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#define S5P_FIMV_ENC_BETA_OFF 0x0850 /* loop filter beta offset */
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#define S5P_FIMV_MR_BUSIF_CTRL 0x0854 /* hidden, bus interface ctrl */
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#define S5P_FIMV_ENC_PXL_CACHE_CTRL 0x0a00 /* pixel cache control */
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/* Channel & stream interface register */
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#define S5P_FIMV_SI_RTN_CHID 0x2000 /* Return CH inst ID register */
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#define S5P_FIMV_SI_CH0_INST_ID 0x2040 /* codec instance ID */
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#define S5P_FIMV_SI_CH1_INST_ID 0x2080 /* codec instance ID */
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/* Decoder */
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#define S5P_FIMV_SI_VRESOL 0x2004 /* vertical res of decoder */
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#define S5P_FIMV_SI_HRESOL 0x2008 /* horizontal res of decoder */
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#define S5P_FIMV_SI_BUF_NUMBER 0x200c /* number of frames in the
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decoded pic */
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#define S5P_FIMV_SI_DISPLAY_Y_ADR 0x2010 /* luma addr of displayed pic */
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#define S5P_FIMV_SI_DISPLAY_C_ADR 0x2014 /* chroma addrof displayed pic */
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#define S5P_FIMV_SI_CONSUMED_BYTES 0x2018 /* Consumed number of bytes to
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decode a frame */
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#define S5P_FIMV_SI_DISPLAY_STATUS 0x201c /* status of decoded picture */
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#define S5P_FIMV_SI_CH0_SB_ST_ADR 0x2044 /* start addr of stream buf */
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#define S5P_FIMV_SI_CH0_SB_FRM_SIZE 0x2048 /* size of stream buf */
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#define S5P_FIMV_SI_CH0_DESC_ADR 0x204c /* addr of descriptor buf */
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#define S5P_FIMV_SI_CH0_CPB_SIZE 0x2058 /* max size of coded pic. buf */
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#define S5P_FIMV_SI_CH0_DESC_SIZE 0x205c /* max size of descriptor buf */
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#define S5P_FIMV_SI_CH1_SB_ST_ADR 0x2084 /* start addr of stream buf */
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#define S5P_FIMV_SI_CH1_SB_FRM_SIZE 0x2088 /* size of stream buf */
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#define S5P_FIMV_SI_CH1_DESC_ADR 0x208c /* addr of descriptor buf */
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#define S5P_FIMV_SI_CH1_CPB_SIZE 0x2098 /* max size of coded pic. buf */
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#define S5P_FIMV_SI_CH1_DESC_SIZE 0x209c /* max size of descriptor buf */
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#define S5P_FIMV_CRC_LUMA0 0x2030 /* luma crc data per frame
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(top field) */
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#define S5P_FIMV_CRC_CHROMA0 0x2034 /* chroma crc data per frame
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(top field) */
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#define S5P_FIMV_CRC_LUMA1 0x2038 /* luma crc data per bottom
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field */
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#define S5P_FIMV_CRC_CHROMA1 0x203c /* chroma crc data per bottom
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field */
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/* Display status */
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#define S5P_FIMV_DEC_STATUS_DECODING_ONLY 0
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#define S5P_FIMV_DEC_STATUS_DECODING_DISPLAY 1
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#define S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 2
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#define S5P_FIMV_DEC_STATUS_DECODING_EMPTY 3
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#define S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK 7
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#define S5P_FIMV_DEC_STATUS_PROGRESSIVE (0<<3)
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#define S5P_FIMV_DEC_STATUS_INTERLACE (1<<3)
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#define S5P_FIMV_DEC_STATUS_INTERLACE_MASK (1<<3)
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#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_TWO (0<<4)
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#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_FOUR (1<<4)
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#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_MASK (1<<4)
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#define S5P_FIMV_DEC_STATUS_CRC_GENERATED (1<<5)
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#define S5P_FIMV_DEC_STATUS_CRC_NOT_GENERATED (0<<5)
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#define S5P_FIMV_DEC_STATUS_CRC_MASK (1<<5)
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#define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK (3<<4)
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#define S5P_FIMV_DEC_STATUS_RESOLUTION_INC (1<<4)
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#define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC (2<<4)
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/* Decode frame address */
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#define S5P_FIMV_DECODE_Y_ADR 0x2024
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#define S5P_FIMV_DECODE_C_ADR 0x2028
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/* Decoded frame tpe */
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#define S5P_FIMV_DECODE_FRAME_TYPE 0x2020
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#define S5P_FIMV_DECODE_FRAME_MASK 7
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#define S5P_FIMV_DECODE_FRAME_SKIPPED 0
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#define S5P_FIMV_DECODE_FRAME_I_FRAME 1
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#define S5P_FIMV_DECODE_FRAME_P_FRAME 2
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#define S5P_FIMV_DECODE_FRAME_B_FRAME 3
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#define S5P_FIMV_DECODE_FRAME_OTHER_FRAME 4
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/* Sizes of buffers required for decoding */
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#define S5P_FIMV_DEC_NB_IP_SIZE (32 * 1024)
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#define S5P_FIMV_DEC_VERT_NB_MV_SIZE (16 * 1024)
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#define S5P_FIMV_DEC_NB_DCAC_SIZE (16 * 1024)
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#define S5P_FIMV_DEC_UPNB_MV_SIZE (68 * 1024)
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#define S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE (136 * 1024)
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#define S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE (32 * 1024)
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#define S5P_FIMV_DEC_VC1_BITPLANE_SIZE (2 * 1024)
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#define S5P_FIMV_DEC_STX_PARSER_SIZE (68 * 1024)
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#define S5P_FIMV_DEC_BUF_ALIGN (8 * 1024)
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#define S5P_FIMV_ENC_BUF_ALIGN (8 * 1024)
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#define S5P_FIMV_NV12M_HALIGN 16
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#define S5P_FIMV_NV12M_LVALIGN 16
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#define S5P_FIMV_NV12M_CVALIGN 8
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#define S5P_FIMV_NV12MT_HALIGN 128
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#define S5P_FIMV_NV12MT_VALIGN 32
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#define S5P_FIMV_NV12M_SALIGN 2048
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#define S5P_FIMV_NV12MT_SALIGN 8192
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/* Sizes of buffers required for encoding */
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#define S5P_FIMV_ENC_UPMV_SIZE 0x10000
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#define S5P_FIMV_ENC_COLFLG_SIZE 0x10000
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#define S5P_FIMV_ENC_INTRAMD_SIZE 0x10000
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#define S5P_FIMV_ENC_INTRAPRED_SIZE 0x4000
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#define S5P_FIMV_ENC_NBORINFO_SIZE 0x10000
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#define S5P_FIMV_ENC_ACDCCOEF_SIZE 0x10000
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/* Encoder */
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#define S5P_FIMV_ENC_SI_STRM_SIZE 0x2004 /* stream size */
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#define S5P_FIMV_ENC_SI_PIC_CNT 0x2008 /* picture count */
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#define S5P_FIMV_ENC_SI_WRITE_PTR 0x200c /* write pointer */
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#define S5P_FIMV_ENC_SI_SLICE_TYPE 0x2010 /* slice type(I/P/B/IDR) */
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_NON_CODED 0
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_I 1
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_P 2
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_B 3
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_SKIPPED 4
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#define S5P_FIMV_ENC_SI_SLICE_TYPE_OTHERS 5
|
||||
#define S5P_FIMV_ENCODED_Y_ADDR 0x2014 /* the addr of the encoded
|
||||
luma pic */
|
||||
#define S5P_FIMV_ENCODED_C_ADDR 0x2018 /* the addr of the encoded
|
||||
chroma pic */
|
||||
|
||||
#define S5P_FIMV_ENC_SI_CH0_SB_ADR 0x2044 /* addr of stream buf */
|
||||
#define S5P_FIMV_ENC_SI_CH0_SB_SIZE 0x204c /* size of stream buf */
|
||||
#define S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR 0x2050 /* current Luma addr */
|
||||
#define S5P_FIMV_ENC_SI_CH0_CUR_C_ADR 0x2054 /* current Chroma addr */
|
||||
#define S5P_FIMV_ENC_SI_CH0_FRAME_INS 0x2058 /* frame insertion */
|
||||
|
||||
#define S5P_FIMV_ENC_SI_CH1_SB_ADR 0x2084 /* addr of stream buf */
|
||||
#define S5P_FIMV_ENC_SI_CH1_SB_SIZE 0x208c /* size of stream buf */
|
||||
#define S5P_FIMV_ENC_SI_CH1_CUR_Y_ADR 0x2090 /* current Luma addr */
|
||||
#define S5P_FIMV_ENC_SI_CH1_CUR_C_ADR 0x2094 /* current Chroma addr */
|
||||
#define S5P_FIMV_ENC_SI_CH1_FRAME_INS 0x2098 /* frame insertion */
|
||||
|
||||
#define S5P_FIMV_ENC_PIC_TYPE_CTRL 0xc504 /* pic type level control */
|
||||
#define S5P_FIMV_ENC_B_RECON_WRITE_ON 0xc508 /* B frame recon write ctrl */
|
||||
#define S5P_FIMV_ENC_MSLICE_CTRL 0xc50c /* multi slice control */
|
||||
#define S5P_FIMV_ENC_MSLICE_MB 0xc510 /* MB number in the one slice */
|
||||
#define S5P_FIMV_ENC_MSLICE_BIT 0xc514 /* bit count for one slice */
|
||||
#define S5P_FIMV_ENC_CIR_CTRL 0xc518 /* number of intra refresh MB */
|
||||
#define S5P_FIMV_ENC_MAP_FOR_CUR 0xc51c /* linear or tiled mode */
|
||||
#define S5P_FIMV_ENC_PADDING_CTRL 0xc520 /* padding control */
|
||||
|
||||
#define S5P_FIMV_ENC_RC_CONFIG 0xc5a0 /* RC config */
|
||||
#define S5P_FIMV_ENC_RC_BIT_RATE 0xc5a8 /* bit rate */
|
||||
#define S5P_FIMV_ENC_RC_QBOUND 0xc5ac /* max/min QP */
|
||||
#define S5P_FIMV_ENC_RC_RPARA 0xc5b0 /* rate control reaction coeff */
|
||||
#define S5P_FIMV_ENC_RC_MB_CTRL 0xc5b4 /* MB adaptive scaling */
|
||||
|
||||
/* Encoder for H264 only */
|
||||
#define S5P_FIMV_ENC_H264_ENTROPY_MODE 0xd004 /* CAVLC or CABAC */
|
||||
#define S5P_FIMV_ENC_H264_ALPHA_OFF 0xd008 /* loop filter alpha offset */
|
||||
#define S5P_FIMV_ENC_H264_BETA_OFF 0xd00c /* loop filter beta offset */
|
||||
#define S5P_FIMV_ENC_H264_NUM_OF_REF 0xd010 /* number of reference for P/B */
|
||||
#define S5P_FIMV_ENC_H264_TRANS_FLAG 0xd034 /* 8x8 transform flag in PPS &
|
||||
high profile */
|
||||
|
||||
#define S5P_FIMV_ENC_RC_FRAME_RATE 0xd0d0 /* frame rate */
|
||||
|
||||
/* Encoder for MPEG4 only */
|
||||
#define S5P_FIMV_ENC_MPEG4_QUART_PXL 0xe008 /* qpel interpolation ctrl */
|
||||
|
||||
/* Additional */
|
||||
#define S5P_FIMV_SI_CH0_DPB_CONF_CTRL 0x2068 /* DPB Config Control Register */
|
||||
#define S5P_FIMV_SLICE_INT_MASK 1
|
||||
#define S5P_FIMV_SLICE_INT_SHIFT 31
|
||||
#define S5P_FIMV_DDELAY_ENA_SHIFT 30
|
||||
#define S5P_FIMV_DDELAY_VAL_MASK 0xff
|
||||
#define S5P_FIMV_DDELAY_VAL_SHIFT 16
|
||||
#define S5P_FIMV_DPB_COUNT_MASK 0xffff
|
||||
#define S5P_FIMV_DPB_FLUSH_MASK 1
|
||||
#define S5P_FIMV_DPB_FLUSH_SHIFT 14
|
||||
|
||||
|
||||
#define S5P_FIMV_SI_CH0_RELEASE_BUF 0x2060 /* DPB release buffer register */
|
||||
#define S5P_FIMV_SI_CH0_HOST_WR_ADR 0x2064 /* address of shared memory */
|
||||
|
||||
/* Codec numbers */
|
||||
#define S5P_FIMV_CODEC_NONE -1
|
||||
|
||||
#define S5P_FIMV_CODEC_H264_DEC 0
|
||||
#define S5P_FIMV_CODEC_VC1_DEC 1
|
||||
#define S5P_FIMV_CODEC_MPEG4_DEC 2
|
||||
#define S5P_FIMV_CODEC_MPEG2_DEC 3
|
||||
#define S5P_FIMV_CODEC_H263_DEC 4
|
||||
#define S5P_FIMV_CODEC_VC1RCV_DEC 5
|
||||
|
||||
#define S5P_FIMV_CODEC_H264_ENC 16
|
||||
#define S5P_FIMV_CODEC_MPEG4_ENC 17
|
||||
#define S5P_FIMV_CODEC_H263_ENC 18
|
||||
|
||||
/* Channel Control Register */
|
||||
#define S5P_FIMV_CH_SEQ_HEADER 1
|
||||
#define S5P_FIMV_CH_FRAME_START 2
|
||||
#define S5P_FIMV_CH_LAST_FRAME 3
|
||||
#define S5P_FIMV_CH_INIT_BUFS 4
|
||||
#define S5P_FIMV_CH_FRAME_START_REALLOC 5
|
||||
#define S5P_FIMV_CH_MASK 7
|
||||
#define S5P_FIMV_CH_SHIFT 16
|
||||
|
||||
|
||||
/* Host to RISC command */
|
||||
#define S5P_FIMV_H2R_CMD_EMPTY 0
|
||||
#define S5P_FIMV_H2R_CMD_OPEN_INSTANCE 1
|
||||
#define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE 2
|
||||
#define S5P_FIMV_H2R_CMD_SYS_INIT 3
|
||||
#define S5P_FIMV_H2R_CMD_FLUSH 4
|
||||
#define S5P_FIMV_H2R_CMD_SLEEP 5
|
||||
#define S5P_FIMV_H2R_CMD_WAKEUP 6
|
||||
|
||||
#define S5P_FIMV_R2H_CMD_EMPTY 0
|
||||
#define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET 1
|
||||
#define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET 2
|
||||
#define S5P_FIMV_R2H_CMD_RSV_RET 3
|
||||
#define S5P_FIMV_R2H_CMD_SEQ_DONE_RET 4
|
||||
#define S5P_FIMV_R2H_CMD_FRAME_DONE_RET 5
|
||||
#define S5P_FIMV_R2H_CMD_SLICE_DONE_RET 6
|
||||
#define S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET 7
|
||||
#define S5P_FIMV_R2H_CMD_SYS_INIT_RET 8
|
||||
#define S5P_FIMV_R2H_CMD_FW_STATUS_RET 9
|
||||
#define S5P_FIMV_R2H_CMD_SLEEP_RET 10
|
||||
#define S5P_FIMV_R2H_CMD_WAKEUP_RET 11
|
||||
#define S5P_FIMV_R2H_CMD_FLUSH_RET 12
|
||||
#define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET 15
|
||||
#define S5P_FIMV_R2H_CMD_EDFU_INIT_RET 16
|
||||
#define S5P_FIMV_R2H_CMD_ERR_RET 32
|
||||
|
||||
/* Error handling defines */
|
||||
#define S5P_FIMV_ERR_WARNINGS_START 145
|
||||
#define S5P_FIMV_ERR_DEC_MASK 0xFFFF
|
||||
#define S5P_FIMV_ERR_DEC_SHIFT 0
|
||||
#define S5P_FIMV_ERR_DSPL_MASK 0xFFFF0000
|
||||
#define S5P_FIMV_ERR_DSPL_SHIFT 16
|
||||
|
||||
/* Shared memory registers' offsets */
|
||||
|
||||
/* An offset of the start position in the stream when
|
||||
* the start position is not aligned */
|
||||
#define S5P_FIMV_SHARED_CROP_INFO_H 0x0020
|
||||
#define S5P_FIMV_SHARED_CROP_LEFT_MASK 0xFFFF
|
||||
#define S5P_FIMV_SHARED_CROP_LEFT_SHIFT 0
|
||||
#define S5P_FIMV_SHARED_CROP_RIGHT_MASK 0xFFFF0000
|
||||
#define S5P_FIMV_SHARED_CROP_RIGHT_SHIFT 16
|
||||
#define S5P_FIMV_SHARED_CROP_INFO_V 0x0024
|
||||
#define S5P_FIMV_SHARED_CROP_TOP_MASK 0xFFFF
|
||||
#define S5P_FIMV_SHARED_CROP_TOP_SHIFT 0
|
||||
#define S5P_FIMV_SHARED_CROP_BOTTOM_MASK 0xFFFF0000
|
||||
#define S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT 16
|
||||
#define S5P_FIMV_SHARED_SET_FRAME_TAG 0x0004
|
||||
#define S5P_FIMV_SHARED_GET_FRAME_TAG_TOP 0x0008
|
||||
#define S5P_FIMV_SHARED_GET_FRAME_TAG_BOT 0x000C
|
||||
#define S5P_FIMV_SHARED_START_BYTE_NUM 0x0018
|
||||
#define S5P_FIMV_SHARED_RC_VOP_TIMING 0x0030
|
||||
#define S5P_FIMV_SHARED_LUMA_DPB_SIZE 0x0064
|
||||
#define S5P_FIMV_SHARED_CHROMA_DPB_SIZE 0x0068
|
||||
#define S5P_FIMV_SHARED_MV_SIZE 0x006C
|
||||
#define S5P_FIMV_SHARED_PIC_TIME_TOP 0x0010
|
||||
#define S5P_FIMV_SHARED_PIC_TIME_BOTTOM 0x0014
|
||||
#define S5P_FIMV_SHARED_EXT_ENC_CONTROL 0x0028
|
||||
#define S5P_FIMV_SHARED_P_B_FRAME_QP 0x0070
|
||||
#define S5P_FIMV_SHARED_ASPECT_RATIO_IDC 0x0074
|
||||
#define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078
|
||||
#define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C
|
||||
#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0
|
||||
|
||||
#endif /* _REGS_FIMV_H */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_cmd.c
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include "regs-mfc.h"
|
||||
#include "s5p_mfc_cmd.h"
|
||||
#include "s5p_mfc_common.h"
|
||||
#include "s5p_mfc_debug.h"
|
||||
|
||||
/* This function is used to send a command to the MFC */
|
||||
static int s5p_mfc_cmd_host2risc(struct s5p_mfc_dev *dev, int cmd,
|
||||
struct s5p_mfc_cmd_args *args)
|
||||
{
|
||||
int cur_cmd;
|
||||
unsigned long timeout;
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
|
||||
/* wait until host to risc command register becomes 'H2R_CMD_EMPTY' */
|
||||
do {
|
||||
if (time_after(jiffies, timeout)) {
|
||||
mfc_err("Timeout while waiting for hardware\n");
|
||||
return -EIO;
|
||||
}
|
||||
cur_cmd = mfc_read(dev, S5P_FIMV_HOST2RISC_CMD);
|
||||
} while (cur_cmd != S5P_FIMV_H2R_CMD_EMPTY);
|
||||
mfc_write(dev, args->arg[0], S5P_FIMV_HOST2RISC_ARG1);
|
||||
mfc_write(dev, args->arg[1], S5P_FIMV_HOST2RISC_ARG2);
|
||||
mfc_write(dev, args->arg[2], S5P_FIMV_HOST2RISC_ARG3);
|
||||
mfc_write(dev, args->arg[3], S5P_FIMV_HOST2RISC_ARG4);
|
||||
/* Issue the command */
|
||||
mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Initialize the MFC */
|
||||
int s5p_mfc_sys_init_cmd(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
struct s5p_mfc_cmd_args h2r_args;
|
||||
|
||||
memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
|
||||
h2r_args.arg[0] = dev->fw_size;
|
||||
return s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_SYS_INIT, &h2r_args);
|
||||
}
|
||||
|
||||
/* Suspend the MFC hardware */
|
||||
int s5p_mfc_sleep_cmd(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
struct s5p_mfc_cmd_args h2r_args;
|
||||
|
||||
memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
|
||||
return s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_SLEEP, &h2r_args);
|
||||
}
|
||||
|
||||
/* Wake up the MFC hardware */
|
||||
int s5p_mfc_wakeup_cmd(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
struct s5p_mfc_cmd_args h2r_args;
|
||||
|
||||
memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
|
||||
return s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_WAKEUP, &h2r_args);
|
||||
}
|
||||
|
||||
|
||||
int s5p_mfc_open_inst_cmd(struct s5p_mfc_ctx *ctx)
|
||||
{
|
||||
struct s5p_mfc_dev *dev = ctx->dev;
|
||||
struct s5p_mfc_cmd_args h2r_args;
|
||||
int ret;
|
||||
|
||||
/* Preparing decoding - getting instance number */
|
||||
mfc_debug(2, "Getting instance number (codec: %d)\n", ctx->codec_mode);
|
||||
dev->curr_ctx = ctx->num;
|
||||
memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
|
||||
h2r_args.arg[0] = ctx->codec_mode;
|
||||
h2r_args.arg[1] = 0; /* no crc & no pixelcache */
|
||||
h2r_args.arg[2] = ctx->ctx_ofs;
|
||||
h2r_args.arg[3] = ctx->ctx_size;
|
||||
ret = s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE,
|
||||
&h2r_args);
|
||||
if (ret) {
|
||||
mfc_err("Failed to create a new instance\n");
|
||||
ctx->state = MFCINST_ERROR;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int s5p_mfc_close_inst_cmd(struct s5p_mfc_ctx *ctx)
|
||||
{
|
||||
struct s5p_mfc_dev *dev = ctx->dev;
|
||||
struct s5p_mfc_cmd_args h2r_args;
|
||||
int ret;
|
||||
|
||||
if (ctx->state == MFCINST_FREE) {
|
||||
mfc_err("Instance already returned\n");
|
||||
ctx->state = MFCINST_ERROR;
|
||||
return -EINVAL;
|
||||
}
|
||||
/* Closing decoding instance */
|
||||
mfc_debug(2, "Returning instance number %d\n", ctx->inst_no);
|
||||
dev->curr_ctx = ctx->num;
|
||||
memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
|
||||
h2r_args.arg[0] = ctx->inst_no;
|
||||
ret = s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_CLOSE_INSTANCE,
|
||||
&h2r_args);
|
||||
if (ret) {
|
||||
mfc_err("Failed to return an instance\n");
|
||||
ctx->state = MFCINST_ERROR;
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_cmd.h
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_CMD_H_
|
||||
#define S5P_MFC_CMD_H_
|
||||
|
||||
#include "s5p_mfc_common.h"
|
||||
|
||||
#define MAX_H2R_ARG 4
|
||||
|
||||
struct s5p_mfc_cmd_args {
|
||||
unsigned int arg[MAX_H2R_ARG];
|
||||
};
|
||||
|
||||
int s5p_mfc_sys_init_cmd(struct s5p_mfc_dev *dev);
|
||||
int s5p_mfc_sleep_cmd(struct s5p_mfc_dev *dev);
|
||||
int s5p_mfc_wakeup_cmd(struct s5p_mfc_dev *dev);
|
||||
int s5p_mfc_open_inst_cmd(struct s5p_mfc_ctx *ctx);
|
||||
int s5p_mfc_close_inst_cmd(struct s5p_mfc_ctx *ctx);
|
||||
|
||||
#endif /* S5P_MFC_CMD_H_ */
|
||||
|
|
@ -0,0 +1,572 @@
|
|||
/*
|
||||
* Samsung S5P Multi Format Codec v 5.0
|
||||
*
|
||||
* This file contains definitions of enums and structs used by the codec
|
||||
* driver.
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
* Kamil Debski, <k.debski@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_COMMON_H_
|
||||
#define S5P_MFC_COMMON_H_
|
||||
|
||||
#include "regs-mfc.h"
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/videodev2.h>
|
||||
#include <media/v4l2-ctrls.h>
|
||||
#include <media/v4l2-device.h>
|
||||
#include <media/v4l2-ioctl.h>
|
||||
#include <media/videobuf2-core.h>
|
||||
|
||||
/* Definitions related to MFC memory */
|
||||
|
||||
/* Offset base used to differentiate between CAPTURE and OUTPUT
|
||||
* while mmaping */
|
||||
#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
|
||||
|
||||
/* Offset used by the hardware to store addresses */
|
||||
#define MFC_OFFSET_SHIFT 11
|
||||
|
||||
#define FIRMWARE_ALIGN 0x20000 /* 128KB */
|
||||
#define MFC_H264_CTX_BUF_SIZE 0x96000 /* 600KB per H264 instance */
|
||||
#define MFC_CTX_BUF_SIZE 0x2800 /* 10KB per instance */
|
||||
#define DESC_BUF_SIZE 0x20000 /* 128KB for DESC buffer */
|
||||
#define SHARED_BUF_SIZE 0x2000 /* 8KB for shared buffer */
|
||||
|
||||
#define DEF_CPB_SIZE 0x40000 /* 512KB */
|
||||
|
||||
#define MFC_BANK1_ALLOC_CTX 0
|
||||
#define MFC_BANK2_ALLOC_CTX 1
|
||||
|
||||
#define MFC_BANK1_ALIGN_ORDER 13
|
||||
#define MFC_BANK2_ALIGN_ORDER 13
|
||||
#define MFC_BASE_ALIGN_ORDER 17
|
||||
|
||||
#include <media/videobuf2-dma-contig.h>
|
||||
|
||||
static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
|
||||
{
|
||||
/* Same functionality as the vb2_dma_contig_plane_paddr */
|
||||
dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
|
||||
|
||||
return *paddr;
|
||||
}
|
||||
|
||||
/* MFC definitions */
|
||||
#define MFC_MAX_EXTRA_DPB 5
|
||||
#define MFC_MAX_BUFFERS 32
|
||||
#define MFC_NUM_CONTEXTS 4
|
||||
/* Interrupt timeout */
|
||||
#define MFC_INT_TIMEOUT 2000
|
||||
/* Busy wait timeout */
|
||||
#define MFC_BW_TIMEOUT 500
|
||||
/* Watchdog interval */
|
||||
#define MFC_WATCHDOG_INTERVAL 1000
|
||||
/* After how many executions watchdog should assume lock up */
|
||||
#define MFC_WATCHDOG_CNT 10
|
||||
#define MFC_NO_INSTANCE_SET -1
|
||||
#define MFC_ENC_CAP_PLANE_COUNT 1
|
||||
#define MFC_ENC_OUT_PLANE_COUNT 2
|
||||
#define STUFF_BYTE 4
|
||||
#define MFC_MAX_CTRLS 64
|
||||
|
||||
#define mfc_read(dev, offset) readl(dev->regs_base + (offset))
|
||||
#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
|
||||
(offset))
|
||||
|
||||
/**
|
||||
* enum s5p_mfc_fmt_type - type of the pixelformat
|
||||
*/
|
||||
enum s5p_mfc_fmt_type {
|
||||
MFC_FMT_DEC,
|
||||
MFC_FMT_ENC,
|
||||
MFC_FMT_RAW,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum s5p_mfc_node_type - The type of an MFC device node.
|
||||
*/
|
||||
enum s5p_mfc_node_type {
|
||||
MFCNODE_INVALID = -1,
|
||||
MFCNODE_DECODER = 0,
|
||||
MFCNODE_ENCODER = 1,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum s5p_mfc_inst_type - The type of an MFC instance.
|
||||
*/
|
||||
enum s5p_mfc_inst_type {
|
||||
MFCINST_INVALID,
|
||||
MFCINST_DECODER,
|
||||
MFCINST_ENCODER,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum s5p_mfc_inst_state - The state of an MFC instance.
|
||||
*/
|
||||
enum s5p_mfc_inst_state {
|
||||
MFCINST_FREE = 0,
|
||||
MFCINST_INIT = 100,
|
||||
MFCINST_GOT_INST,
|
||||
MFCINST_HEAD_PARSED,
|
||||
MFCINST_BUFS_SET,
|
||||
MFCINST_RUNNING,
|
||||
MFCINST_FINISHING,
|
||||
MFCINST_FINISHED,
|
||||
MFCINST_RETURN_INST,
|
||||
MFCINST_ERROR,
|
||||
MFCINST_ABORT,
|
||||
MFCINST_RES_CHANGE_INIT,
|
||||
MFCINST_RES_CHANGE_FLUSH,
|
||||
MFCINST_RES_CHANGE_END,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum s5p_mfc_queue_state - The state of buffer queue.
|
||||
*/
|
||||
enum s5p_mfc_queue_state {
|
||||
QUEUE_FREE,
|
||||
QUEUE_BUFS_REQUESTED,
|
||||
QUEUE_BUFS_QUERIED,
|
||||
QUEUE_BUFS_MMAPED,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum s5p_mfc_decode_arg - type of frame decoding
|
||||
*/
|
||||
enum s5p_mfc_decode_arg {
|
||||
MFC_DEC_FRAME,
|
||||
MFC_DEC_LAST_FRAME,
|
||||
MFC_DEC_RES_CHANGE,
|
||||
};
|
||||
|
||||
struct s5p_mfc_ctx;
|
||||
|
||||
/**
|
||||
* struct s5p_mfc_buf - MFC buffer
|
||||
*/
|
||||
struct s5p_mfc_buf {
|
||||
struct list_head list;
|
||||
struct vb2_buffer *b;
|
||||
union {
|
||||
struct {
|
||||
size_t luma;
|
||||
size_t chroma;
|
||||
} raw;
|
||||
size_t stream;
|
||||
} cookie;
|
||||
int used;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s5p_mfc_pm - power management data structure
|
||||
*/
|
||||
struct s5p_mfc_pm {
|
||||
struct clk *clock;
|
||||
struct clk *clock_gate;
|
||||
atomic_t power;
|
||||
struct device *device;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s5p_mfc_dev - The struct containing driver internal parameters.
|
||||
*
|
||||
* @v4l2_dev: v4l2_device
|
||||
* @vfd_dec: video device for decoding
|
||||
* @vfd_enc: video device for encoding
|
||||
* @plat_dev: platform device
|
||||
* @mem_dev_l: child device of the left memory bank (0)
|
||||
* @mem_dev_r: child device of the right memory bank (1)
|
||||
* @regs_base: base address of the MFC hw registers
|
||||
* @irq: irq resource
|
||||
* @mfc_mem: MFC registers memory resource
|
||||
* @dec_ctrl_handler: control framework handler for decoding
|
||||
* @enc_ctrl_handler: control framework handler for encoding
|
||||
* @pm: power management control
|
||||
* @num_inst: couter of active MFC instances
|
||||
* @irqlock: lock for operations on videobuf2 queues
|
||||
* @condlock: lock for changing/checking if a context is ready to be
|
||||
* processed
|
||||
* @mfc_mutex: lock for video_device
|
||||
* @int_cond: variable used by the waitqueue
|
||||
* @int_type: type of last interrupt
|
||||
* @int_err: error number for last interrupt
|
||||
* @queue: waitqueue for waiting for completion of device commands
|
||||
* @fw_size: size of firmware
|
||||
* @bank1: address of the beggining of bank 1 memory
|
||||
* @bank2: address of the beggining of bank 2 memory
|
||||
* @hw_lock: used for hardware locking
|
||||
* @ctx: array of driver contexts
|
||||
* @curr_ctx: number of the currently running context
|
||||
* @ctx_work_bits: used to mark which contexts are waiting for hardware
|
||||
* @watchdog_cnt: counter for the watchdog
|
||||
* @watchdog_workqueue: workqueue for the watchdog
|
||||
* @watchdog_work: worker for the watchdog
|
||||
* @alloc_ctx: videobuf2 allocator contexts for two memory banks
|
||||
* @enter_suspend: flag set when entering suspend
|
||||
*
|
||||
*/
|
||||
struct s5p_mfc_dev {
|
||||
struct v4l2_device v4l2_dev;
|
||||
struct video_device *vfd_dec;
|
||||
struct video_device *vfd_enc;
|
||||
struct platform_device *plat_dev;
|
||||
struct device *mem_dev_l;
|
||||
struct device *mem_dev_r;
|
||||
void __iomem *regs_base;
|
||||
int irq;
|
||||
struct resource *mfc_mem;
|
||||
struct v4l2_ctrl_handler dec_ctrl_handler;
|
||||
struct v4l2_ctrl_handler enc_ctrl_handler;
|
||||
struct s5p_mfc_pm pm;
|
||||
int num_inst;
|
||||
spinlock_t irqlock; /* lock when operating on videobuf2 queues */
|
||||
spinlock_t condlock; /* lock when changing/checking if a context is
|
||||
ready to be processed */
|
||||
struct mutex mfc_mutex; /* video_device lock */
|
||||
int int_cond;
|
||||
int int_type;
|
||||
unsigned int int_err;
|
||||
wait_queue_head_t queue;
|
||||
size_t fw_size;
|
||||
size_t bank1;
|
||||
size_t bank2;
|
||||
unsigned long hw_lock;
|
||||
struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
|
||||
int curr_ctx;
|
||||
unsigned long ctx_work_bits;
|
||||
atomic_t watchdog_cnt;
|
||||
struct timer_list watchdog_timer;
|
||||
struct workqueue_struct *watchdog_workqueue;
|
||||
struct work_struct watchdog_work;
|
||||
void *alloc_ctx[2];
|
||||
unsigned long enter_suspend;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s5p_mfc_h264_enc_params - encoding parameters for h264
|
||||
*/
|
||||
struct s5p_mfc_h264_enc_params {
|
||||
enum v4l2_mpeg_video_h264_profile profile;
|
||||
enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
|
||||
s8 loop_filter_alpha;
|
||||
s8 loop_filter_beta;
|
||||
enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
|
||||
u8 max_ref_pic;
|
||||
u8 num_ref_pic_4p;
|
||||
int _8x8_transform;
|
||||
int rc_mb;
|
||||
int rc_mb_dark;
|
||||
int rc_mb_smooth;
|
||||
int rc_mb_static;
|
||||
int rc_mb_activity;
|
||||
int vui_sar;
|
||||
u8 vui_sar_idc;
|
||||
u16 vui_ext_sar_width;
|
||||
u16 vui_ext_sar_height;
|
||||
int open_gop;
|
||||
u16 open_gop_size;
|
||||
u8 rc_frame_qp;
|
||||
u8 rc_min_qp;
|
||||
u8 rc_max_qp;
|
||||
u8 rc_p_frame_qp;
|
||||
u8 rc_b_frame_qp;
|
||||
enum v4l2_mpeg_video_h264_level level_v4l2;
|
||||
int level;
|
||||
u16 cpb_size;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
|
||||
*/
|
||||
struct s5p_mfc_mpeg4_enc_params {
|
||||
/* MPEG4 Only */
|
||||
enum v4l2_mpeg_video_mpeg4_profile profile;
|
||||
int quarter_pixel;
|
||||
/* Common for MPEG4, H263 */
|
||||
u16 vop_time_res;
|
||||
u16 vop_frm_delta;
|
||||
u8 rc_frame_qp;
|
||||
u8 rc_min_qp;
|
||||
u8 rc_max_qp;
|
||||
u8 rc_p_frame_qp;
|
||||
u8 rc_b_frame_qp;
|
||||
enum v4l2_mpeg_video_mpeg4_level level_v4l2;
|
||||
int level;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s5p_mfc_enc_params - general encoding parameters
|
||||
*/
|
||||
struct s5p_mfc_enc_params {
|
||||
u16 width;
|
||||
u16 height;
|
||||
|
||||
u16 gop_size;
|
||||
enum v4l2_mpeg_video_multi_slice_mode slice_mode;
|
||||
u16 slice_mb;
|
||||
u32 slice_bit;
|
||||
u16 intra_refresh_mb;
|
||||
int pad;
|
||||
u8 pad_luma;
|
||||
u8 pad_cb;
|
||||
u8 pad_cr;
|
||||
int rc_frame;
|
||||
u32 rc_bitrate;
|
||||
u16 rc_reaction_coeff;
|
||||
u16 vbv_size;
|
||||
|
||||
enum v4l2_mpeg_video_header_mode seq_hdr_mode;
|
||||
enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
|
||||
int fixed_target_bit;
|
||||
|
||||
u8 num_b_frame;
|
||||
u32 rc_framerate_num;
|
||||
u32 rc_framerate_denom;
|
||||
int interlace;
|
||||
|
||||
union {
|
||||
struct s5p_mfc_h264_enc_params h264;
|
||||
struct s5p_mfc_mpeg4_enc_params mpeg4;
|
||||
} codec;
|
||||
|
||||
};
|
||||
|
||||
/**
|
||||
* struct s5p_mfc_codec_ops - codec ops, used by encoding
|
||||
*/
|
||||
struct s5p_mfc_codec_ops {
|
||||
/* initialization routines */
|
||||
int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
|
||||
int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
|
||||
/* execution routines */
|
||||
int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
|
||||
int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
|
||||
};
|
||||
|
||||
#define call_cop(c, op, args...) \
|
||||
(((c)->c_ops->op) ? \
|
||||
((c)->c_ops->op(args)) : 0)
|
||||
|
||||
/**
|
||||
* struct s5p_mfc_ctx - This struct contains the instance context
|
||||
*
|
||||
* @dev: pointer to the s5p_mfc_dev of the device
|
||||
* @fh: struct v4l2_fh
|
||||
* @num: number of the context that this structure describes
|
||||
* @int_cond: variable used by the waitqueue
|
||||
* @int_type: type of the last interrupt
|
||||
* @int_err: error number received from MFC hw in the interrupt
|
||||
* @queue: waitqueue that can be used to wait for this context to
|
||||
* finish
|
||||
* @src_fmt: source pixelformat information
|
||||
* @dst_fmt: destination pixelformat information
|
||||
* @vq_src: vb2 queue for source buffers
|
||||
* @vq_dst: vb2 queue for destination buffers
|
||||
* @src_queue: driver internal queue for source buffers
|
||||
* @dst_queue: driver internal queue for destination buffers
|
||||
* @src_queue_cnt: number of buffers queued on the source internal queue
|
||||
* @dst_queue_cnt: number of buffers queued on the dest internal queue
|
||||
* @type: type of the instance - decoder or encoder
|
||||
* @state: state of the context
|
||||
* @inst_no: number of hw instance associated with the context
|
||||
* @img_width: width of the image that is decoded or encoded
|
||||
* @img_height: height of the image that is decoded or encoded
|
||||
* @buf_width: width of the buffer for processed image
|
||||
* @buf_height: height of the buffer for processed image
|
||||
* @luma_size: size of a luma plane
|
||||
* @chroma_size: size of a chroma plane
|
||||
* @mv_size: size of a motion vectors buffer
|
||||
* @consumed_stream: number of bytes that have been used so far from the
|
||||
* decoding buffer
|
||||
* @dpb_flush_flag: flag used to indicate that a DPB buffers are being
|
||||
* flushed
|
||||
* @bank1_buf: handle to memory allocated for temporary buffers from
|
||||
* memory bank 1
|
||||
* @bank1_phys: address of the temporary buffers from memory bank 1
|
||||
* @bank1_size: size of the memory allocated for temporary buffers from
|
||||
* memory bank 1
|
||||
* @bank2_buf: handle to memory allocated for temporary buffers from
|
||||
* memory bank 2
|
||||
* @bank2_phys: address of the temporary buffers from memory bank 2
|
||||
* @bank2_size: size of the memory allocated for temporary buffers from
|
||||
* memory bank 2
|
||||
* @capture_state: state of the capture buffers queue
|
||||
* @output_state: state of the output buffers queue
|
||||
* @src_bufs: information on allocated source buffers
|
||||
* @dst_bufs: information on allocated destination buffers
|
||||
* @sequence: counter for the sequence number for v4l2
|
||||
* @dec_dst_flag: flags for buffers queued in the hardware
|
||||
* @dec_src_buf_size: size of the buffer for source buffers in decoding
|
||||
* @codec_mode: number of codec mode used by MFC hw
|
||||
* @slice_interface: slice interface flag
|
||||
* @loop_filter_mpeg4: loop filter for MPEG4 flag
|
||||
* @display_delay: value of the display delay for H264
|
||||
* @display_delay_enable: display delay for H264 enable flag
|
||||
* @after_packed_pb: flag used to track buffer when stream is in
|
||||
* Packed PB format
|
||||
* @dpb_count: count of the DPB buffers required by MFC hw
|
||||
* @total_dpb_count: count of DPB buffers with additional buffers
|
||||
* requested by the application
|
||||
* @ctx_buf: handle to the memory associated with this context
|
||||
* @ctx_phys: address of the memory associated with this context
|
||||
* @ctx_size: size of the memory associated with this context
|
||||
* @desc_buf: description buffer for decoding handle
|
||||
* @desc_phys: description buffer for decoding address
|
||||
* @shm_alloc: handle for the shared memory buffer
|
||||
* @shm: virtual address for the shared memory buffer
|
||||
* @shm_ofs: address offset for shared memory
|
||||
* @enc_params: encoding parameters for MFC
|
||||
* @enc_dst_buf_size: size of the buffers for encoder output
|
||||
* @frame_type: used to force the type of the next encoded frame
|
||||
* @ref_queue: list of the reference buffers for encoding
|
||||
* @ref_queue_cnt: number of the buffers in the reference list
|
||||
* @c_ops: ops for encoding
|
||||
* @ctrls: array of controls, used when adding controls to the
|
||||
* v4l2 control framework
|
||||
* @ctrl_handler: handler for v4l2 framework
|
||||
*/
|
||||
struct s5p_mfc_ctx {
|
||||
struct s5p_mfc_dev *dev;
|
||||
struct v4l2_fh fh;
|
||||
|
||||
int num;
|
||||
|
||||
int int_cond;
|
||||
int int_type;
|
||||
unsigned int int_err;
|
||||
wait_queue_head_t queue;
|
||||
|
||||
struct s5p_mfc_fmt *src_fmt;
|
||||
struct s5p_mfc_fmt *dst_fmt;
|
||||
|
||||
struct vb2_queue vq_src;
|
||||
struct vb2_queue vq_dst;
|
||||
|
||||
struct list_head src_queue;
|
||||
struct list_head dst_queue;
|
||||
|
||||
unsigned int src_queue_cnt;
|
||||
unsigned int dst_queue_cnt;
|
||||
|
||||
enum s5p_mfc_inst_type type;
|
||||
enum s5p_mfc_inst_state state;
|
||||
int inst_no;
|
||||
|
||||
/* Image parameters */
|
||||
int img_width;
|
||||
int img_height;
|
||||
int buf_width;
|
||||
int buf_height;
|
||||
|
||||
int luma_size;
|
||||
int chroma_size;
|
||||
int mv_size;
|
||||
|
||||
unsigned long consumed_stream;
|
||||
|
||||
unsigned int dpb_flush_flag;
|
||||
|
||||
/* Buffers */
|
||||
void *bank1_buf;
|
||||
size_t bank1_phys;
|
||||
size_t bank1_size;
|
||||
|
||||
void *bank2_buf;
|
||||
size_t bank2_phys;
|
||||
size_t bank2_size;
|
||||
|
||||
enum s5p_mfc_queue_state capture_state;
|
||||
enum s5p_mfc_queue_state output_state;
|
||||
|
||||
struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
|
||||
int src_bufs_cnt;
|
||||
struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
|
||||
int dst_bufs_cnt;
|
||||
|
||||
unsigned int sequence;
|
||||
unsigned long dec_dst_flag;
|
||||
size_t dec_src_buf_size;
|
||||
|
||||
/* Control values */
|
||||
int codec_mode;
|
||||
int slice_interface;
|
||||
int loop_filter_mpeg4;
|
||||
int display_delay;
|
||||
int display_delay_enable;
|
||||
int after_packed_pb;
|
||||
|
||||
int dpb_count;
|
||||
int total_dpb_count;
|
||||
|
||||
/* Buffers */
|
||||
void *ctx_buf;
|
||||
size_t ctx_phys;
|
||||
size_t ctx_ofs;
|
||||
size_t ctx_size;
|
||||
|
||||
void *desc_buf;
|
||||
size_t desc_phys;
|
||||
|
||||
|
||||
void *shm_alloc;
|
||||
void *shm;
|
||||
size_t shm_ofs;
|
||||
|
||||
struct s5p_mfc_enc_params enc_params;
|
||||
|
||||
size_t enc_dst_buf_size;
|
||||
|
||||
enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
|
||||
|
||||
struct list_head ref_queue;
|
||||
unsigned int ref_queue_cnt;
|
||||
|
||||
struct s5p_mfc_codec_ops *c_ops;
|
||||
|
||||
struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
|
||||
struct v4l2_ctrl_handler ctrl_handler;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct s5p_mfc_fmt - structure used to store information about pixelformats
|
||||
* used by the MFC
|
||||
*/
|
||||
struct s5p_mfc_fmt {
|
||||
char *name;
|
||||
u32 fourcc;
|
||||
u32 codec_mode;
|
||||
enum s5p_mfc_fmt_type type;
|
||||
u32 num_planes;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mfc_control - structure used to store information about MFC controls
|
||||
* it is used to initialize the control framework.
|
||||
*/
|
||||
struct mfc_control {
|
||||
__u32 id;
|
||||
enum v4l2_ctrl_type type;
|
||||
__u8 name[32]; /* Whatever */
|
||||
__s32 minimum; /* Note signedness */
|
||||
__s32 maximum;
|
||||
__s32 step;
|
||||
__u32 menu_skip_mask;
|
||||
__s32 default_value;
|
||||
__u32 flags;
|
||||
__u32 reserved[2];
|
||||
__u8 is_volatile;
|
||||
};
|
||||
|
||||
|
||||
#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
|
||||
#define ctrl_to_ctx(__ctrl) \
|
||||
container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
|
||||
|
||||
#endif /* S5P_MFC_COMMON_H_ */
|
||||
|
|
@ -0,0 +1,343 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/sched.h>
|
||||
#include "regs-mfc.h"
|
||||
#include "s5p_mfc_cmd.h"
|
||||
#include "s5p_mfc_common.h"
|
||||
#include "s5p_mfc_debug.h"
|
||||
#include "s5p_mfc_intr.h"
|
||||
#include "s5p_mfc_pm.h"
|
||||
|
||||
static void *s5p_mfc_bitproc_buf;
|
||||
static size_t s5p_mfc_bitproc_phys;
|
||||
static unsigned char *s5p_mfc_bitproc_virt;
|
||||
|
||||
/* Allocate and load firmware */
|
||||
int s5p_mfc_alloc_and_load_firmware(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
struct firmware *fw_blob;
|
||||
size_t bank2_base_phys;
|
||||
void *b_base;
|
||||
int err;
|
||||
|
||||
/* Firmare has to be present as a separate file or compiled
|
||||
* into kernel. */
|
||||
mfc_debug_enter();
|
||||
err = request_firmware((const struct firmware **)&fw_blob,
|
||||
"s5pc110-mfc.fw", dev->v4l2_dev.dev);
|
||||
if (err != 0) {
|
||||
mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
dev->fw_size = ALIGN(fw_blob->size, FIRMWARE_ALIGN);
|
||||
if (s5p_mfc_bitproc_buf) {
|
||||
mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
|
||||
release_firmware(fw_blob);
|
||||
return -ENOMEM;
|
||||
}
|
||||
s5p_mfc_bitproc_buf = vb2_dma_contig_memops.alloc(
|
||||
dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], dev->fw_size);
|
||||
if (IS_ERR(s5p_mfc_bitproc_buf)) {
|
||||
s5p_mfc_bitproc_buf = 0;
|
||||
mfc_err("Allocating bitprocessor buffer failed\n");
|
||||
release_firmware(fw_blob);
|
||||
return -ENOMEM;
|
||||
}
|
||||
s5p_mfc_bitproc_phys = s5p_mfc_mem_cookie(
|
||||
dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], s5p_mfc_bitproc_buf);
|
||||
if (s5p_mfc_bitproc_phys & ((1 << MFC_BASE_ALIGN_ORDER) - 1)) {
|
||||
mfc_err("The base memory for bank 1 is not aligned to 128KB\n");
|
||||
vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
|
||||
s5p_mfc_bitproc_phys = 0;
|
||||
s5p_mfc_bitproc_buf = 0;
|
||||
release_firmware(fw_blob);
|
||||
return -EIO;
|
||||
}
|
||||
s5p_mfc_bitproc_virt = vb2_dma_contig_memops.vaddr(s5p_mfc_bitproc_buf);
|
||||
if (!s5p_mfc_bitproc_virt) {
|
||||
mfc_err("Bitprocessor memory remap failed\n");
|
||||
vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
|
||||
s5p_mfc_bitproc_phys = 0;
|
||||
s5p_mfc_bitproc_buf = 0;
|
||||
release_firmware(fw_blob);
|
||||
return -EIO;
|
||||
}
|
||||
dev->bank1 = s5p_mfc_bitproc_phys;
|
||||
b_base = vb2_dma_contig_memops.alloc(
|
||||
dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], 1 << MFC_BANK2_ALIGN_ORDER);
|
||||
if (IS_ERR(b_base)) {
|
||||
vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
|
||||
s5p_mfc_bitproc_phys = 0;
|
||||
s5p_mfc_bitproc_buf = 0;
|
||||
mfc_err("Allocating bank2 base failed\n");
|
||||
release_firmware(fw_blob);
|
||||
return -ENOMEM;
|
||||
}
|
||||
bank2_base_phys = s5p_mfc_mem_cookie(
|
||||
dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], b_base);
|
||||
vb2_dma_contig_memops.put(b_base);
|
||||
if (bank2_base_phys & ((1 << MFC_BASE_ALIGN_ORDER) - 1)) {
|
||||
mfc_err("The base memory for bank 2 is not aligned to 128KB\n");
|
||||
vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
|
||||
s5p_mfc_bitproc_phys = 0;
|
||||
s5p_mfc_bitproc_buf = 0;
|
||||
release_firmware(fw_blob);
|
||||
return -EIO;
|
||||
}
|
||||
dev->bank2 = bank2_base_phys;
|
||||
memcpy(s5p_mfc_bitproc_virt, fw_blob->data, fw_blob->size);
|
||||
wmb();
|
||||
release_firmware(fw_blob);
|
||||
mfc_debug_leave();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Reload firmware to MFC */
|
||||
int s5p_mfc_reload_firmware(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
struct firmware *fw_blob;
|
||||
int err;
|
||||
|
||||
/* Firmare has to be present as a separate file or compiled
|
||||
* into kernel. */
|
||||
mfc_debug_enter();
|
||||
err = request_firmware((const struct firmware **)&fw_blob,
|
||||
"s5pc110-mfc.fw", dev->v4l2_dev.dev);
|
||||
if (err != 0) {
|
||||
mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if (fw_blob->size > dev->fw_size) {
|
||||
mfc_err("MFC firmware is too big to be loaded\n");
|
||||
release_firmware(fw_blob);
|
||||
return -ENOMEM;
|
||||
}
|
||||
if (s5p_mfc_bitproc_buf == 0 || s5p_mfc_bitproc_phys == 0) {
|
||||
mfc_err("MFC firmware is not allocated or was not mapped correctly\n");
|
||||
release_firmware(fw_blob);
|
||||
return -EINVAL;
|
||||
}
|
||||
memcpy(s5p_mfc_bitproc_virt, fw_blob->data, fw_blob->size);
|
||||
wmb();
|
||||
release_firmware(fw_blob);
|
||||
mfc_debug_leave();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Release firmware memory */
|
||||
int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
/* Before calling this function one has to make sure
|
||||
* that MFC is no longer processing */
|
||||
if (!s5p_mfc_bitproc_buf)
|
||||
return -EINVAL;
|
||||
vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
|
||||
s5p_mfc_bitproc_virt = 0;
|
||||
s5p_mfc_bitproc_phys = 0;
|
||||
s5p_mfc_bitproc_buf = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Reset the device */
|
||||
int s5p_mfc_reset(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
unsigned int mc_status;
|
||||
unsigned long timeout;
|
||||
|
||||
mfc_debug_enter();
|
||||
/* Stop procedure */
|
||||
/* reset RISC */
|
||||
mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
|
||||
/* All reset except for MC */
|
||||
mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
|
||||
mdelay(10);
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
|
||||
/* Check MC status */
|
||||
do {
|
||||
if (time_after(jiffies, timeout)) {
|
||||
mfc_err("Timeout while resetting MFC\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
|
||||
|
||||
} while (mc_status & 0x3);
|
||||
|
||||
mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
|
||||
mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
|
||||
mfc_debug_leave();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A);
|
||||
mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B);
|
||||
mfc_debug(2, "Bank1: %08x, Bank2: %08x\n", dev->bank1, dev->bank2);
|
||||
}
|
||||
|
||||
static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
|
||||
mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
|
||||
mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
|
||||
mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
|
||||
}
|
||||
|
||||
/* Initialize hardware */
|
||||
int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
unsigned int ver;
|
||||
int ret;
|
||||
|
||||
mfc_debug_enter();
|
||||
if (!s5p_mfc_bitproc_buf)
|
||||
return -EINVAL;
|
||||
|
||||
/* 0. MFC reset */
|
||||
mfc_debug(2, "MFC reset..\n");
|
||||
s5p_mfc_clock_on();
|
||||
ret = s5p_mfc_reset(dev);
|
||||
if (ret) {
|
||||
mfc_err("Failed to reset MFC - timeout\n");
|
||||
return ret;
|
||||
}
|
||||
mfc_debug(2, "Done MFC reset..\n");
|
||||
/* 1. Set DRAM base Addr */
|
||||
s5p_mfc_init_memctrl(dev);
|
||||
/* 2. Initialize registers of channel I/F */
|
||||
s5p_mfc_clear_cmds(dev);
|
||||
/* 3. Release reset signal to the RISC */
|
||||
s5p_mfc_clean_dev_int_flags(dev);
|
||||
mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
|
||||
mfc_debug(2, "Will now wait for completion of firmware transfer\n");
|
||||
if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_FW_STATUS_RET)) {
|
||||
mfc_err("Failed to load firmware\n");
|
||||
s5p_mfc_reset(dev);
|
||||
s5p_mfc_clock_off();
|
||||
return -EIO;
|
||||
}
|
||||
s5p_mfc_clean_dev_int_flags(dev);
|
||||
/* 4. Initialize firmware */
|
||||
ret = s5p_mfc_sys_init_cmd(dev);
|
||||
if (ret) {
|
||||
mfc_err("Failed to send command to MFC - timeout\n");
|
||||
s5p_mfc_reset(dev);
|
||||
s5p_mfc_clock_off();
|
||||
return ret;
|
||||
}
|
||||
mfc_debug(2, "Ok, now will write a command to init the system\n");
|
||||
if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SYS_INIT_RET)) {
|
||||
mfc_err("Failed to load firmware\n");
|
||||
s5p_mfc_reset(dev);
|
||||
s5p_mfc_clock_off();
|
||||
return -EIO;
|
||||
}
|
||||
dev->int_cond = 0;
|
||||
if (dev->int_err != 0 || dev->int_type !=
|
||||
S5P_FIMV_R2H_CMD_SYS_INIT_RET) {
|
||||
/* Failure. */
|
||||
mfc_err("Failed to init firmware - error: %d int: %d\n",
|
||||
dev->int_err, dev->int_type);
|
||||
s5p_mfc_reset(dev);
|
||||
s5p_mfc_clock_off();
|
||||
return -EIO;
|
||||
}
|
||||
ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
|
||||
mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
|
||||
(ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
|
||||
s5p_mfc_clock_off();
|
||||
mfc_debug_leave();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
mfc_debug_enter();
|
||||
s5p_mfc_clock_on();
|
||||
s5p_mfc_clean_dev_int_flags(dev);
|
||||
ret = s5p_mfc_sleep_cmd(dev);
|
||||
if (ret) {
|
||||
mfc_err("Failed to send command to MFC - timeout\n");
|
||||
return ret;
|
||||
}
|
||||
if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SLEEP_RET)) {
|
||||
mfc_err("Failed to sleep\n");
|
||||
return -EIO;
|
||||
}
|
||||
s5p_mfc_clock_off();
|
||||
dev->int_cond = 0;
|
||||
if (dev->int_err != 0 || dev->int_type !=
|
||||
S5P_FIMV_R2H_CMD_SLEEP_RET) {
|
||||
/* Failure. */
|
||||
mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
|
||||
dev->int_type);
|
||||
return -EIO;
|
||||
}
|
||||
mfc_debug_leave();
|
||||
return ret;
|
||||
}
|
||||
|
||||
int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
mfc_debug_enter();
|
||||
/* 0. MFC reset */
|
||||
mfc_debug(2, "MFC reset..\n");
|
||||
s5p_mfc_clock_on();
|
||||
ret = s5p_mfc_reset(dev);
|
||||
if (ret) {
|
||||
mfc_err("Failed to reset MFC - timeout\n");
|
||||
return ret;
|
||||
}
|
||||
mfc_debug(2, "Done MFC reset..\n");
|
||||
/* 1. Set DRAM base Addr */
|
||||
s5p_mfc_init_memctrl(dev);
|
||||
/* 2. Initialize registers of channel I/F */
|
||||
s5p_mfc_clear_cmds(dev);
|
||||
s5p_mfc_clean_dev_int_flags(dev);
|
||||
/* 3. Initialize firmware */
|
||||
ret = s5p_mfc_wakeup_cmd(dev);
|
||||
if (ret) {
|
||||
mfc_err("Failed to send command to MFC - timeout\n");
|
||||
return ret;
|
||||
}
|
||||
/* 4. Release reset signal to the RISC */
|
||||
mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
|
||||
mfc_debug(2, "Ok, now will write a command to wakeup the system\n");
|
||||
if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_WAKEUP_RET)) {
|
||||
mfc_err("Failed to load firmware\n");
|
||||
return -EIO;
|
||||
}
|
||||
s5p_mfc_clock_off();
|
||||
dev->int_cond = 0;
|
||||
if (dev->int_err != 0 || dev->int_type !=
|
||||
S5P_FIMV_R2H_CMD_WAKEUP_RET) {
|
||||
/* Failure. */
|
||||
mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
|
||||
dev->int_type);
|
||||
return -EIO;
|
||||
}
|
||||
mfc_debug_leave();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_CTRL_H
|
||||
#define S5P_MFC_CTRL_H
|
||||
|
||||
#include "s5p_mfc_common.h"
|
||||
|
||||
int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev);
|
||||
int s5p_mfc_alloc_and_load_firmware(struct s5p_mfc_dev *dev);
|
||||
int s5p_mfc_reload_firmware(struct s5p_mfc_dev *dev);
|
||||
|
||||
int s5p_mfc_init_hw(struct s5p_mfc_dev *dev);
|
||||
|
||||
int s5p_mfc_sleep(struct s5p_mfc_dev *dev);
|
||||
int s5p_mfc_wakeup(struct s5p_mfc_dev *dev);
|
||||
|
||||
int s5p_mfc_reset(struct s5p_mfc_dev *dev);
|
||||
|
||||
#endif /* S5P_MFC_CTRL_H */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* drivers/media/video/samsung/mfc5/s5p_mfc_debug.h
|
||||
*
|
||||
* Header file for Samsung MFC (Multi Function Codec - FIMV) driver
|
||||
* This file contains debug macros
|
||||
*
|
||||
* Kamil Debski, Copyright (c) 2011 Samsung Electronics
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_DEBUG_H_
|
||||
#define S5P_MFC_DEBUG_H_
|
||||
|
||||
#define DEBUG
|
||||
|
||||
#ifdef DEBUG
|
||||
extern int debug;
|
||||
|
||||
#define mfc_debug(level, fmt, args...) \
|
||||
do { \
|
||||
if (debug >= level) \
|
||||
printk(KERN_DEBUG "%s:%d: " fmt, \
|
||||
__func__, __LINE__, ##args); \
|
||||
} while (0)
|
||||
#else
|
||||
#define mfc_debug(level, fmt, args...)
|
||||
#endif
|
||||
|
||||
#define mfc_debug_enter() mfc_debug(5, "enter")
|
||||
#define mfc_debug_leave() mfc_debug(5, "leave")
|
||||
|
||||
#define mfc_err(fmt, args...) \
|
||||
do { \
|
||||
printk(KERN_ERR "%s:%d: " fmt, \
|
||||
__func__, __LINE__, ##args); \
|
||||
} while (0)
|
||||
|
||||
#define mfc_info(fmt, args...) \
|
||||
do { \
|
||||
printk(KERN_INFO "%s:%d: " fmt, \
|
||||
__func__, __LINE__, ##args); \
|
||||
} while (0)
|
||||
|
||||
#endif /* S5P_MFC_DEBUG_H_ */
|
||||
Разница между файлами не показана из-за своего большого размера
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|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_dec.h
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_DEC_H_
|
||||
#define S5P_MFC_DEC_H_
|
||||
|
||||
struct s5p_mfc_codec_ops *get_dec_codec_ops(void);
|
||||
struct vb2_ops *get_dec_queue_ops(void);
|
||||
const struct v4l2_ioctl_ops *get_dec_v4l2_ioctl_ops(void);
|
||||
struct s5p_mfc_fmt *get_dec_def_fmt(bool src);
|
||||
int s5p_mfc_dec_ctrls_setup(struct s5p_mfc_ctx *ctx);
|
||||
void s5p_mfc_dec_ctrls_delete(struct s5p_mfc_ctx *ctx);
|
||||
|
||||
#endif /* S5P_MFC_DEC_H_ */
|
||||
Разница между файлами не показана из-за своего большого размера
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|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_enc.h
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_ENC_H_
|
||||
#define S5P_MFC_ENC_H_
|
||||
|
||||
struct s5p_mfc_codec_ops *get_enc_codec_ops(void);
|
||||
struct vb2_ops *get_enc_queue_ops(void);
|
||||
const struct v4l2_ioctl_ops *get_enc_v4l2_ioctl_ops(void);
|
||||
struct s5p_mfc_fmt *get_enc_def_fmt(bool src);
|
||||
int s5p_mfc_enc_ctrls_setup(struct s5p_mfc_ctx *ctx);
|
||||
void s5p_mfc_enc_ctrls_delete(struct s5p_mfc_ctx *ctx);
|
||||
|
||||
#endif /* S5P_MFC_ENC_H_ */
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* drivers/media/video/samsung/mfc5/s5p_mfc_intr.c
|
||||
*
|
||||
* C file for Samsung MFC (Multi Function Codec - FIMV) driver
|
||||
* This file contains functions used to wait for command completion.
|
||||
*
|
||||
* Kamil Debski, Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/wait.h>
|
||||
#include "regs-mfc.h"
|
||||
#include "s5p_mfc_common.h"
|
||||
#include "s5p_mfc_debug.h"
|
||||
#include "s5p_mfc_intr.h"
|
||||
|
||||
int s5p_mfc_wait_for_done_dev(struct s5p_mfc_dev *dev, int command)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = wait_event_interruptible_timeout(dev->queue,
|
||||
(dev->int_cond && (dev->int_type == command
|
||||
|| dev->int_type == S5P_FIMV_R2H_CMD_ERR_RET)),
|
||||
msecs_to_jiffies(MFC_INT_TIMEOUT));
|
||||
if (ret == 0) {
|
||||
mfc_err("Interrupt (dev->int_type:%d, command:%d) timed out\n",
|
||||
dev->int_type, command);
|
||||
return 1;
|
||||
} else if (ret == -ERESTARTSYS) {
|
||||
mfc_err("Interrupted by a signal\n");
|
||||
return 1;
|
||||
}
|
||||
mfc_debug(1, "Finished waiting (dev->int_type:%d, command: %d)\n",
|
||||
dev->int_type, command);
|
||||
if (dev->int_type == S5P_FIMV_R2H_CMD_ERR_RET)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void s5p_mfc_clean_dev_int_flags(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
dev->int_cond = 0;
|
||||
dev->int_type = 0;
|
||||
dev->int_err = 0;
|
||||
}
|
||||
|
||||
int s5p_mfc_wait_for_done_ctx(struct s5p_mfc_ctx *ctx,
|
||||
int command, int interrupt)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (interrupt) {
|
||||
ret = wait_event_interruptible_timeout(ctx->queue,
|
||||
(ctx->int_cond && (ctx->int_type == command
|
||||
|| ctx->int_type == S5P_FIMV_R2H_CMD_ERR_RET)),
|
||||
msecs_to_jiffies(MFC_INT_TIMEOUT));
|
||||
} else {
|
||||
ret = wait_event_timeout(ctx->queue,
|
||||
(ctx->int_cond && (ctx->int_type == command
|
||||
|| ctx->int_type == S5P_FIMV_R2H_CMD_ERR_RET)),
|
||||
msecs_to_jiffies(MFC_INT_TIMEOUT));
|
||||
}
|
||||
if (ret == 0) {
|
||||
mfc_err("Interrupt (ctx->int_type:%d, command:%d) timed out\n",
|
||||
ctx->int_type, command);
|
||||
return 1;
|
||||
} else if (ret == -ERESTARTSYS) {
|
||||
mfc_err("Interrupted by a signal\n");
|
||||
return 1;
|
||||
}
|
||||
mfc_debug(1, "Finished waiting (ctx->int_type:%d, command: %d)\n",
|
||||
ctx->int_type, command);
|
||||
if (ctx->int_type == S5P_FIMV_R2H_CMD_ERR_RET)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void s5p_mfc_clean_ctx_int_flags(struct s5p_mfc_ctx *ctx)
|
||||
{
|
||||
ctx->int_cond = 0;
|
||||
ctx->int_type = 0;
|
||||
ctx->int_err = 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* drivers/media/video/samsung/mfc5/s5p_mfc_intr.h
|
||||
*
|
||||
* Header file for Samsung MFC (Multi Function Codec - FIMV) driver
|
||||
* It contains waiting functions declarations.
|
||||
*
|
||||
* Kamil Debski, Copyright (C) 2011 Samsung Electronics
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_INTR_H_
|
||||
#define S5P_MFC_INTR_H_
|
||||
|
||||
#include "s5p_mfc_common.h"
|
||||
|
||||
int s5p_mfc_wait_for_done_ctx(struct s5p_mfc_ctx *ctx,
|
||||
int command, int interrupt);
|
||||
int s5p_mfc_wait_for_done_dev(struct s5p_mfc_dev *dev, int command);
|
||||
void s5p_mfc_clean_ctx_int_flags(struct s5p_mfc_ctx *ctx);
|
||||
void s5p_mfc_clean_dev_int_flags(struct s5p_mfc_dev *dev);
|
||||
|
||||
#endif /* S5P_MFC_INTR_H_ */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* drivers/media/video/samsung/mfc5/s5p_mfc_opr.h
|
||||
*
|
||||
* Header file for Samsung MFC (Multi Function Codec - FIMV) driver
|
||||
* Contains declarations of hw related functions.
|
||||
*
|
||||
* Kamil Debski, Copyright (C) 2011 Samsung Electronics
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_OPR_H_
|
||||
#define S5P_MFC_OPR_H_
|
||||
|
||||
#include "s5p_mfc_common.h"
|
||||
|
||||
int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx);
|
||||
int s5p_mfc_init_encode(struct s5p_mfc_ctx *mfc_ctx);
|
||||
|
||||
/* Decoding functions */
|
||||
int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx);
|
||||
int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr,
|
||||
unsigned int start_num_byte,
|
||||
unsigned int buf_size);
|
||||
|
||||
/* Encoding functions */
|
||||
void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
|
||||
unsigned long y_addr, unsigned long c_addr);
|
||||
int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx,
|
||||
unsigned long addr, unsigned int size);
|
||||
void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
|
||||
unsigned long *y_addr, unsigned long *c_addr);
|
||||
int s5p_mfc_set_enc_ref_buffer(struct s5p_mfc_ctx *mfc_ctx);
|
||||
|
||||
int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx,
|
||||
enum s5p_mfc_decode_arg last_frame);
|
||||
int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *mfc_ctx);
|
||||
|
||||
/* Memory allocation */
|
||||
int s5p_mfc_alloc_dec_temp_buffers(struct s5p_mfc_ctx *ctx);
|
||||
void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx);
|
||||
void s5p_mfc_release_dec_desc_buffer(struct s5p_mfc_ctx *ctx);
|
||||
|
||||
int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx);
|
||||
void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx);
|
||||
|
||||
int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx);
|
||||
void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx);
|
||||
|
||||
void s5p_mfc_try_run(struct s5p_mfc_dev *dev);
|
||||
void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
|
||||
|
||||
#define s5p_mfc_get_dspl_y_adr() (readl(dev->regs_base + \
|
||||
S5P_FIMV_SI_DISPLAY_Y_ADR) << \
|
||||
MFC_OFFSET_SHIFT)
|
||||
#define s5p_mfc_get_dec_y_adr() (readl(dev->regs_base + \
|
||||
S5P_FIMV_SI_DISPLAY_Y_ADR) << \
|
||||
MFC_OFFSET_SHIFT)
|
||||
#define s5p_mfc_get_dspl_status() readl(dev->regs_base + \
|
||||
S5P_FIMV_SI_DISPLAY_STATUS)
|
||||
#define s5p_mfc_get_frame_type() (readl(dev->regs_base + \
|
||||
S5P_FIMV_DECODE_FRAME_TYPE) \
|
||||
& S5P_FIMV_DECODE_FRAME_MASK)
|
||||
#define s5p_mfc_get_consumed_stream() readl(dev->regs_base + \
|
||||
S5P_FIMV_SI_CONSUMED_BYTES)
|
||||
#define s5p_mfc_get_int_reason() (readl(dev->regs_base + \
|
||||
S5P_FIMV_RISC2HOST_CMD) & \
|
||||
S5P_FIMV_RISC2HOST_CMD_MASK)
|
||||
#define s5p_mfc_get_int_err() readl(dev->regs_base + \
|
||||
S5P_FIMV_RISC2HOST_ARG2)
|
||||
#define s5p_mfc_err_dec(x) (((x) & S5P_FIMV_ERR_DEC_MASK) >> \
|
||||
S5P_FIMV_ERR_DEC_SHIFT)
|
||||
#define s5p_mfc_err_dspl(x) (((x) & S5P_FIMV_ERR_DSPL_MASK) >> \
|
||||
S5P_FIMV_ERR_DSPL_SHIFT)
|
||||
#define s5p_mfc_get_img_width() readl(dev->regs_base + \
|
||||
S5P_FIMV_SI_HRESOL)
|
||||
#define s5p_mfc_get_img_height() readl(dev->regs_base + \
|
||||
S5P_FIMV_SI_VRESOL)
|
||||
#define s5p_mfc_get_dpb_count() readl(dev->regs_base + \
|
||||
S5P_FIMV_SI_BUF_NUMBER)
|
||||
#define s5p_mfc_get_inst_no() readl(dev->regs_base + \
|
||||
S5P_FIMV_RISC2HOST_ARG1)
|
||||
#define s5p_mfc_get_enc_strm_size() readl(dev->regs_base + \
|
||||
S5P_FIMV_ENC_SI_STRM_SIZE)
|
||||
#define s5p_mfc_get_enc_slice_type() readl(dev->regs_base + \
|
||||
S5P_FIMV_ENC_SI_SLICE_TYPE)
|
||||
|
||||
#endif /* S5P_MFC_OPR_H_ */
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_pm.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/platform_device.h>
|
||||
#ifdef CONFIG_PM_RUNTIME
|
||||
#include <linux/pm_runtime.h>
|
||||
#endif
|
||||
#include "s5p_mfc_common.h"
|
||||
#include "s5p_mfc_debug.h"
|
||||
#include "s5p_mfc_pm.h"
|
||||
|
||||
#define MFC_CLKNAME "sclk_mfc"
|
||||
#define MFC_GATE_CLK_NAME "mfc"
|
||||
|
||||
#define CLK_DEBUG
|
||||
|
||||
static struct s5p_mfc_pm *pm;
|
||||
static struct s5p_mfc_dev *p_dev;
|
||||
|
||||
#ifdef CLK_DEBUG
|
||||
atomic_t clk_ref;
|
||||
#endif
|
||||
|
||||
int s5p_mfc_init_pm(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
pm = &dev->pm;
|
||||
p_dev = dev;
|
||||
pm->clock_gate = clk_get(&dev->plat_dev->dev, MFC_GATE_CLK_NAME);
|
||||
if (IS_ERR(pm->clock_gate)) {
|
||||
mfc_err("Failed to get clock-gating control\n");
|
||||
ret = -ENOENT;
|
||||
goto err_g_ip_clk;
|
||||
}
|
||||
pm->clock = clk_get(&dev->plat_dev->dev, MFC_CLKNAME);
|
||||
if (IS_ERR(pm->clock)) {
|
||||
mfc_err("Failed to get MFC clock\n");
|
||||
ret = -ENOENT;
|
||||
goto err_g_ip_clk_2;
|
||||
}
|
||||
atomic_set(&pm->power, 0);
|
||||
#ifdef CONFIG_PM_RUNTIME
|
||||
pm->device = &dev->plat_dev->dev;
|
||||
pm_runtime_enable(pm->device);
|
||||
#endif
|
||||
#ifdef CLK_DEBUG
|
||||
atomic_set(&clk_ref, 0);
|
||||
#endif
|
||||
return 0;
|
||||
err_g_ip_clk_2:
|
||||
clk_put(pm->clock_gate);
|
||||
err_g_ip_clk:
|
||||
return ret;
|
||||
}
|
||||
|
||||
void s5p_mfc_final_pm(struct s5p_mfc_dev *dev)
|
||||
{
|
||||
clk_put(pm->clock_gate);
|
||||
clk_put(pm->clock);
|
||||
#ifdef CONFIG_PM_RUNTIME
|
||||
pm_runtime_disable(pm->device);
|
||||
#endif
|
||||
}
|
||||
|
||||
int s5p_mfc_clock_on(void)
|
||||
{
|
||||
int ret;
|
||||
#ifdef CLK_DEBUG
|
||||
atomic_inc(&clk_ref);
|
||||
mfc_debug(3, "+ %d", atomic_read(&clk_ref));
|
||||
#endif
|
||||
ret = clk_enable(pm->clock_gate);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void s5p_mfc_clock_off(void)
|
||||
{
|
||||
#ifdef CLK_DEBUG
|
||||
atomic_dec(&clk_ref);
|
||||
mfc_debug(3, "- %d", atomic_read(&clk_ref));
|
||||
#endif
|
||||
clk_disable(pm->clock_gate);
|
||||
}
|
||||
|
||||
int s5p_mfc_power_on(void)
|
||||
{
|
||||
#ifdef CONFIG_PM_RUNTIME
|
||||
return pm_runtime_get_sync(pm->device);
|
||||
#else
|
||||
atomic_set(&pm->power, 1);
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
int s5p_mfc_power_off(void)
|
||||
{
|
||||
#ifdef CONFIG_PM_RUNTIME
|
||||
return pm_runtime_put_sync(pm->device);
|
||||
#else
|
||||
atomic_set(&pm->power, 0);
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_pm.h
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_PM_H_
|
||||
#define S5P_MFC_PM_H_
|
||||
|
||||
int s5p_mfc_init_pm(struct s5p_mfc_dev *dev);
|
||||
void s5p_mfc_final_pm(struct s5p_mfc_dev *dev);
|
||||
|
||||
int s5p_mfc_clock_on(void);
|
||||
void s5p_mfc_clock_off(void);
|
||||
int s5p_mfc_power_on(void);
|
||||
int s5p_mfc_power_off(void);
|
||||
|
||||
#endif /* S5P_MFC_PM_H_ */
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_shm.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS4
|
||||
#include <linux/dma-mapping.h>
|
||||
#endif
|
||||
#include <linux/io.h>
|
||||
#include "s5p_mfc_common.h"
|
||||
#include "s5p_mfc_debug.h"
|
||||
|
||||
int s5p_mfc_init_shm(struct s5p_mfc_ctx *ctx)
|
||||
{
|
||||
struct s5p_mfc_dev *dev = ctx->dev;
|
||||
void *shm_alloc_ctx = dev->alloc_ctx[MFC_BANK1_ALLOC_CTX];
|
||||
|
||||
ctx->shm_alloc = vb2_dma_contig_memops.alloc(shm_alloc_ctx,
|
||||
SHARED_BUF_SIZE);
|
||||
if (IS_ERR(ctx->shm_alloc)) {
|
||||
mfc_err("failed to allocate shared memory\n");
|
||||
return PTR_ERR(ctx->shm_alloc);
|
||||
}
|
||||
/* shm_ofs only keeps the offset from base (port a) */
|
||||
ctx->shm_ofs = s5p_mfc_mem_cookie(shm_alloc_ctx, ctx->shm_alloc)
|
||||
- dev->bank1;
|
||||
BUG_ON(ctx->shm_ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
|
||||
ctx->shm = vb2_dma_contig_memops.vaddr(ctx->shm_alloc);
|
||||
if (!ctx->shm) {
|
||||
vb2_dma_contig_memops.put(ctx->shm_alloc);
|
||||
ctx->shm_ofs = 0;
|
||||
ctx->shm_alloc = NULL;
|
||||
mfc_err("failed to virt addr of shared memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
memset((void *)ctx->shm, 0, SHARED_BUF_SIZE);
|
||||
wmb();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* linux/drivers/media/video/s5p-mfc/s5p_mfc_shm.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef S5P_MFC_SHM_H_
|
||||
#define S5P_MFC_SHM_H_
|
||||
|
||||
enum MFC_SHM_OFS
|
||||
{
|
||||
EXTENEDED_DECODE_STATUS = 0x00, /* D */
|
||||
SET_FRAME_TAG = 0x04, /* D */
|
||||
GET_FRAME_TAG_TOP = 0x08, /* D */
|
||||
GET_FRAME_TAG_BOT = 0x0C, /* D */
|
||||
PIC_TIME_TOP = 0x10, /* D */
|
||||
PIC_TIME_BOT = 0x14, /* D */
|
||||
START_BYTE_NUM = 0x18, /* D */
|
||||
|
||||
CROP_INFO_H = 0x20, /* D */
|
||||
CROP_INFO_V = 0x24, /* D */
|
||||
EXT_ENC_CONTROL = 0x28, /* E */
|
||||
ENC_PARAM_CHANGE = 0x2C, /* E */
|
||||
RC_VOP_TIMING = 0x30, /* E, MPEG4 */
|
||||
HEC_PERIOD = 0x34, /* E, MPEG4 */
|
||||
METADATA_ENABLE = 0x38, /* C */
|
||||
METADATA_STATUS = 0x3C, /* C */
|
||||
METADATA_DISPLAY_INDEX = 0x40, /* C */
|
||||
EXT_METADATA_START_ADDR = 0x44, /* C */
|
||||
PUT_EXTRADATA = 0x48, /* C */
|
||||
EXTRADATA_ADDR = 0x4C, /* C */
|
||||
|
||||
ALLOC_LUMA_DPB_SIZE = 0x64, /* D */
|
||||
ALLOC_CHROMA_DPB_SIZE = 0x68, /* D */
|
||||
ALLOC_MV_SIZE = 0x6C, /* D */
|
||||
P_B_FRAME_QP = 0x70, /* E */
|
||||
SAMPLE_ASPECT_RATIO_IDC = 0x74, /* E, H.264, depend on
|
||||
ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
|
||||
EXTENDED_SAR = 0x78, /* E, H.264, depned on
|
||||
ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
|
||||
DISP_PIC_PROFILE = 0x7C, /* D */
|
||||
FLUSH_CMD_TYPE = 0x80, /* C */
|
||||
FLUSH_CMD_INBUF1 = 0x84, /* C */
|
||||
FLUSH_CMD_INBUF2 = 0x88, /* C */
|
||||
FLUSH_CMD_OUTBUF = 0x8C, /* E */
|
||||
NEW_RC_BIT_RATE = 0x90, /* E, format as RC_BIT_RATE(0xC5A8)
|
||||
depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */
|
||||
NEW_RC_FRAME_RATE = 0x94, /* E, format as RC_FRAME_RATE(0xD0D0)
|
||||
depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */
|
||||
NEW_I_PERIOD = 0x98, /* E, format as I_FRM_CTRL(0xC504)
|
||||
depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */
|
||||
H264_I_PERIOD = 0x9C, /* E, H.264, open GOP */
|
||||
RC_CONTROL_CONFIG = 0xA0, /* E */
|
||||
BATCH_INPUT_ADDR = 0xA4, /* E */
|
||||
BATCH_OUTPUT_ADDR = 0xA8, /* E */
|
||||
BATCH_OUTPUT_SIZE = 0xAC, /* E */
|
||||
MIN_LUMA_DPB_SIZE = 0xB0, /* D */
|
||||
DEVICE_FORMAT_ID = 0xB4, /* C */
|
||||
H264_POC_TYPE = 0xB8, /* D */
|
||||
MIN_CHROMA_DPB_SIZE = 0xBC, /* D */
|
||||
DISP_PIC_FRAME_TYPE = 0xC0, /* D */
|
||||
FREE_LUMA_DPB = 0xC4, /* D, VC1 MPEG4 */
|
||||
ASPECT_RATIO_INFO = 0xC8, /* D, MPEG4 */
|
||||
EXTENDED_PAR = 0xCC, /* D, MPEG4 */
|
||||
DBG_HISTORY_INPUT0 = 0xD0, /* C */
|
||||
DBG_HISTORY_INPUT1 = 0xD4, /* C */
|
||||
DBG_HISTORY_OUTPUT = 0xD8, /* C */
|
||||
HIERARCHICAL_P_QP = 0xE0, /* E, H.264 */
|
||||
};
|
||||
|
||||
int s5p_mfc_init_shm(struct s5p_mfc_ctx *ctx);
|
||||
|
||||
#define s5p_mfc_write_shm(ctx, x, ofs) \
|
||||
do { \
|
||||
writel(x, (ctx->shm + ofs)); \
|
||||
wmb(); \
|
||||
} while (0)
|
||||
|
||||
static inline u32 s5p_mfc_read_shm(struct s5p_mfc_ctx *ctx, unsigned int ofs)
|
||||
{
|
||||
rmb();
|
||||
return readl(ctx->shm + ofs);
|
||||
}
|
||||
|
||||
#endif /* S5P_MFC_SHM_H_ */
|
||||
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