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ARM: SoC: late updates for linux-5.1 

Here are two branches that came relatively late during the linux-5.0
 development cycle and have dependencies on the other branches:
 
 - On the TI OMAP platform, the CPSW Ethernet PHY mode selection driver
   is being replaced, this puts the final pieces in place
 
 - On the DaVinci platform, the interrupt handling code in arch/arm
   gets moved into a regular device driver in drivers/irqchip.
 
 Since they both had some time in linux-next after the 5.0-rc8
 release, I'm sending them along with the other updates.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC late updates from Arnd Bergmann:
 "Here are two branches that came relatively late during the linux-5.0
  development cycle and have dependencies on the other branches:

   - On the TI OMAP platform, the CPSW Ethernet PHY mode selection
     driver is being replaced, this puts the final pieces in place

   - On the DaVinci platform, the interrupt handling code in arch/arm
     gets moved into a regular device driver in drivers/irqchip.

  Since they both had some time in linux-next after the 5.0-rc8 release,
  I'm sending them along with the other updates"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
  net: ethernet: ti: cpsw: deprecate cpsw-phy-sel driver
  ARM: davinci: remove intc related fields from davinci_soc_info
  irqchip: davinci-cp-intc: move the driver to drivers/irqchip
  ARM: davinci: cp-intc: remove redundant comments
  ARM: davinci: cp-intc: drop GPL license boilerplate
  ARM: davinci: cp-intc: use readl/writel_relaxed()
  ARM: davinci: cp-intc: unify error handling
  ARM: davinci: cp-intc: improve coding style
  ARM: davinci: cp-intc: request the memory region before remapping it
  ARM: davinci: cp-intc: use the new-style config structure
  ARM: davinci: cp-intc: convert all hex numbers to lowercase
  ARM: davinci: cp-intc: use a common prefix for all symbols
  ARM: davinci: cp-intc: add the new config structures for da8xx SoCs
  irqchip: davinci-cp-intc: add a new config structure
  ARM: davinci: cp-intc: add a wrapper around cp_intc_init()
  ARM: davinci: cp-intc: remove cp_intc.h
  irqchip: davinci-aintc: move the driver to drivers/irqchip
  ARM: davinci: aintc: remove unnecessary includes
  ARM: davinci: aintc: remove the timer-specific irq_set_handler()
  ARM: davinci: aintc: request memory region before remapping it
  ...
This commit is contained in:
Linus Torvalds 2019-03-06 10:22:26 -08:00
Родитель 64b1b217f1 2547635054
Коммит afe6fe7036
43 изменённых файлов: 889 добавлений и 964 удалений
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2
arch/arm/Kconfig
Просмотреть файл

@ -590,11 +590,13 @@ config ARCH_DAVINCI
select GENERIC_ALLOCATOR
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select GENERIC_IRQ_MULTI_HANDLER
select GPIOLIB
select HAVE_IDE
select PM_GENERIC_DOMAINS if PM
select PM_GENERIC_DOMAINS_OF if PM && OF
select RESET_CONTROLLER
select SPARSE_IRQ
select USE_OF
select ZONE_DMA
help

19
arch/arm/mach-davinci/Kconfig
Просмотреть файл

@ -1,13 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
if ARCH_DAVINCI
config AINTC
bool
config CP_INTC
bool
select IRQ_DOMAIN
config ARCH_DAVINCI_DMx
bool
@ -17,17 +10,17 @@ comment "DaVinci Core Type"
config ARCH_DAVINCI_DM644x
bool "DaVinci 644x based system"
select AINTC
select DAVINCI_AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_DM355
bool "DaVinci 355 based system"
select AINTC
select DAVINCI_AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_DM646x
bool "DaVinci 646x based system"
select AINTC
select DAVINCI_AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_DA830
@ -36,20 +29,20 @@ config ARCH_DAVINCI_DA830
select ARCH_DAVINCI_DA8XX
# needed on silicon revs 1.0, 1.1:
select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE
select CP_INTC
select DAVINCI_CP_INTC
config ARCH_DAVINCI_DA850
bool "DA850/OMAP-L138/AM18x based system"
depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
select ARCH_DAVINCI_DA8XX
select CP_INTC
select DAVINCI_CP_INTC
config ARCH_DAVINCI_DA8XX
bool
config ARCH_DAVINCI_DM365
bool "DaVinci 365 based system"
select AINTC
select DAVINCI_AINTC
select ARCH_DAVINCI_DMx
comment "DaVinci Board Type"

3
arch/arm/mach-davinci/Makefile
Просмотреть файл

@ -18,9 +18,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o
obj-$(CONFIG_AINTC) += irq.o
obj-$(CONFIG_CP_INTC) += cp_intc.o
# Board specific
obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o
obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o

8
arch/arm/mach-davinci/asp.h
Просмотреть файл

@ -49,9 +49,9 @@
#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5
/* Interrupts */
#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
#define DAVINCI_ASP1_RX_INT IRQ_MBRINT
#define DAVINCI_ASP1_TX_INT IRQ_MBXINT
#define DAVINCI_ASP0_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
#define DAVINCI_ASP0_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
#define DAVINCI_ASP1_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
#define DAVINCI_ASP1_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
#endif /* __ASM_ARCH_DAVINCI_ASP_H */

5
arch/arm/mach-davinci/board-da830-evm.c
Просмотреть файл

@ -36,10 +36,11 @@
#include <asm/mach/arch.h>
#include <mach/common.h>
#include "cp_intc.h"
#include <mach/mux.h>
#include <mach/da8xx.h>
#include "irqs.h"
#define DA830_EVM_PHY_ID ""
/*
* USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
@ -633,7 +634,7 @@ static void __init da830_evm_map_io(void)
MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
.atag_offset = 0x100,
.map_io = da830_evm_map_io,
.init_irq = cp_intc_init,
.init_irq = da830_init_irq,
.init_time = da830_init_time,
.init_machine = da830_evm_init,
.init_late = davinci_init_late,

5
arch/arm/mach-davinci/board-da850-evm.c
Просмотреть файл

@ -43,9 +43,10 @@
#include <linux/spi/flash.h>
#include <mach/common.h>
#include "cp_intc.h"
#include <mach/da8xx.h>
#include <mach/mux.h>
#include "irqs.h"
#include "sram.h"
#include <asm/mach-types.h>
@ -1499,7 +1500,7 @@ static void __init da850_evm_map_io(void)
MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
.atag_offset = 0x100,
.map_io = da850_evm_map_io,
.init_irq = cp_intc_init,
.init_irq = da850_init_irq,
.init_time = da850_init_time,
.init_machine = da850_evm_init,
.init_late = davinci_init_late,

2
arch/arm/mach-davinci/board-dm355-evm.c
Просмотреть файл

@ -438,7 +438,7 @@ static __init void dm355_evm_init(void)
MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
.atag_offset = 0x100,
.map_io = dm355_evm_map_io,
.init_irq = davinci_irq_init,
.init_irq = dm355_init_irq,
.init_time = dm355_init_time,
.init_machine = dm355_evm_init,
.init_late = davinci_init_late,

2
arch/arm/mach-davinci/board-dm355-leopard.c
Просмотреть файл

@ -273,7 +273,7 @@ static __init void dm355_leopard_init(void)
MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
.atag_offset = 0x100,
.map_io = dm355_leopard_map_io,
.init_irq = davinci_irq_init,
.init_irq = dm355_init_irq,
.init_time = dm355_init_time,
.init_machine = dm355_leopard_init,
.init_late = davinci_init_late,

2
arch/arm/mach-davinci/board-dm365-evm.c
Просмотреть файл

@ -831,7 +831,7 @@ static __init void dm365_evm_init(void)
MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
.atag_offset = 0x100,
.map_io = dm365_evm_map_io,
.init_irq = davinci_irq_init,
.init_irq = dm365_init_irq,
.init_time = dm365_init_time,
.init_machine = dm365_evm_init,
.init_late = davinci_init_late,

8
arch/arm/mach-davinci/board-dm644x-evm.c
Просмотреть файл

@ -36,9 +36,10 @@
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <linux/platform_data/i2c-davinci.h>
#include <mach/serial.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mmc-davinci.h>
#include <linux/platform_data/usb-davinci.h>
@ -46,6 +47,7 @@
#include <linux/platform_data/ti-aemif.h>
#include "davinci.h"
#include "irqs.h"
#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
#define LXT971_PHY_ID (0x001378e2)
@ -886,7 +888,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
/* Maintainer: MontaVista Software <source@mvista.com> */
.atag_offset = 0x100,
.map_io = davinci_evm_map_io,
.init_irq = davinci_irq_init,
.init_irq = dm644x_init_irq,
.init_time = dm644x_init_time,
.init_machine = davinci_evm_init,
.init_late = davinci_init_late,

6
arch/arm/mach-davinci/board-dm646x-evm.c
Просмотреть файл

@ -44,10 +44,10 @@
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/serial.h>
#include "davinci.h"
#include "irqs.h"
#define NAND_BLOCK_SIZE SZ_128K
@ -860,7 +860,7 @@ static __init void evm_init(void)
MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
.init_irq = dm646x_init_irq,
.init_time = dm646x_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
@ -870,7 +870,7 @@ MACHINE_END
MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
.init_irq = dm646x_init_irq,
.init_time = dm6467t_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,

3
arch/arm/mach-davinci/board-mityomapl138.c
Просмотреть файл

@ -29,7 +29,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include "cp_intc.h"
#include <mach/da8xx.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h>
@ -628,7 +627,7 @@ static void __init mityomapl138_map_io(void)
MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
.atag_offset = 0x100,
.map_io = mityomapl138_map_io,
.init_irq = cp_intc_init,
.init_irq = da850_init_irq,
.init_time = da850_init_time,
.init_machine = mityomapl138_init,
.init_late = davinci_init_late,

2
arch/arm/mach-davinci/board-neuros-osd2.c
Просмотреть файл

@ -231,7 +231,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
/* Maintainer: Neuros Technologies <neuros@groups.google.com> */
.atag_offset = 0x100,
.map_io = davinci_ntosd2_map_io,
.init_irq = davinci_irq_init,
.init_irq = dm644x_init_irq,
.init_time = dm644x_init_time,
.init_machine = davinci_ntosd2_init,
.init_late = davinci_init_late,

3
arch/arm/mach-davinci/board-omapl138-hawk.c
Просмотреть файл

@ -27,7 +27,6 @@
#include <asm/mach/arch.h>
#include <mach/common.h>
#include "cp_intc.h"
#include <mach/da8xx.h>
#include <mach/mux.h>
@ -399,7 +398,7 @@ static void __init omapl138_hawk_map_io(void)
MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
.atag_offset = 0x100,
.map_io = omapl138_hawk_map_io,
.init_irq = cp_intc_init,
.init_irq = da850_init_irq,
.init_time = da850_init_time,
.init_machine = omapl138_hawk_init,
.init_late = davinci_init_late,

2
arch/arm/mach-davinci/board-sffsdr.c
Просмотреть файл

@ -152,7 +152,7 @@ static __init void davinci_sffsdr_init(void)
MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
.atag_offset = 0x100,
.map_io = davinci_sffsdr_map_io,
.init_irq = davinci_irq_init,
.init_irq = dm644x_init_irq,
.init_time = dm644x_init_time,
.init_machine = davinci_sffsdr_init,
.init_late = davinci_init_late,

3
arch/arm/mach-davinci/common.c
Просмотреть файл

@ -23,9 +23,6 @@
struct davinci_soc_info davinci_soc_info;
EXPORT_SYMBOL(davinci_soc_info);
void __iomem *davinci_intc_base;
int davinci_intc_type;
static int __init davinci_init_id(struct davinci_soc_info *soc_info)
{
int i;

215
arch/arm/mach-davinci/cp_intc.c
Просмотреть файл

@ -1,215 +0,0 @@
/*
* TI Common Platform Interrupt Controller (cp_intc) driver
*
* Author: Steve Chen <schen@mvista.com>
* Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/export.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <mach/common.h>
#include "cp_intc.h"
static inline unsigned int cp_intc_read(unsigned offset)
{
return __raw_readl(davinci_intc_base + offset);
}
static inline void cp_intc_write(unsigned long value, unsigned offset)
{
__raw_writel(value, davinci_intc_base + offset);
}
static void cp_intc_ack_irq(struct irq_data *d)
{
cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
}
/* Disable interrupt */
static void cp_intc_mask_irq(struct irq_data *d)
{
/* XXX don't know why we need to disable nIRQ here... */
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
}
/* Enable interrupt */
static void cp_intc_unmask_irq(struct irq_data *d)
{
cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
}
static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
unsigned reg = BIT_WORD(d->hwirq);
unsigned mask = BIT_MASK(d->hwirq);
unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
switch (flow_type) {
case IRQ_TYPE_EDGE_RISING:
polarity |= mask;
type |= mask;
break;
case IRQ_TYPE_EDGE_FALLING:
polarity &= ~mask;
type |= mask;
break;
case IRQ_TYPE_LEVEL_HIGH:
polarity |= mask;
type &= ~mask;
break;
case IRQ_TYPE_LEVEL_LOW:
polarity &= ~mask;
type &= ~mask;
break;
default:
return -EINVAL;
}
cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
return 0;
}
static struct irq_chip cp_intc_irq_chip = {
.name = "cp_intc",
.irq_ack = cp_intc_ack_irq,
.irq_mask = cp_intc_mask_irq,
.irq_unmask = cp_intc_unmask_irq,
.irq_set_type = cp_intc_set_irq_type,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
static struct irq_domain *cp_intc_domain;
static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
irq_set_chip(virq, &cp_intc_irq_chip);
irq_set_probe(virq);
irq_set_handler(virq, handle_edge_irq);
return 0;
}
static const struct irq_domain_ops cp_intc_host_ops = {
.map = cp_intc_host_map,
.xlate = irq_domain_xlate_onetwocell,
};
int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)
{
u32 num_irq = davinci_soc_info.intc_irq_num;
u8 *irq_prio = davinci_soc_info.intc_irq_prios;
u32 *host_map = davinci_soc_info.intc_host_map;
unsigned num_reg = BITS_TO_LONGS(num_irq);
int i, irq_base;
davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
if (node) {
davinci_intc_base = of_iomap(node, 0);
if (of_property_read_u32(node, "ti,intc-size", &num_irq))
pr_warn("unable to get intc-size, default to %d\n",
num_irq);
} else {
davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
}
if (WARN_ON(!davinci_intc_base))
return -EINVAL;
cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
/* Disable all host interrupts */
cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
/* Disable system interrupts */
for (i = 0; i < num_reg; i++)
cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
/* Set to normal mode, no nesting, no priority hold */
cp_intc_write(0, CP_INTC_CTRL);
cp_intc_write(0, CP_INTC_HOST_CTRL);
/* Clear system interrupt status */
for (i = 0; i < num_reg; i++)
cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
/* Enable nIRQ (what about nFIQ?) */
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
/*
* Priority is determined by host channel: lower channel number has
* higher priority i.e. channel 0 has highest priority and channel 31
* had the lowest priority.
*/
num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
if (irq_prio) {
unsigned j, k;
u32 val;
for (k = i = 0; i < num_reg; i++) {
for (val = j = 0; j < 4; j++, k++) {
val >>= 8;
if (k < num_irq)
val |= irq_prio[k] << 24;
}
cp_intc_write(val, CP_INTC_CHAN_MAP(i));
}
} else {
/*
* Default everything to channel 15 if priority not specified.
* Note that channel 0-1 are mapped to nFIQ and channels 2-31
* are mapped to nIRQ.
*/
for (i = 0; i < num_reg; i++)
cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
}
if (host_map)
for (i = 0; host_map[i] != -1; i++)
cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
if (irq_base < 0) {
pr_warn("Couldn't allocate IRQ numbers\n");
irq_base = 0;
}
/* create a legacy host */
cp_intc_domain = irq_domain_add_legacy(node, num_irq,
irq_base, 0, &cp_intc_host_ops, NULL);
if (!cp_intc_domain) {
pr_err("cp_intc: failed to allocate irq host!\n");
return -EINVAL;
}
/* Enable global interrupt */
cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
return 0;
}
void __init cp_intc_init(void)
{
cp_intc_of_init(NULL, NULL);
}
IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", cp_intc_of_init);

57
arch/arm/mach-davinci/cp_intc.h
Просмотреть файл

@ -1,57 +0,0 @@
/*
* TI Common Platform Interrupt Controller (cp_intc) definitions
*
* Author: Steve Chen <schen@mvista.com>
* Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef __ASM_HARDWARE_CP_INTC_H
#define __ASM_HARDWARE_CP_INTC_H
#define CP_INTC_REV 0x00
#define CP_INTC_CTRL 0x04
#define CP_INTC_HOST_CTRL 0x0C
#define CP_INTC_GLOBAL_ENABLE 0x10
#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C
#define CP_INTC_SYS_STAT_IDX_SET 0x20
#define CP_INTC_SYS_STAT_IDX_CLR 0x24
#define CP_INTC_SYS_ENABLE_IDX_SET 0x28
#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C
#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30
#define CP_INTC_HOST_ENABLE_IDX_SET 0x34
#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38
#define CP_INTC_PACING_PRESCALE 0x40
#define CP_INTC_VECTOR_BASE 0x50
#define CP_INTC_VECTOR_SIZE 0x54
#define CP_INTC_VECTOR_NULL 0x58
#define CP_INTC_PRIO_IDX 0x80
#define CP_INTC_PRIO_VECTOR 0x84
#define CP_INTC_SECURE_ENABLE 0x90
#define CP_INTC_SECURE_PRIO_IDX 0x94
#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4))
#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4))
#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4))
#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2))
#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2))
#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2))
#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2))
#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2))
#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2))
#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2))
#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2))
#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2))
#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2))
#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
void cp_intc_init(void);
int cp_intc_of_init(struct device_node *, struct device_node *);
#endif /* __ASM_HARDWARE_CP_INTC_H */

128
arch/arm/mach-davinci/da830.c
Просмотреть файл

@ -12,6 +12,7 @@
#include <linux/clk/davinci.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/irqchip/irq-davinci-cp-intc.h>
#include <linux/platform_data/gpio-davinci.h>
#include <asm/mach/map.h>
@ -19,9 +20,9 @@
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <mach/irqs.h>
#include <mach/time.h>
#include "irqs.h"
#include "mux.h"
/* Offsets of the 8 compare registers on the da830 */
@ -623,101 +624,6 @@ const short da830_eqep1_pins[] __initconst = {
-1
};
/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
[IRQ_DA8XX_COMMTX] = 7,
[IRQ_DA8XX_COMMRX] = 7,
[IRQ_DA8XX_NINT] = 7,
[IRQ_DA8XX_EVTOUT0] = 7,
[IRQ_DA8XX_EVTOUT1] = 7,
[IRQ_DA8XX_EVTOUT2] = 7,
[IRQ_DA8XX_EVTOUT3] = 7,
[IRQ_DA8XX_EVTOUT4] = 7,
[IRQ_DA8XX_EVTOUT5] = 7,
[IRQ_DA8XX_EVTOUT6] = 7,
[IRQ_DA8XX_EVTOUT7] = 7,
[IRQ_DA8XX_CCINT0] = 7,
[IRQ_DA8XX_CCERRINT] = 7,
[IRQ_DA8XX_TCERRINT0] = 7,
[IRQ_DA8XX_AEMIFINT] = 7,
[IRQ_DA8XX_I2CINT0] = 7,
[IRQ_DA8XX_MMCSDINT0] = 7,
[IRQ_DA8XX_MMCSDINT1] = 7,
[IRQ_DA8XX_ALLINT0] = 7,
[IRQ_DA8XX_RTC] = 7,
[IRQ_DA8XX_SPINT0] = 7,
[IRQ_DA8XX_TINT12_0] = 7,
[IRQ_DA8XX_TINT34_0] = 7,
[IRQ_DA8XX_TINT12_1] = 7,
[IRQ_DA8XX_TINT34_1] = 7,
[IRQ_DA8XX_UARTINT0] = 7,
[IRQ_DA8XX_KEYMGRINT] = 7,
[IRQ_DA830_MPUERR] = 7,
[IRQ_DA8XX_CHIPINT0] = 7,
[IRQ_DA8XX_CHIPINT1] = 7,
[IRQ_DA8XX_CHIPINT2] = 7,
[IRQ_DA8XX_CHIPINT3] = 7,
[IRQ_DA8XX_TCERRINT1] = 7,
[IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
[IRQ_DA8XX_C0_RX_PULSE] = 7,
[IRQ_DA8XX_C0_TX_PULSE] = 7,
[IRQ_DA8XX_C0_MISC_PULSE] = 7,
[IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
[IRQ_DA8XX_C1_RX_PULSE] = 7,
[IRQ_DA8XX_C1_TX_PULSE] = 7,
[IRQ_DA8XX_C1_MISC_PULSE] = 7,
[IRQ_DA8XX_MEMERR] = 7,
[IRQ_DA8XX_GPIO0] = 7,
[IRQ_DA8XX_GPIO1] = 7,
[IRQ_DA8XX_GPIO2] = 7,
[IRQ_DA8XX_GPIO3] = 7,
[IRQ_DA8XX_GPIO4] = 7,
[IRQ_DA8XX_GPIO5] = 7,
[IRQ_DA8XX_GPIO6] = 7,
[IRQ_DA8XX_GPIO7] = 7,
[IRQ_DA8XX_GPIO8] = 7,
[IRQ_DA8XX_I2CINT1] = 7,
[IRQ_DA8XX_LCDINT] = 7,
[IRQ_DA8XX_UARTINT1] = 7,
[IRQ_DA8XX_MCASPINT] = 7,
[IRQ_DA8XX_ALLINT1] = 7,
[IRQ_DA8XX_SPINT1] = 7,
[IRQ_DA8XX_UHPI_INT1] = 7,
[IRQ_DA8XX_USB_INT] = 7,
[IRQ_DA8XX_IRQN] = 7,
[IRQ_DA8XX_RWAKEUP] = 7,
[IRQ_DA8XX_UARTINT2] = 7,
[IRQ_DA8XX_DFTSSINT] = 7,
[IRQ_DA8XX_EHRPWM0] = 7,
[IRQ_DA8XX_EHRPWM0TZ] = 7,
[IRQ_DA8XX_EHRPWM1] = 7,
[IRQ_DA8XX_EHRPWM1TZ] = 7,
[IRQ_DA830_EHRPWM2] = 7,
[IRQ_DA830_EHRPWM2TZ] = 7,
[IRQ_DA8XX_ECAP0] = 7,
[IRQ_DA8XX_ECAP1] = 7,
[IRQ_DA8XX_ECAP2] = 7,
[IRQ_DA830_EQEP0] = 7,
[IRQ_DA830_EQEP1] = 7,
[IRQ_DA830_T12CMPINT0_0] = 7,
[IRQ_DA830_T12CMPINT1_0] = 7,
[IRQ_DA830_T12CMPINT2_0] = 7,
[IRQ_DA830_T12CMPINT3_0] = 7,
[IRQ_DA830_T12CMPINT4_0] = 7,
[IRQ_DA830_T12CMPINT5_0] = 7,
[IRQ_DA830_T12CMPINT6_0] = 7,
[IRQ_DA830_T12CMPINT7_0] = 7,
[IRQ_DA830_T12CMPINT0_1] = 7,
[IRQ_DA830_T12CMPINT1_1] = 7,
[IRQ_DA830_T12CMPINT2_1] = 7,
[IRQ_DA830_T12CMPINT3_1] = 7,
[IRQ_DA830_T12CMPINT4_1] = 7,
[IRQ_DA830_T12CMPINT5_1] = 7,
[IRQ_DA830_T12CMPINT6_1] = 7,
[IRQ_DA830_T12CMPINT7_1] = 7,
[IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
};
static struct map_desc da830_io_desc[] = {
{
.virtual = IO_VIRT,
@ -772,17 +678,17 @@ int __init da830_register_gpio(void)
static struct davinci_timer_instance da830_timer_instance[2] = {
{
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_0,
.top_irq = IRQ_DA8XX_TINT34_0,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
.cmp_off = DA830_CMP12_0,
.cmp_irq = IRQ_DA830_T12CMPINT0_0,
.cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0),
},
{
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_1,
.top_irq = IRQ_DA8XX_TINT34_1,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
.cmp_off = DA830_CMP12_0,
.cmp_irq = IRQ_DA830_T12CMPINT0_1,
.cmp_irq = DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_1),
},
};
@ -806,10 +712,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da830_pins,
.pinmux_pins_num = ARRAY_SIZE(da830_pins),
.intc_base = DA8XX_CP_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_CP_INTC,
.intc_irq_prios = da830_default_priorities,
.intc_irq_num = DA830_N_CP_INTC_IRQ,
.timer_info = &da830_timer_info,
.emac_pdata = &da8xx_emac_pdata,
};
@ -822,6 +724,20 @@ void __init da830_init(void)
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
}
static const struct davinci_cp_intc_config da830_cp_intc_config = {
.reg = {
.start = DA8XX_CP_INTC_BASE,
.end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
.flags = IORESOURCE_MEM,
},
.num_irqs = DA830_N_CP_INTC_IRQ,
};
void __init da830_init_irq(void)
{
davinci_cp_intc_init(&da830_cp_intc_config);
}
void __init da830_init_time(void)
{
void __iomem *pll;

154
arch/arm/mach-davinci/da850.c
Просмотреть файл

@ -18,6 +18,7 @@
#include <linux/cpufreq.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/irqchip/irq-davinci-cp-intc.h>
#include <linux/mfd/da8xx-cfgchip.h>
#include <linux/platform_data/clk-da8xx-cfgchip.h>
#include <linux/platform_data/clk-davinci-pll.h>
@ -32,10 +33,10 @@
#include <mach/cpufreq.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <mach/irqs.h>
#include <mach/pm.h>
#include <mach/time.h>
#include "irqs.h"
#include "mux.h"
#define DA850_PLL1_BASE 0x01e1a000
@ -298,111 +299,6 @@ const short da850_vpif_display_pins[] __initconst = {
-1
};
/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
[IRQ_DA8XX_COMMTX] = 7,
[IRQ_DA8XX_COMMRX] = 7,
[IRQ_DA8XX_NINT] = 7,
[IRQ_DA8XX_EVTOUT0] = 7,
[IRQ_DA8XX_EVTOUT1] = 7,
[IRQ_DA8XX_EVTOUT2] = 7,
[IRQ_DA8XX_EVTOUT3] = 7,
[IRQ_DA8XX_EVTOUT4] = 7,
[IRQ_DA8XX_EVTOUT5] = 7,
[IRQ_DA8XX_EVTOUT6] = 7,
[IRQ_DA8XX_EVTOUT7] = 7,
[IRQ_DA8XX_CCINT0] = 7,
[IRQ_DA8XX_CCERRINT] = 7,
[IRQ_DA8XX_TCERRINT0] = 7,
[IRQ_DA8XX_AEMIFINT] = 7,
[IRQ_DA8XX_I2CINT0] = 7,
[IRQ_DA8XX_MMCSDINT0] = 7,
[IRQ_DA8XX_MMCSDINT1] = 7,
[IRQ_DA8XX_ALLINT0] = 7,
[IRQ_DA8XX_RTC] = 7,
[IRQ_DA8XX_SPINT0] = 7,
[IRQ_DA8XX_TINT12_0] = 7,
[IRQ_DA8XX_TINT34_0] = 7,
[IRQ_DA8XX_TINT12_1] = 7,
[IRQ_DA8XX_TINT34_1] = 7,
[IRQ_DA8XX_UARTINT0] = 7,
[IRQ_DA8XX_KEYMGRINT] = 7,
[IRQ_DA850_MPUADDRERR0] = 7,
[IRQ_DA8XX_CHIPINT0] = 7,
[IRQ_DA8XX_CHIPINT1] = 7,
[IRQ_DA8XX_CHIPINT2] = 7,
[IRQ_DA8XX_CHIPINT3] = 7,
[IRQ_DA8XX_TCERRINT1] = 7,
[IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
[IRQ_DA8XX_C0_RX_PULSE] = 7,
[IRQ_DA8XX_C0_TX_PULSE] = 7,
[IRQ_DA8XX_C0_MISC_PULSE] = 7,
[IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
[IRQ_DA8XX_C1_RX_PULSE] = 7,
[IRQ_DA8XX_C1_TX_PULSE] = 7,
[IRQ_DA8XX_C1_MISC_PULSE] = 7,
[IRQ_DA8XX_MEMERR] = 7,
[IRQ_DA8XX_GPIO0] = 7,
[IRQ_DA8XX_GPIO1] = 7,
[IRQ_DA8XX_GPIO2] = 7,
[IRQ_DA8XX_GPIO3] = 7,
[IRQ_DA8XX_GPIO4] = 7,
[IRQ_DA8XX_GPIO5] = 7,
[IRQ_DA8XX_GPIO6] = 7,
[IRQ_DA8XX_GPIO7] = 7,
[IRQ_DA8XX_GPIO8] = 7,
[IRQ_DA8XX_I2CINT1] = 7,
[IRQ_DA8XX_LCDINT] = 7,
[IRQ_DA8XX_UARTINT1] = 7,
[IRQ_DA8XX_MCASPINT] = 7,
[IRQ_DA8XX_ALLINT1] = 7,
[IRQ_DA8XX_SPINT1] = 7,
[IRQ_DA8XX_UHPI_INT1] = 7,
[IRQ_DA8XX_USB_INT] = 7,
[IRQ_DA8XX_IRQN] = 7,
[IRQ_DA8XX_RWAKEUP] = 7,
[IRQ_DA8XX_UARTINT2] = 7,
[IRQ_DA8XX_DFTSSINT] = 7,
[IRQ_DA8XX_EHRPWM0] = 7,
[IRQ_DA8XX_EHRPWM0TZ] = 7,
[IRQ_DA8XX_EHRPWM1] = 7,
[IRQ_DA8XX_EHRPWM1TZ] = 7,
[IRQ_DA850_SATAINT] = 7,
[IRQ_DA850_TINTALL_2] = 7,
[IRQ_DA8XX_ECAP0] = 7,
[IRQ_DA8XX_ECAP1] = 7,
[IRQ_DA8XX_ECAP2] = 7,
[IRQ_DA850_MMCSDINT0_1] = 7,
[IRQ_DA850_MMCSDINT1_1] = 7,
[IRQ_DA850_T12CMPINT0_2] = 7,
[IRQ_DA850_T12CMPINT1_2] = 7,
[IRQ_DA850_T12CMPINT2_2] = 7,
[IRQ_DA850_T12CMPINT3_2] = 7,
[IRQ_DA850_T12CMPINT4_2] = 7,
[IRQ_DA850_T12CMPINT5_2] = 7,
[IRQ_DA850_T12CMPINT6_2] = 7,
[IRQ_DA850_T12CMPINT7_2] = 7,
[IRQ_DA850_T12CMPINT0_3] = 7,
[IRQ_DA850_T12CMPINT1_3] = 7,
[IRQ_DA850_T12CMPINT2_3] = 7,
[IRQ_DA850_T12CMPINT3_3] = 7,
[IRQ_DA850_T12CMPINT4_3] = 7,
[IRQ_DA850_T12CMPINT5_3] = 7,
[IRQ_DA850_T12CMPINT6_3] = 7,
[IRQ_DA850_T12CMPINT7_3] = 7,
[IRQ_DA850_RPIINT] = 7,
[IRQ_DA850_VPIFINT] = 7,
[IRQ_DA850_CCINT1] = 7,
[IRQ_DA850_CCERRINT1] = 7,
[IRQ_DA850_TCERRINT2] = 7,
[IRQ_DA850_TINTALL_3] = 7,
[IRQ_DA850_MCBSP0RINT] = 7,
[IRQ_DA850_MCBSP0XINT] = 7,
[IRQ_DA850_MCBSP1RINT] = 7,
[IRQ_DA850_MCBSP1XINT] = 7,
[IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
};
static struct map_desc da850_io_desc[] = {
{
.virtual = IO_VIRT,
@ -439,23 +335,23 @@ static struct davinci_id da850_ids[] = {
static struct davinci_timer_instance da850_timer_instance[4] = {
{
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_0,
.top_irq = IRQ_DA8XX_TINT34_0,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
},
{
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = IRQ_DA8XX_TINT12_1,
.top_irq = IRQ_DA8XX_TINT34_1,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
},
{
.base = DA850_TIMER64P2_BASE,
.bottom_irq = IRQ_DA850_TINT12_2,
.top_irq = IRQ_DA850_TINT34_2,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2),
},
{
.base = DA850_TIMER64P3_BASE,
.bottom_irq = IRQ_DA850_TINT12_3,
.top_irq = IRQ_DA850_TINT34_3,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3),
},
};
@ -658,8 +554,8 @@ static struct platform_device da850_vpif_dev = {
static struct resource da850_vpif_display_resource[] = {
{
.start = IRQ_DA850_VPIFINT,
.end = IRQ_DA850_VPIFINT,
.start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
.end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
.flags = IORESOURCE_IRQ,
},
};
@ -677,13 +573,13 @@ static struct platform_device da850_vpif_display_dev = {
static struct resource da850_vpif_capture_resource[] = {
{
.start = IRQ_DA850_VPIFINT,
.end = IRQ_DA850_VPIFINT,
.start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
.end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA850_VPIFINT,
.end = IRQ_DA850_VPIFINT,
.start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
.end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
.flags = IORESOURCE_IRQ,
},
};
@ -738,10 +634,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da850_pins,
.pinmux_pins_num = ARRAY_SIZE(da850_pins),
.intc_base = DA8XX_CP_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_CP_INTC,
.intc_irq_prios = da850_default_priorities,
.intc_irq_num = DA850_N_CP_INTC_IRQ,
.timer_info = &da850_timer_info,
.emac_pdata = &da8xx_emac_pdata,
.sram_dma = DA8XX_SHARED_RAM_BASE,
@ -760,6 +652,20 @@ void __init da850_init(void)
WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
}
static const struct davinci_cp_intc_config da850_cp_intc_config = {
.reg = {
.start = DA8XX_CP_INTC_BASE,
.end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
.flags = IORESOURCE_MEM,
},
.num_irqs = DA850_N_CP_INTC_IRQ,
};
void __init da850_init_irq(void)
{
davinci_cp_intc_init(&da850_cp_intc_config);
}
void __init da850_init_time(void)
{
void __iomem *pll0;

4
arch/arm/mach-davinci/davinci.h
Просмотреть файл

@ -88,6 +88,7 @@ int davinci_init_wdt(void);
/* DM355 function declarations */
void dm355_init(void);
void dm355_init_time(void);
void dm355_init_irq(void);
void dm355_register_clocks(void);
void dm355_init_spi0(unsigned chipselect_mask,
const struct spi_board_info *info, unsigned len);
@ -97,6 +98,7 @@ int dm355_gpio_register(void);
/* DM365 function declarations */
void dm365_init(void);
void dm365_init_irq(void);
void dm365_init_time(void);
void dm365_register_clocks(void);
void dm365_init_asp(void);
@ -110,6 +112,7 @@ int dm365_gpio_register(void);
/* DM644x function declarations */
void dm644x_init(void);
void dm644x_init_irq(void);
void dm644x_init_devices(void);
void dm644x_init_time(void);
void dm644x_register_clocks(void);
@ -119,6 +122,7 @@ int dm644x_gpio_register(void);
/* DM646x function declarations */
void dm646x_init(void);
void dm646x_init_irq(void);
void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
void dm646x_register_clocks(void);
void dm646x_init_mcasp0(struct snd_platform_data *pdata);

147
arch/arm/mach-davinci/devices-da8xx.c
Просмотреть файл

@ -28,6 +28,7 @@
#include "asp.h"
#include "cpuidle.h"
#include "irqs.h"
#include "sram.h"
#define DA8XX_TPCC_BASE 0x01c00000
@ -64,7 +65,7 @@ void __iomem *da8xx_syscfg1_base;
static struct plat_serial8250_port da8xx_serial0_pdata[] = {
{
.mapbase = DA8XX_UART0_BASE,
.irq = IRQ_DA8XX_UARTINT0,
.irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -77,7 +78,7 @@ static struct plat_serial8250_port da8xx_serial0_pdata[] = {
static struct plat_serial8250_port da8xx_serial1_pdata[] = {
{
.mapbase = DA8XX_UART1_BASE,
.irq = IRQ_DA8XX_UARTINT1,
.irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -90,7 +91,7 @@ static struct plat_serial8250_port da8xx_serial1_pdata[] = {
static struct plat_serial8250_port da8xx_serial2_pdata[] = {
{
.mapbase = DA8XX_UART2_BASE,
.irq = IRQ_DA8XX_UARTINT2,
.irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -171,12 +172,12 @@ static struct resource da8xx_edma0_resources[] = {
},
{
.name = "edma3_ccint",
.start = IRQ_DA8XX_CCINT0,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
.flags = IORESOURCE_IRQ,
},
{
.name = "edma3_ccerrint",
.start = IRQ_DA8XX_CCERRINT,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
.flags = IORESOURCE_IRQ,
},
};
@ -196,12 +197,12 @@ static struct resource da850_edma1_resources[] = {
},
{
.name = "edma3_ccint",
.start = IRQ_DA850_CCINT1,
.start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
.flags = IORESOURCE_IRQ,
},
{
.name = "edma3_ccerrint",
.start = IRQ_DA850_CCERRINT1,
.start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
.flags = IORESOURCE_IRQ,
},
};
@ -306,8 +307,8 @@ static struct resource da8xx_i2c_resources0[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA8XX_I2CINT0,
.end = IRQ_DA8XX_I2CINT0,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
.flags = IORESOURCE_IRQ,
},
};
@ -326,8 +327,8 @@ static struct resource da8xx_i2c_resources1[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA8XX_I2CINT1,
.end = IRQ_DA8XX_I2CINT1,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
.flags = IORESOURCE_IRQ,
},
};
@ -382,23 +383,23 @@ static struct resource da8xx_emac_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
.end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_C0_RX_PULSE,
.end = IRQ_DA8XX_C0_RX_PULSE,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_C0_TX_PULSE,
.end = IRQ_DA8XX_C0_TX_PULSE,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_C0_MISC_PULSE,
.end = IRQ_DA8XX_C0_MISC_PULSE,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
.flags = IORESOURCE_IRQ,
},
};
@ -470,7 +471,7 @@ static struct resource da830_mcasp1_resources[] = {
},
{
.name = "common",
.start = IRQ_DA8XX_MCASPINT,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
.flags = IORESOURCE_IRQ,
},
};
@ -505,7 +506,7 @@ static struct resource da830_mcasp2_resources[] = {
},
{
.name = "common",
.start = IRQ_DA8XX_MCASPINT,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
.flags = IORESOURCE_IRQ,
},
};
@ -540,7 +541,7 @@ static struct resource da850_mcasp_resources[] = {
},
{
.name = "common",
.start = IRQ_DA8XX_MCASPINT,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
.flags = IORESOURCE_IRQ,
},
};
@ -588,43 +589,43 @@ static struct resource da8xx_pruss_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA8XX_EVTOUT0,
.end = IRQ_DA8XX_EVTOUT0,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_EVTOUT1,
.end = IRQ_DA8XX_EVTOUT1,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_EVTOUT2,
.end = IRQ_DA8XX_EVTOUT2,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_EVTOUT3,
.end = IRQ_DA8XX_EVTOUT3,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_EVTOUT4,
.end = IRQ_DA8XX_EVTOUT4,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_EVTOUT5,
.end = IRQ_DA8XX_EVTOUT5,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_EVTOUT6,
.end = IRQ_DA8XX_EVTOUT6,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_EVTOUT7,
.end = IRQ_DA8XX_EVTOUT7,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
.flags = IORESOURCE_IRQ,
},
};
@ -674,8 +675,8 @@ static struct resource da8xx_lcdc_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = { /* interrupt */
.start = IRQ_DA8XX_LCDINT,
.end = IRQ_DA8XX_LCDINT,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
.flags = IORESOURCE_IRQ,
},
};
@ -700,48 +701,48 @@ static struct resource da8xx_gpio_resources[] = {
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
.start = IRQ_DA8XX_GPIO0,
.end = IRQ_DA8XX_GPIO0,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO1,
.end = IRQ_DA8XX_GPIO1,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO2,
.end = IRQ_DA8XX_GPIO2,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO3,
.end = IRQ_DA8XX_GPIO3,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO4,
.end = IRQ_DA8XX_GPIO4,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO5,
.end = IRQ_DA8XX_GPIO5,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO6,
.end = IRQ_DA8XX_GPIO6,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO7,
.end = IRQ_DA8XX_GPIO7,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA8XX_GPIO8,
.end = IRQ_DA8XX_GPIO8,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
.flags = IORESOURCE_IRQ,
},
};
@ -766,8 +767,8 @@ static struct resource da8xx_mmcsd0_resources[] = {
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
.start = IRQ_DA8XX_MMCSDINT0,
.end = IRQ_DA8XX_MMCSDINT0,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
.flags = IORESOURCE_IRQ,
},
};
@ -793,8 +794,8 @@ static struct resource da850_mmcsd1_resources[] = {
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
.start = IRQ_DA850_MMCSDINT0_1,
.end = IRQ_DA850_MMCSDINT0_1,
.start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
.end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
.flags = IORESOURCE_IRQ,
},
};
@ -845,8 +846,8 @@ static struct resource da8xx_rproc_resources[] = {
.flags = IORESOURCE_MEM,
},
{ /* dsp irq */
.start = IRQ_DA8XX_CHIPINT0,
.end = IRQ_DA8XX_CHIPINT0,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
.flags = IORESOURCE_IRQ,
},
};
@ -936,13 +937,13 @@ static struct resource da8xx_rtc_resources[] = {
.flags = IORESOURCE_MEM,
},
{ /* timer irq */
.start = IRQ_DA8XX_RTC,
.end = IRQ_DA8XX_RTC,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
.flags = IORESOURCE_IRQ,
},
{ /* alarm irq */
.start = IRQ_DA8XX_RTC,
.end = IRQ_DA8XX_RTC,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
.flags = IORESOURCE_IRQ,
},
};
@ -1009,8 +1010,8 @@ static struct resource da8xx_spi0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DA8XX_SPINT0,
.end = IRQ_DA8XX_SPINT0,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
.flags = IORESOURCE_IRQ,
},
};
@ -1022,8 +1023,8 @@ static struct resource da8xx_spi1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DA8XX_SPINT1,
.end = IRQ_DA8XX_SPINT1,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
.flags = IORESOURCE_IRQ,
},
};
@ -1103,7 +1104,7 @@ static struct resource da850_sata_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA850_SATAINT,
.start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
.flags = IORESOURCE_IRQ,
},
};

40
arch/arm/mach-davinci/devices.c
Просмотреть файл

@ -11,21 +11,20 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/platform_data/i2c-davinci.h>
#include <linux/platform_data/mmc-davinci.h>
#include <linux/platform_data/edma.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/reboot.h>
#include <mach/hardware.h>
#include <linux/platform_data/i2c-davinci.h>
#include <mach/irqs.h>
#include <mach/cputype.h>
#include <mach/mux.h>
#include <linux/platform_data/mmc-davinci.h>
#include <mach/time.h>
#include <linux/platform_data/edma.h>
#include "davinci.h"
#include "irqs.h"
#define DAVINCI_I2C_BASE 0x01C21000
#define DAVINCI_ATA_BASE 0x01C66000
@ -56,7 +55,7 @@ static struct resource i2c_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_I2C,
.start = DAVINCI_INTC_IRQ(IRQ_I2C),
.flags = IORESOURCE_IRQ,
},
};
@ -84,8 +83,8 @@ static struct resource ide_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_IDE,
.end = IRQ_IDE,
.start = DAVINCI_INTC_IRQ(IRQ_IDE),
.end = DAVINCI_INTC_IRQ(IRQ_IDE),
.flags = IORESOURCE_IRQ,
},
};
@ -133,11 +132,11 @@ static struct resource mmcsd0_resources[] = {
},
/* IRQs: MMC/SD, then SDIO */
{
.start = IRQ_MMCINT,
.start = DAVINCI_INTC_IRQ(IRQ_MMCINT),
.flags = IORESOURCE_IRQ,
}, {
/* different on dm355 */
.start = IRQ_SDIOINT,
.start = DAVINCI_INTC_IRQ(IRQ_SDIOINT),
.flags = IORESOURCE_IRQ,
},
};
@ -163,10 +162,10 @@ static struct resource mmcsd1_resources[] = {
},
/* IRQs: MMC/SD, then SDIO */
{
.start = IRQ_DM355_MMCINT1,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_MMCINT1),
.flags = IORESOURCE_IRQ,
}, {
.start = IRQ_DM355_SDIOINT1,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_SDIOINT1),
.flags = IORESOURCE_IRQ,
},
};
@ -219,7 +218,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
SZ_4K - 1;
mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
mmcsd1_resources[2].start = DAVINCI_INTC_IRQ(
IRQ_DM365_SDIOINT1);
davinci_mmcsd1_device.name = "da830-mmc";
} else
break;
@ -230,7 +230,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
if (cpu_is_davinci_dm355()) {
mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
IRQ_DM355_SDIOINT0);
/* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
davinci_cfg_reg(DM355_MMCSD0);
@ -241,7 +242,8 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
mmcsd0_resources[2].start = DAVINCI_INTC_IRQ(
IRQ_DM365_SDIOINT0);
davinci_mmcsd0_device.name = "da830-mmc";
} else if (cpu_is_davinci_dm644x()) {
/* REVISIT: should this be in board-init code? */
@ -313,13 +315,13 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata)
struct davinci_timer_instance davinci_timer_instance[2] = {
{
.base = DAVINCI_TIMER0_BASE,
.bottom_irq = IRQ_TINT0_TINT12,
.top_irq = IRQ_TINT0_TINT34,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12),
.top_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34),
},
{
.base = DAVINCI_TIMER1_BASE,
.bottom_irq = IRQ_TINT1_TINT12,
.top_irq = IRQ_TINT1_TINT34,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT12),
.top_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34),
},
};

78
arch/arm/mach-davinci/dm355.c
Просмотреть файл

@ -15,6 +15,7 @@
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/init.h>
#include <linux/irqchip/irq-davinci-aintc.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_data/spi-davinci.h>
@ -26,13 +27,13 @@
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/irqs.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include "asp.h"
#include "davinci.h"
#include "irqs.h"
#include "mux.h"
#define DM355_UART2_BASE (IO_PHYS + 0x206000)
@ -53,7 +54,7 @@ static struct resource dm355_spi0_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DM355_SPINT0_0,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
.flags = IORESOURCE_IRQ,
},
};
@ -273,12 +274,12 @@ static struct resource edma_resources[] = {
},
{
.name = "edma3_ccint",
.start = IRQ_CCINT0,
.start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
.flags = IORESOURCE_IRQ,
},
{
.name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
.flags = IORESOURCE_IRQ,
},
/* not using (or muxing) TC*_ERR */
@ -358,13 +359,13 @@ static struct platform_device dm355_vpss_device = {
static struct resource vpfe_resources[] = {
{
.start = IRQ_VDINT0,
.end = IRQ_VDINT0,
.start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
.end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_VDINT1,
.end = IRQ_VDINT1,
.start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
.end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
.flags = IORESOURCE_IRQ,
},
};
@ -422,8 +423,8 @@ static struct platform_device dm355_osd_dev = {
static struct resource dm355_venc_resources[] = {
{
.start = IRQ_VENCINT,
.end = IRQ_VENCINT,
.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.flags = IORESOURCE_IRQ,
},
/* venc registers io space */
@ -442,8 +443,8 @@ static struct resource dm355_venc_resources[] = {
static struct resource dm355_v4l2_disp_resources[] = {
{
.start = IRQ_VENCINT,
.end = IRQ_VENCINT,
.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.flags = IORESOURCE_IRQ,
},
/* venc registers io space */
@ -547,38 +548,38 @@ static struct resource dm355_gpio_resources[] = {
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
.start = IRQ_DM355_GPIOBNK0,
.end = IRQ_DM355_GPIOBNK0,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK1,
.end = IRQ_DM355_GPIOBNK1,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK2,
.end = IRQ_DM355_GPIOBNK2,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK3,
.end = IRQ_DM355_GPIOBNK3,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK4,
.end = IRQ_DM355_GPIOBNK4,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK5,
.end = IRQ_DM355_GPIOBNK5,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM355_GPIOBNK6,
.end = IRQ_DM355_GPIOBNK6,
.start = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
.end = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
.flags = IORESOURCE_IRQ,
},
};
@ -632,7 +633,7 @@ static struct davinci_timer_info dm355_timer_info = {
static struct plat_serial8250_port dm355_serial0_platform_data[] = {
{
.mapbase = DAVINCI_UART0_BASE,
.irq = IRQ_UARTINT0,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -645,7 +646,7 @@ static struct plat_serial8250_port dm355_serial0_platform_data[] = {
static struct plat_serial8250_port dm355_serial1_platform_data[] = {
{
.mapbase = DAVINCI_UART1_BASE,
.irq = IRQ_UARTINT1,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -658,7 +659,7 @@ static struct plat_serial8250_port dm355_serial1_platform_data[] = {
static struct plat_serial8250_port dm355_serial2_platform_data[] = {
{
.mapbase = DM355_UART2_BASE,
.irq = IRQ_DM355_UARTINT2,
.irq = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -704,10 +705,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm355_pins,
.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
.intc_base = DAVINCI_ARM_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_AINTC,
.intc_irq_prios = dm355_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm355_timer_info,
.sram_dma = 0x00010000,
.sram_len = SZ_32K,
@ -793,6 +790,21 @@ int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
return 0;
}
static const struct davinci_aintc_config dm355_aintc_config = {
.reg = {
.start = DAVINCI_ARM_INTC_BASE,
.end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.num_irqs = 64,
.prios = dm355_default_priorities,
};
void __init dm355_init_irq(void)
{
davinci_aintc_init(&dm355_aintc_config);
}
static int __init dm355_init_devices(void)
{
struct platform_device *edma_pdev;

102
arch/arm/mach-davinci/dm365.c
Просмотреть файл

@ -19,6 +19,7 @@
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/init.h>
#include <linux/irqchip/irq-davinci-aintc.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_data/keyscan-davinci.h>
@ -31,13 +32,13 @@
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/irqs.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include "asp.h"
#include "davinci.h"
#include "irqs.h"
#include "mux.h"
#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
@ -224,7 +225,7 @@ static struct resource dm365_spi0_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DM365_SPIINT0_0,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
.flags = IORESOURCE_IRQ,
},
};
@ -266,43 +267,43 @@ static struct resource dm365_gpio_resources[] = {
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
.start = IRQ_DM365_GPIO0,
.end = IRQ_DM365_GPIO0,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO1,
.end = IRQ_DM365_GPIO1,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO2,
.end = IRQ_DM365_GPIO2,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO3,
.end = IRQ_DM365_GPIO3,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO4,
.end = IRQ_DM365_GPIO4,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO5,
.end = IRQ_DM365_GPIO5,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO6,
.end = IRQ_DM365_GPIO6,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_GPIO7,
.end = IRQ_DM365_GPIO7,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
.flags = IORESOURCE_IRQ,
},
};
@ -336,23 +337,23 @@ static struct resource dm365_emac_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DM365_EMAC_RXTHRESH,
.end = IRQ_DM365_EMAC_RXTHRESH,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_EMAC_RXPULSE,
.end = IRQ_DM365_EMAC_RXPULSE,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_EMAC_TXPULSE,
.end = IRQ_DM365_EMAC_TXPULSE,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM365_EMAC_MISCPULSE,
.end = IRQ_DM365_EMAC_MISCPULSE,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
.flags = IORESOURCE_IRQ,
},
};
@ -518,12 +519,12 @@ static struct resource edma_resources[] = {
},
{
.name = "edma3_ccint",
.start = IRQ_CCINT0,
.start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
.flags = IORESOURCE_IRQ,
},
{
.name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
.flags = IORESOURCE_IRQ,
},
/* not using TC*_ERR */
@ -597,7 +598,7 @@ static struct resource dm365_rtc_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DM365_RTCINT,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
.flags = IORESOURCE_IRQ,
},
};
@ -627,8 +628,8 @@ static struct resource dm365_ks_resources[] = {
},
{
/* interrupt */
.start = IRQ_DM365_KEYINT,
.end = IRQ_DM365_KEYINT,
.start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
.end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
.flags = IORESOURCE_IRQ,
},
};
@ -669,7 +670,7 @@ static struct davinci_timer_info dm365_timer_info = {
static struct plat_serial8250_port dm365_serial0_platform_data[] = {
{
.mapbase = DAVINCI_UART0_BASE,
.irq = IRQ_UARTINT0,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -682,7 +683,7 @@ static struct plat_serial8250_port dm365_serial0_platform_data[] = {
static struct plat_serial8250_port dm365_serial1_platform_data[] = {
{
.mapbase = DM365_UART1_BASE,
.irq = IRQ_UARTINT1,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -721,10 +722,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm365_pins,
.pinmux_pins_num = ARRAY_SIZE(dm365_pins),
.intc_base = DAVINCI_ARM_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_AINTC,
.intc_irq_prios = dm365_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm365_timer_info,
.emac_pdata = &dm365_emac_pdata,
.sram_dma = 0x00010000,
@ -822,13 +819,13 @@ static struct platform_device dm365_vpss_device = {
static struct resource vpfe_resources[] = {
{
.start = IRQ_VDINT0,
.end = IRQ_VDINT0,
.start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
.end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_VDINT1,
.end = IRQ_VDINT1,
.start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
.end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
.flags = IORESOURCE_IRQ,
},
};
@ -909,8 +906,8 @@ static struct platform_device dm365_osd_dev = {
static struct resource dm365_venc_resources[] = {
{
.start = IRQ_VENCINT,
.end = IRQ_VENCINT,
.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.flags = IORESOURCE_IRQ,
},
/* venc registers io space */
@ -929,8 +926,8 @@ static struct resource dm365_venc_resources[] = {
static struct resource dm365_v4l2_disp_resources[] = {
{
.start = IRQ_VENCINT,
.end = IRQ_VENCINT,
.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.flags = IORESOURCE_IRQ,
},
/* venc registers io space */
@ -1052,6 +1049,21 @@ int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
return 0;
}
static const struct davinci_aintc_config dm365_aintc_config = {
.reg = {
.start = DAVINCI_ARM_INTC_BASE,
.end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.num_irqs = 64,
.prios = dm365_default_priorities,
};
void __init dm365_init_irq(void)
{
davinci_aintc_init(&dm365_aintc_config);
}
static int __init dm365_init_devices(void)
{
struct platform_device *edma_pdev;

68
arch/arm/mach-davinci/dm644x.c
Просмотреть файл

@ -14,6 +14,7 @@
#include <linux/clkdev.h>
#include <linux/dmaengine.h>
#include <linux/init.h>
#include <linux/irqchip/irq-davinci-aintc.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_device.h>
@ -23,13 +24,13 @@
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/irqs.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include "asp.h"
#include "davinci.h"
#include "irqs.h"
#include "mux.h"
/*
@ -59,8 +60,8 @@ static struct resource dm644x_emac_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_EMACINT,
.end = IRQ_EMACINT,
.start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
.end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
.flags = IORESOURCE_IRQ,
},
};
@ -260,12 +261,12 @@ static struct resource edma_resources[] = {
},
{
.name = "edma3_ccint",
.start = IRQ_CCINT0,
.start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
.flags = IORESOURCE_IRQ,
},
{
.name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
.flags = IORESOURCE_IRQ,
},
/* not using TC*_ERR */
@ -330,13 +331,13 @@ static struct platform_device dm644x_vpss_device = {
static struct resource dm644x_vpfe_resources[] = {
{
.start = IRQ_VDINT0,
.end = IRQ_VDINT0,
.start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
.end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_VDINT1,
.end = IRQ_VDINT1,
.start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
.end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
.flags = IORESOURCE_IRQ,
},
};
@ -442,8 +443,8 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
static struct resource dm644x_v4l2_disp_resources[] = {
{
.start = IRQ_VENCINT,
.end = IRQ_VENCINT,
.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.flags = IORESOURCE_IRQ,
},
};
@ -491,28 +492,28 @@ static struct resource dm644_gpio_resources[] = {
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
.start = IRQ_GPIOBNK0,
.end = IRQ_GPIOBNK0,
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_GPIOBNK1,
.end = IRQ_GPIOBNK1,
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_GPIOBNK2,
.end = IRQ_GPIOBNK2,
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_GPIOBNK3,
.end = IRQ_GPIOBNK3,
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_GPIOBNK4,
.end = IRQ_GPIOBNK4,
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
.flags = IORESOURCE_IRQ,
},
};
@ -573,7 +574,7 @@ static struct davinci_timer_info dm644x_timer_info = {
static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
{
.mapbase = DAVINCI_UART0_BASE,
.irq = IRQ_UARTINT0,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -586,7 +587,7 @@ static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
{
.mapbase = DAVINCI_UART1_BASE,
.irq = IRQ_UARTINT1,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -599,7 +600,7 @@ static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
{
.mapbase = DAVINCI_UART2_BASE,
.irq = IRQ_UARTINT2,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@ -645,10 +646,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm644x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
.intc_base = DAVINCI_ARM_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_AINTC,
.intc_irq_prios = dm644x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm644x_timer_info,
.emac_pdata = &dm644x_emac_pdata,
.sram_dma = 0x00008000,
@ -729,6 +726,21 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
return 0;
}
static const struct davinci_aintc_config dm644x_aintc_config = {
.reg = {
.start = DAVINCI_ARM_INTC_BASE,
.end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.num_irqs = 64,
.prios = dm644x_default_priorities,
};
void __init dm644x_init_irq(void)
{
davinci_aintc_init(&dm644x_aintc_config);
}
void __init dm644x_init_devices(void)
{
struct platform_device *edma_pdev;

82
arch/arm/mach-davinci/dm646x.c
Просмотреть файл

@ -15,6 +15,7 @@
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/init.h>
#include <linux/irqchip/irq-davinci-aintc.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_device.h>
@ -24,13 +25,13 @@
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/irqs.h>
#include <mach/mux.h>
#include <mach/serial.h>
#include <mach/time.h>
#include "asp.h"
#include "davinci.h"
#include "irqs.h"
#include "mux.h"
#define DAVINCI_VPIF_BASE (0x01C12000)
@ -62,23 +63,23 @@ static struct resource dm646x_emac_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DM646X_EMACRXTHINT,
.end = IRQ_DM646X_EMACRXTHINT,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM646X_EMACRXINT,
.end = IRQ_DM646X_EMACRXINT,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM646X_EMACTXINT,
.end = IRQ_DM646X_EMACTXINT,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM646X_EMACMISCINT,
.end = IRQ_DM646X_EMACMISCINT,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
.flags = IORESOURCE_IRQ,
},
};
@ -273,12 +274,12 @@ static struct resource edma_resources[] = {
},
{
.name = "edma3_ccint",
.start = IRQ_CCINT0,
.start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
.flags = IORESOURCE_IRQ,
},
{
.name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
.flags = IORESOURCE_IRQ,
},
/* not using TC*_ERR */
@ -315,12 +316,12 @@ static struct resource dm646x_mcasp0_resources[] = {
},
{
.name = "tx",
.start = IRQ_DM646X_MCASP0TXINT,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = IRQ_DM646X_MCASP0RXINT,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
.flags = IORESOURCE_IRQ,
},
};
@ -341,7 +342,7 @@ static struct resource dm646x_mcasp1_resources[] = {
},
{
.name = "tx",
.start = IRQ_DM646X_MCASP1TXINT,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
.flags = IORESOURCE_IRQ,
},
};
@ -388,13 +389,13 @@ static struct platform_device vpif_dev = {
static struct resource vpif_display_resource[] = {
{
.start = IRQ_DM646X_VP_VERTINT2,
.end = IRQ_DM646X_VP_VERTINT2,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM646X_VP_VERTINT3,
.end = IRQ_DM646X_VP_VERTINT3,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
.flags = IORESOURCE_IRQ,
},
};
@ -412,13 +413,13 @@ static struct platform_device vpif_display_dev = {
static struct resource vpif_capture_resource[] = {
{
.start = IRQ_DM646X_VP_VERTINT0,
.end = IRQ_DM646X_VP_VERTINT0,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM646X_VP_VERTINT1,
.end = IRQ_DM646X_VP_VERTINT1,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
.flags = IORESOURCE_IRQ,
},
};
@ -441,18 +442,18 @@ static struct resource dm646x_gpio_resources[] = {
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
.start = IRQ_DM646X_GPIOBNK0,
.end = IRQ_DM646X_GPIOBNK0,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM646X_GPIOBNK1,
.end = IRQ_DM646X_GPIOBNK1,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DM646X_GPIOBNK2,
.end = IRQ_DM646X_GPIOBNK2,
.start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
.end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
.flags = IORESOURCE_IRQ,
},
};
@ -513,7 +514,7 @@ static struct davinci_timer_info dm646x_timer_info = {
static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
{
.mapbase = DAVINCI_UART0_BASE,
.irq = IRQ_UARTINT0,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM32,
@ -526,7 +527,7 @@ static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
{
.mapbase = DAVINCI_UART1_BASE,
.irq = IRQ_UARTINT1,
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM32,
@ -539,7 +540,7 @@ static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
{
.mapbase = DAVINCI_UART2_BASE,
.irq = IRQ_DM646X_UARTINT2,
.irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM32,
@ -585,10 +586,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = {
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm646x_pins,
.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
.intc_base = DAVINCI_ARM_INTC_BASE,
.intc_type = DAVINCI_INTC_TYPE_AINTC,
.intc_irq_prios = dm646x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm646x_timer_info,
.emac_pdata = &dm646x_emac_pdata,
.sram_dma = 0x10010000,
@ -690,6 +687,21 @@ void __init dm646x_register_clocks(void)
platform_device_register(&dm646x_pll2_device);
}
static const struct davinci_aintc_config dm646x_aintc_config = {
.reg = {
.start = DAVINCI_ARM_INTC_BASE,
.end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
.num_irqs = 64,
.prios = dm646x_default_priorities,
};
void __init dm646x_init_irq(void)
{
davinci_aintc_init(&dm646x_aintc_config);
}
static int __init dm646x_init_devices(void)
{
int ret = 0;

14
arch/arm/mach-davinci/include/mach/common.h
Просмотреть файл

@ -17,11 +17,12 @@
#include <linux/types.h>
#include <linux/reboot.h>
void davinci_timer_init(struct clk *clk);
#include <asm/irq.h>
extern void davinci_irq_init(void);
extern void __iomem *davinci_intc_base;
extern int davinci_intc_type;
#define DAVINCI_INTC_START NR_IRQS
#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
void davinci_timer_init(struct clk *clk);
struct davinci_timer_instance {
u32 base;
@ -57,11 +58,6 @@ struct davinci_soc_info {
u32 pinmux_base;
const struct mux_config *pinmux_pins;
unsigned long pinmux_pins_num;
u32 intc_base;
int intc_type;
u8 *intc_irq_prios;
unsigned long intc_irq_num;
u32 *intc_host_map;
struct davinci_timer_info *timer_info;
int gpio_type;
u32 gpio_base;

2
arch/arm/mach-davinci/include/mach/da8xx.h
Просмотреть файл

@ -88,10 +88,12 @@ extern unsigned int da850_max_speed;
#define DA8XX_ARM_RAM_BASE 0xffff0000
void da830_init(void);
void da830_init_irq(void);
void da830_init_time(void);
void da830_register_clocks(void);
void da850_init(void);
void da850_init_irq(void);
void da850_init_time(void);
void da850_register_clocks(void);

39
arch/arm/mach-davinci/include/mach/entry-macro.S
Просмотреть файл

@ -1,39 +0,0 @@
/*
* Low-level IRQ helper macros for TI DaVinci-based platforms
*
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
*
* 2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <mach/irqs.h>
.macro get_irqnr_preamble, base, tmp
ldr \base, =davinci_intc_base
ldr \base, [\base]
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
ldr \tmp, =davinci_intc_type
ldr \tmp, [\tmp]
cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
beq 1001f
#endif
#if defined(CONFIG_AINTC)
ldr \tmp, [\base, #0x14]
movs \tmp, \tmp, lsr #2
sub \irqnr, \tmp, #1
b 1002f
#endif
#if defined(CONFIG_CP_INTC)
1001: ldr \irqnr, [\base, #0x80] /* get irq number */
mov \tmp, \irqnr, lsr #31
and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */
and \tmp, \tmp, #0x1
cmp \tmp, #0x1
#endif
1002:
.endm

117
arch/arm/mach-davinci/irq.c
Просмотреть файл

@ -1,117 +0,0 @@
/*
* Interrupt handler for DaVinci boards.
*
* Copyright (C) 2006 Texas Instruments.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/cputype.h>
#include <mach/common.h>
#include <asm/mach/irq.h>
#define FIQ_REG0_OFFSET 0x0000
#define FIQ_REG1_OFFSET 0x0004
#define IRQ_REG0_OFFSET 0x0008
#define IRQ_REG1_OFFSET 0x000C
#define IRQ_ENT_REG0_OFFSET 0x0018
#define IRQ_ENT_REG1_OFFSET 0x001C
#define IRQ_INCTL_REG_OFFSET 0x0020
#define IRQ_EABASE_REG_OFFSET 0x0024
#define IRQ_INTPRI0_REG_OFFSET 0x0030
#define IRQ_INTPRI7_REG_OFFSET 0x004C
static inline void davinci_irq_writel(unsigned long value, int offset)
{
__raw_writel(value, davinci_intc_base + offset);
}
static __init void
davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
if (!gc) {
pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
__func__, irq_start);
return;
}
ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->regs.ack = IRQ_REG0_OFFSET;
ct->regs.mask = IRQ_ENT_REG0_OFFSET;
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}
/* ARM Interrupt Controller Initialization */
void __init davinci_irq_init(void)
{
unsigned i, j;
const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
if (WARN_ON(!davinci_intc_base))
return;
/* Clear all interrupt requests */
davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
/* Disable all interrupts */
davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
/* Interrupts disabled immediately, IRQ entry reflects all */
davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
/* we don't use the hardware vector table, just its entry addresses */
davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
/* Clear all interrupt requests */
davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
u32 pri;
for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
pri |= (*davinci_def_priorities & 0x07) << j;
davinci_irq_writel(pri, i);
}
for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
davinci_alloc_gc(davinci_intc_base + j, i, 32);
irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
}

4
arch/arm/mach-davinci/include/mach/irqs.h → arch/arm/mach-davinci/irqs.h
Просмотреть файл

@ -30,9 +30,6 @@
/* Base address */
#define DAVINCI_ARM_INTC_BASE 0x01C48000
#define DAVINCI_INTC_TYPE_AINTC 0
#define DAVINCI_INTC_TYPE_CP_INTC 1
/* Interrupt lines */
#define IRQ_VDINT0 0
#define IRQ_VDINT1 1
@ -404,6 +401,5 @@
/* da850 currently has the most gpio pins (144) */
#define DAVINCI_N_GPIO 144
/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
#endif /* __ASM_ARCH_IRQS_H */

9
arch/arm/mach-davinci/usb-da8xx.c
Просмотреть файл

@ -18,7 +18,8 @@
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <mach/irqs.h>
#include "irqs.h"
#define DA8XX_USB0_BASE 0x01e00000
#define DA8XX_USB1_BASE 0x01e25000
@ -70,7 +71,7 @@ static struct resource da8xx_usb20_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA8XX_USB_INT,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_USB_INT),
.flags = IORESOURCE_IRQ,
.name = "mc",
},
@ -105,8 +106,8 @@ static struct resource da8xx_usb11_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DA8XX_IRQN,
.end = IRQ_DA8XX_IRQN,
.start = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
.end = DAVINCI_INTC_IRQ(IRQ_DA8XX_IRQN),
.flags = IORESOURCE_IRQ,
},
};

15
arch/arm/mach-davinci/usb.c
Просмотреть файл

@ -2,16 +2,16 @@
/*
* USB
*/
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/usb-davinci.h>
#include <linux/usb/musb.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/cputype.h>
#include <linux/platform_data/usb-davinci.h>
#include "irqs.h"
#define DAVINCI_USB_OTG_BASE 0x01c64000
@ -38,7 +38,7 @@ static struct resource usb_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_USBINT,
.start = DAVINCI_INTC_IRQ(IRQ_USBINT),
.flags = IORESOURCE_IRQ,
.name = "mc"
},
@ -70,8 +70,9 @@ void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
if (cpu_is_davinci_dm646x()) {
/* Override the defaults as DM6467 uses different IRQs. */
usb_dev.resource[1].start = IRQ_DM646X_USBINT;
usb_dev.resource[2].start = IRQ_DM646X_USBDMAINT;
usb_dev.resource[1].start = DAVINCI_INTC_IRQ(IRQ_DM646X_USBINT);
usb_dev.resource[2].start = DAVINCI_INTC_IRQ(
IRQ_DM646X_USBDMAINT);
} else /* other devices don't have dedicated CPPI IRQ */
usb_dev.num_resources = 2;

4
drivers/input/keyboard/davinci_keyscan.c
Просмотреть файл

@ -32,10 +32,6 @@
#include <linux/errno.h>
#include <linux/slab.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <linux/platform_data/keyscan-davinci.h>
/* Key scan registers */

10
drivers/irqchip/Kconfig
Просмотреть файл

@ -129,6 +129,16 @@ config BRCMSTB_L2_IRQ
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
config DAVINCI_AINTC
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
config DAVINCI_CP_INTC
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
config DW_APB_ICTL
bool
select GENERIC_IRQ_CHIP

2
drivers/irqchip/Makefile
Просмотреть файл

@ -6,6 +6,8 @@ obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
obj-$(CONFIG_ATH79) += irq-ath79-misc.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o

163
drivers/irqchip/irq-davinci-aintc.c Normal file
Просмотреть файл

@ -0,0 +1,163 @@
// SPDX-License-Identifier: GPL-2.0-or-later
//
// Copyright (C) 2006, 2019 Texas Instruments.
//
// Interrupt handler for DaVinci boards.
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/irq-davinci-aintc.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <asm/exception.h>
#define DAVINCI_AINTC_FIQ_REG0 0x00
#define DAVINCI_AINTC_FIQ_REG1 0x04
#define DAVINCI_AINTC_IRQ_REG0 0x08
#define DAVINCI_AINTC_IRQ_REG1 0x0c
#define DAVINCI_AINTC_IRQ_IRQENTRY 0x14
#define DAVINCI_AINTC_IRQ_ENT_REG0 0x18
#define DAVINCI_AINTC_IRQ_ENT_REG1 0x1c
#define DAVINCI_AINTC_IRQ_INCTL_REG 0x20
#define DAVINCI_AINTC_IRQ_EABASE_REG 0x24
#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x30
#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x4c
static void __iomem *davinci_aintc_base;
static struct irq_domain *davinci_aintc_irq_domain;
static inline void davinci_aintc_writel(unsigned long value, int offset)
{
writel_relaxed(value, davinci_aintc_base + offset);
}
static inline unsigned long davinci_aintc_readl(int offset)
{
return readl_relaxed(davinci_aintc_base + offset);
}
static __init void
davinci_aintc_setup_gc(void __iomem *base,
unsigned int irq_start, unsigned int num)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start);
gc->reg_base = base;
gc->irq_base = irq_start;
ct = gc->chip_types;
ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->regs.ack = DAVINCI_AINTC_IRQ_REG0;
ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0;
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}
static asmlinkage void __exception_irq_entry
davinci_aintc_handle_irq(struct pt_regs *regs)
{
int irqnr = davinci_aintc_readl(DAVINCI_AINTC_IRQ_IRQENTRY);
/*
* Use the formula for entry vector index generation from section
* 8.3.3 of the manual.
*/
irqnr >>= 2;
irqnr -= 1;
handle_domain_irq(davinci_aintc_irq_domain, irqnr, regs);
}
/* ARM Interrupt Controller Initialization */
void __init davinci_aintc_init(const struct davinci_aintc_config *config)
{
unsigned int irq_off, reg_off, prio, shift;
void __iomem *req;
int ret, irq_base;
const u8 *prios;
req = request_mem_region(config->reg.start,
resource_size(&config->reg),
"davinci-cp-intc");
if (!req) {
pr_err("%s: register range busy\n", __func__);
return;
}
davinci_aintc_base = ioremap(config->reg.start,
resource_size(&config->reg));
if (!davinci_aintc_base) {
pr_err("%s: unable to ioremap register range\n", __func__);
return;
}
/* Clear all interrupt requests */
davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
/* Disable all interrupts */
davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG0);
davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG1);
/* Interrupts disabled immediately, IRQ entry reflects all */
davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_INCTL_REG);
/* we don't use the hardware vector table, just its entry addresses */
davinci_aintc_writel(0, DAVINCI_AINTC_IRQ_EABASE_REG);
/* Clear all interrupt requests */
davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
prios = config->prios;
for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG;
reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) {
for (shift = 0, prio = 0; shift < 32; shift += 4, prios++)
prio |= (*prios & 0x07) << shift;
davinci_aintc_writel(prio, reg_off);
}
irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
if (irq_base < 0) {
pr_err("%s: unable to allocate interrupt descriptors: %d\n",
__func__, irq_base);
return;
}
davinci_aintc_irq_domain = irq_domain_add_legacy(NULL,
config->num_irqs, irq_base, 0,
&irq_domain_simple_ops, NULL);
if (!davinci_aintc_irq_domain) {
pr_err("%s: unable to create interrupt domain\n", __func__);
return;
}
ret = irq_alloc_domain_generic_chips(davinci_aintc_irq_domain, 32, 1,
"AINTC", handle_edge_irq,
IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0);
if (ret) {
pr_err("%s: unable to allocate generic irq chips for domain\n",
__func__);
return;
}
for (irq_off = 0, reg_off = 0;
irq_off < config->num_irqs;
irq_off += 32, reg_off += 0x04)
davinci_aintc_setup_gc(davinci_aintc_base + reg_off,
irq_base + irq_off, 32);
set_handle_irq(davinci_aintc_handle_irq);
}

260
drivers/irqchip/irq-davinci-cp-intc.c Normal file
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@ -0,0 +1,260 @@
// SPDX-License-Identifier: GPL-2.0-only
//
// Author: Steve Chen <schen@mvista.com>
// Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
// Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
// Copyright (C) 2019, Texas Instruments
//
// TI Common Platform Interrupt Controller (cp_intc) driver
#include <linux/export.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/irq-davinci-cp-intc.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/exception.h>
#define DAVINCI_CP_INTC_CTRL 0x04
#define DAVINCI_CP_INTC_HOST_CTRL 0x0c
#define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10
#define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24
#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28
#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2c
#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34
#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38
#define DAVINCI_CP_INTC_PRIO_IDX 0x80
#define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
#define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
#define DAVINCI_CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
#define DAVINCI_CP_INTC_SYS_POLARITY(n) (0x0d00 + (n << 2))
#define DAVINCI_CP_INTC_SYS_TYPE(n) (0x0d80 + (n << 2))
#define DAVINCI_CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
#define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0)
#define DAVINCI_CP_INTC_GPIR_NONE BIT(31)
static void __iomem *davinci_cp_intc_base;
static struct irq_domain *davinci_cp_intc_irq_domain;
static inline unsigned int davinci_cp_intc_read(unsigned int offset)
{
return readl_relaxed(davinci_cp_intc_base + offset);
}
static inline void davinci_cp_intc_write(unsigned long value,
unsigned int offset)
{
writel_relaxed(value, davinci_cp_intc_base + offset);
}
static void davinci_cp_intc_ack_irq(struct irq_data *d)
{
davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR);
}
static void davinci_cp_intc_mask_irq(struct irq_data *d)
{
/* XXX don't know why we need to disable nIRQ here... */
davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR);
davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR);
davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
}
static void davinci_cp_intc_unmask_irq(struct irq_data *d)
{
davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET);
}
static int davinci_cp_intc_set_irq_type(struct irq_data *d,
unsigned int flow_type)
{
unsigned int reg, mask, polarity, type;
reg = BIT_WORD(d->hwirq);
mask = BIT_MASK(d->hwirq);
polarity = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_POLARITY(reg));
type = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_TYPE(reg));
switch (flow_type) {
case IRQ_TYPE_EDGE_RISING:
polarity |= mask;
type |= mask;
break;
case IRQ_TYPE_EDGE_FALLING:
polarity &= ~mask;
type |= mask;
break;
case IRQ_TYPE_LEVEL_HIGH:
polarity |= mask;
type &= ~mask;
break;
case IRQ_TYPE_LEVEL_LOW:
polarity &= ~mask;
type &= ~mask;
break;
default:
return -EINVAL;
}
davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg));
davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg));
return 0;
}
static struct irq_chip davinci_cp_intc_irq_chip = {
.name = "cp_intc",
.irq_ack = davinci_cp_intc_ack_irq,
.irq_mask = davinci_cp_intc_mask_irq,
.irq_unmask = davinci_cp_intc_unmask_irq,
.irq_set_type = davinci_cp_intc_set_irq_type,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
static asmlinkage void __exception_irq_entry
davinci_cp_intc_handle_irq(struct pt_regs *regs)
{
int gpir, irqnr, none;
/*
* The interrupt number is in first ten bits. The NONE field set to 1
* indicates a spurious irq.
*/
gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX);
irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK;
none = gpir & DAVINCI_CP_INTC_GPIR_NONE;
if (unlikely(none)) {
pr_err_once("%s: spurious irq!\n", __func__);
return;
}
handle_domain_irq(davinci_cp_intc_irq_domain, irqnr, regs);
}
static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
irq_set_chip(virq, &davinci_cp_intc_irq_chip);
irq_set_probe(virq);
irq_set_handler(virq, handle_edge_irq);
return 0;
}
static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
.map = davinci_cp_intc_host_map,
.xlate = irq_domain_xlate_onetwocell,
};
static int __init
davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
struct device_node *node)
{
unsigned int num_regs = BITS_TO_LONGS(config->num_irqs);
int offset, irq_base;
void __iomem *req;
req = request_mem_region(config->reg.start,
resource_size(&config->reg),
"davinci-cp-intc");
if (!req) {
pr_err("%s: register range busy\n", __func__);
return -EBUSY;
}
davinci_cp_intc_base = ioremap(config->reg.start,
resource_size(&config->reg));
if (!davinci_cp_intc_base) {
pr_err("%s: unable to ioremap register range\n", __func__);
return -EINVAL;
}
davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE);
/* Disable all host interrupts */
davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0));
/* Disable system interrupts */
for (offset = 0; offset < num_regs; offset++)
davinci_cp_intc_write(~0,
DAVINCI_CP_INTC_SYS_ENABLE_CLR(offset));
/* Set to normal mode, no nesting, no priority hold */
davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL);
davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL);
/* Clear system interrupt status */
for (offset = 0; offset < num_regs; offset++)
davinci_cp_intc_write(~0,
DAVINCI_CP_INTC_SYS_STAT_CLR(offset));
/* Enable nIRQ (what about nFIQ?) */
davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
/* Default all priorities to channel 7. */
num_regs = (config->num_irqs + 3) >> 2; /* 4 channels per register */
for (offset = 0; offset < num_regs; offset++)
davinci_cp_intc_write(0x07070707,
DAVINCI_CP_INTC_CHAN_MAP(offset));
irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
if (irq_base < 0) {
pr_err("%s: unable to allocate interrupt descriptors: %d\n",
__func__, irq_base);
return irq_base;
}
davinci_cp_intc_irq_domain = irq_domain_add_legacy(
node, config->num_irqs, irq_base, 0,
&davinci_cp_intc_irq_domain_ops, NULL);
if (!davinci_cp_intc_irq_domain) {
pr_err("%s: unable to create an interrupt domain\n", __func__);
return -EINVAL;
}
set_handle_irq(davinci_cp_intc_handle_irq);
/* Enable global interrupt */
davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE);
return 0;
}
int __init davinci_cp_intc_init(const struct davinci_cp_intc_config *config)
{
return davinci_cp_intc_do_init(config, NULL);
}
static int __init davinci_cp_intc_of_init(struct device_node *node,
struct device_node *parent)
{
struct davinci_cp_intc_config config = { };
int ret;
ret = of_address_to_resource(node, 0, &config.reg);
if (ret) {
pr_err("%s: unable to get the register range from device-tree\n",
__func__);
return ret;
}
ret = of_property_read_u32(node, "ti,intc-size", &config.num_irqs);
if (ret) {
pr_err("%s: unable to read the 'ti,intc-size' property\n",
__func__);
return ret;
}
return davinci_cp_intc_do_init(&config, node);
}
IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init);

6
drivers/net/ethernet/ti/Kconfig
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@ -49,10 +49,11 @@ config TI_DAVINCI_CPDMA
will be called davinci_cpdma. This is recommended.
config TI_CPSW_PHY_SEL
bool
bool "TI CPSW Phy mode Selection (DEPRECATED)"
default n
---help---
This driver supports configuring of the phy mode connected to
the CPSW.
the CPSW. DEPRECATED: use PHY_TI_GMII_SEL.
config TI_CPSW_ALE
tristate "TI CPSW ALE Support"
@ -64,7 +65,6 @@ config TI_CPSW
depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST
select TI_DAVINCI_CPDMA
select TI_DAVINCI_MDIO
select TI_CPSW_PHY_SEL
select TI_CPSW_ALE
select MFD_SYSCON
select REGMAP

6
drivers/net/ethernet/ti/cpsw.h
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@ -21,7 +21,13 @@
((mac)[2] << 16) | ((mac)[3] << 24))
#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
#if IS_ENABLED(CONFIG_TI_CPSW_PHY_SEL)
void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave);
#else
static inline
void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
{}
#endif
int ti_cm_get_macid(struct device *dev, int slave, u8 *mac_addr);
#endif /* __CPSW_H__ */

27
include/linux/irqchip/irq-davinci-aintc.h Normal file
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@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2019 Texas Instruments
*/
#ifndef _LINUX_IRQ_DAVINCI_AINTC_
#define _LINUX_IRQ_DAVINCI_AINTC_
#include <linux/ioport.h>
/**
* struct davinci_aintc_config - configuration data for davinci-aintc driver.
*
* @reg: register range to map
* @num_irqs: number of HW interrupts supported by the controller
* @prios: an array of size num_irqs containing priority settings for
* each interrupt
*/
struct davinci_aintc_config {
struct resource reg;
unsigned int num_irqs;
u8 *prios;
};
void davinci_aintc_init(const struct davinci_aintc_config *config);
#endif /* _LINUX_IRQ_DAVINCI_AINTC_ */

25
include/linux/irqchip/irq-davinci-cp-intc.h Normal file
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@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2019 Texas Instruments
*/
#ifndef _LINUX_IRQ_DAVINCI_CP_INTC_
#define _LINUX_IRQ_DAVINCI_CP_INTC_
#include <linux/ioport.h>
/**
* struct davinci_cp_intc_config - configuration data for davinci-cp-intc
* driver.
*
* @reg: register range to map
* @num_irqs: number of HW interrupts supported by the controller
*/
struct davinci_cp_intc_config {
struct resource reg;
unsigned int num_irqs;
};
int davinci_cp_intc_init(const struct davinci_cp_intc_config *config);
#endif /* _LINUX_IRQ_DAVINCI_CP_INTC_ */