staging: comedi: ni_stc.h: tidy up G_{Mode,Load,Input}*_Register

Rename the CamelCase and define he G0 and G1 registers to add clarity
to the mio_regmap tables.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2015-05-01 14:59:06 -07:00 коммит произвёл Greg Kroah-Hartman
Родитель a2c537362a
Коммит aff2700837
2 изменённых файлов: 25 добавлений и 24 удалений

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@ -336,14 +336,14 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
[NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
[NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
[NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
[G_Mode_Register(0)] = { 0x134, 2 },
[G_Mode_Register(1)] = { 0x136, 2 },
[G_Load_A_Register(0)] = { 0x138, 4 },
[G_Load_B_Register(0)] = { 0x13c, 4 },
[G_Load_A_Register(1)] = { 0x140, 4 },
[G_Load_B_Register(1)] = { 0x144, 4 },
[G_Input_Select_Register(0)] = { 0x148, 2 },
[G_Input_Select_Register(1)] = { 0x14a, 2 },
[NISTC_G0_MODE_REG] = { 0x134, 2 },
[NISTC_G1_MODE_REG] = { 0x136, 2 },
[NISTC_G0_LOADA_REG] = { 0x138, 4 },
[NISTC_G0_LOADB_REG] = { 0x13c, 4 },
[NISTC_G1_LOADA_REG] = { 0x140, 4 },
[NISTC_G1_LOADB_REG] = { 0x144, 4 },
[NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
[NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
[AO_Mode_1_Register] = { 0x14c, 2 },
[AO_Mode_2_Register] = { 0x14e, 2 },
[AO_UI_Load_A_Register] = { 0x150, 4 },
@ -3738,14 +3738,14 @@ static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
[NITIO_G1_HW_SAVE] = { G_HW_Save_Register(1), 4 },
[NITIO_G0_SW_SAVE] = { G_Save_Register(0), 4 },
[NITIO_G1_SW_SAVE] = { G_Save_Register(1), 4 },
[NITIO_G0_MODE] = { G_Mode_Register(0), 2 },
[NITIO_G1_MODE] = { G_Mode_Register(1), 2 },
[NITIO_G0_LOADA] = { G_Load_A_Register(0), 4 },
[NITIO_G1_LOADA] = { G_Load_A_Register(1), 4 },
[NITIO_G0_LOADB] = { G_Load_B_Register(0), 4 },
[NITIO_G1_LOADB] = { G_Load_B_Register(1), 4 },
[NITIO_G0_INPUT_SEL] = { G_Input_Select_Register(0), 2 },
[NITIO_G1_INPUT_SEL] = { G_Input_Select_Register(1), 2 },
[NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
[NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
[NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
[NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
[NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
[NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
[NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
[NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
[NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
[NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
[NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */

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@ -211,6 +211,15 @@
#define NISTC_AI_SI2_LOADA_REG 23
#define NISTC_AI_SI2_LOADB_REG 25
#define NISTC_G0_MODE_REG 26
#define NISTC_G1_MODE_REG 27
#define NISTC_G0_LOADA_REG 28
#define NISTC_G0_LOADB_REG 30
#define NISTC_G1_LOADA_REG 32
#define NISTC_G1_LOADB_REG 34
#define NISTC_G0_INPUT_SEL_REG 36
#define NISTC_G1_INPUT_SEL_REG 37
#define AI_Status_1_Register 2
#define Interrupt_A_St 0x8000
#define AI_FIFO_Full_St 0x4000
@ -605,14 +614,6 @@ static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection
#define G_HW_Save_Register(a) (8+(a)*2)
#define G_HW_Save_Register_High(a) (8+(a)*2)
#define G_HW_Save_Register_Low(a) (9+(a)*2)
#define G_Input_Select_Register(a) (36+(a))
#define G_Load_A_Register(a) (28+(a)*4)
#define G_Load_A_Register_High(a) (28+(a)*4)
#define G_Load_A_Register_Low(a) (29+(a)*4)
#define G_Load_B_Register(a) (30+(a)*4)
#define G_Load_B_Register_High(a) (30+(a)*4)
#define G_Load_B_Register_Low(a) (31+(a)*4)
#define G_Mode_Register(a) (26+(a))
#define G_Save_Register(a) (12+(a)*2)
#define G_Save_Register_High(a) (12+(a)*2)
#define G_Save_Register_Low(a) (13+(a)*2)