irqchip/tegra: Fix overflow implicit truncation warnings
[ Upstream commit 443685992b
]
Fix -Woverflow warnings for tegra irqchip driver which is a result
of moving arm64 custom MMIO accessor macros to asm-generic function
implementations giving a bonus type-checking now and uncovering these
overflow warnings.
drivers/irqchip/irq-tegra.c: In function ‘tegra_ictlr_suspend’:
drivers/irqchip/irq-tegra.c:151:18: warning: large integer implicitly truncated to unsigned type [-Woverflow]
writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
^
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Cc: Marc Zyngier <maz@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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Коммит
b01d6bfdf2
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@ -148,10 +148,10 @@ static int tegra_ictlr_suspend(void)
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lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
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/* Disable COP interrupts */
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writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
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writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
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/* Disable CPU interrupts */
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writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
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writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
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/* Enable the wakeup sources of ictlr */
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writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
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@ -172,12 +172,12 @@ static void tegra_ictlr_resume(void)
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writel_relaxed(lic->cpu_iep[i],
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ictlr + ICTLR_CPU_IEP_CLASS);
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writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
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writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
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writel_relaxed(lic->cpu_ier[i],
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ictlr + ICTLR_CPU_IER_SET);
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writel_relaxed(lic->cop_iep[i],
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ictlr + ICTLR_COP_IEP_CLASS);
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writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
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writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
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writel_relaxed(lic->cop_ier[i],
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ictlr + ICTLR_COP_IER_SET);
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}
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@ -312,7 +312,7 @@ static int __init tegra_ictlr_init(struct device_node *node,
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lic->base[i] = base;
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/* Disable all interrupts */
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writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
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writel_relaxed(GENMASK(31, 0), base + ICTLR_CPU_IER_CLR);
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/* All interrupts target IRQ */
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writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
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