POWERPC: Move generic cpm2 stuff to powerpc
This moves the cpm2 common code and PIC stuff to the powerpc. Most of the files were just copied from ppc/, with minor tuning to make it compile, and, subsequently, work. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
This commit is contained in:
Vitaly Bordug
Родитель
3dd0dcbe9d
Коммит
b0c110b4f1
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@ -20,3 +20,8 @@ ifeq ($(CONFIG_PPC64),y)
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obj-$(CONFIG_SMP) += locks.o
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obj-$(CONFIG_DEBUG_KERNEL) += sstep.o
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endif
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# Temporary hack until we have migrated to asm-powerpc
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ifeq ($(CONFIG_PPC_MERGE),y)
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obj-$(CONFIG_CPM2) += rheap.o
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endif
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@ -17,3 +17,8 @@ ifeq ($(CONFIG_PPC_MERGE),y)
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obj-$(CONFIG_PPC_I8259) += i8259.o
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obj-$(CONFIG_PPC_83xx) += ipic.o
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endif
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# Temporary hack until we have migrated to asm-powerpc
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ifeq ($(ARCH),powerpc)
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obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
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endif
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@ -0,0 +1,210 @@
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/*
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* General Purpose functions for the global management of the
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* 8260 Communication Processor Module.
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* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
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* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
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* 2.3.99 Updates
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*
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* 2006 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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* Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/*
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*
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* In addition to the individual control of the communication
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* channels, there are a few functions that globally affect the
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* communication processor.
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*
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* Buffer descriptors must be allocated from the dual ported memory
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* space. The allocator for that is here. When the communication
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* process is reset, we reclaim the memory available. There is
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* currently no deallocator for this memory.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mpc8260.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/cpm2.h>
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#include <asm/rheap.h>
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#include <asm/fs_pd.h>
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#include <sysdev/fsl_soc.h>
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static void cpm2_dpinit(void);
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cpm_cpm2_t *cpmp; /* Pointer to comm processor space */
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/* We allocate this here because it is used almost exclusively for
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* the communication processor devices.
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*/
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cpm2_map_t *cpm2_immr;
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#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
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of space for CPM as it is larger
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than on PQ2 */
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void
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cpm2_reset(void)
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{
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cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
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/* Reclaim the DP memory for our use.
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*/
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cpm2_dpinit();
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/* Tell everyone where the comm processor resides.
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*/
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cpmp = &cpm2_immr->im_cpm;
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}
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/* Set a baud rate generator. This needs lots of work. There are
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* eight BRGs, which can be connected to the CPM channels or output
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* as clocks. The BRGs are in two different block of internal
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* memory mapped space.
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* The baud rate clock is the system clock divided by something.
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* It was set up long ago during the initial boot phase and is
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* is given to us.
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* Baud rate clocks are zero-based in the driver code (as that maps
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* to port numbers). Documentation uses 1-based numbering.
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*/
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#define BRG_INT_CLK (get_brgfreq())
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#define BRG_UART_CLK (BRG_INT_CLK/16)
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/* This function is used by UARTS, or anything else that uses a 16x
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* oversampled clock.
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*/
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void
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cpm_setbrg(uint brg, uint rate)
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{
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volatile uint *bp;
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/* This is good enough to get SMCs running.....
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*/
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if (brg < 4) {
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bp = (uint *)&cpm2_immr->im_brgc1;
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} else {
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bp = (uint *)&cpm2_immr->im_brgc5;
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brg -= 4;
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}
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bp += brg;
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*bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN;
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}
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/* This function is used to set high speed synchronous baud rate
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* clocks.
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*/
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void
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cpm2_fastbrg(uint brg, uint rate, int div16)
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{
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volatile uint *bp;
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if (brg < 4) {
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bp = (uint *)&cpm2_immr->im_brgc1;
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}
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else {
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bp = (uint *)&cpm2_immr->im_brgc5;
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brg -= 4;
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}
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bp += brg;
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*bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
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if (div16)
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*bp |= CPM_BRG_DIV16;
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}
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/*
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* dpalloc / dpfree bits.
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*/
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static spinlock_t cpm_dpmem_lock;
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/* 16 blocks should be enough to satisfy all requests
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* until the memory subsystem goes up... */
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static rh_block_t cpm_boot_dpmem_rh_block[16];
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static rh_info_t cpm_dpmem_info;
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static void cpm2_dpinit(void)
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{
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spin_lock_init(&cpm_dpmem_lock);
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/* initialize the info header */
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rh_init(&cpm_dpmem_info, 1,
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sizeof(cpm_boot_dpmem_rh_block) /
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sizeof(cpm_boot_dpmem_rh_block[0]),
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cpm_boot_dpmem_rh_block);
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/* Attach the usable dpmem area */
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/* XXX: This is actually crap. CPM_DATAONLY_BASE and
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* CPM_DATAONLY_SIZE is only a subset of the available dpram. It
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* varies with the processor and the microcode patches activated.
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* But the following should be at least safe.
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*/
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rh_attach_region(&cpm_dpmem_info, (void *)CPM_DATAONLY_BASE,
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CPM_DATAONLY_SIZE);
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}
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/* This function returns an index into the DPRAM area.
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*/
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uint cpm_dpalloc(uint size, uint align)
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{
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void *start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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cpm_dpmem_info.alignment = align;
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start = rh_alloc(&cpm_dpmem_info, size, "commproc");
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return (uint)start;
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}
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EXPORT_SYMBOL(cpm_dpalloc);
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int cpm_dpfree(uint offset)
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{
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int ret;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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ret = rh_free(&cpm_dpmem_info, (void *)offset);
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(cpm_dpfree);
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/* not sure if this is ever needed */
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uint cpm_dpalloc_fixed(uint offset, uint size, uint align)
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{
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void *start;
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unsigned long flags;
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spin_lock_irqsave(&cpm_dpmem_lock, flags);
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cpm_dpmem_info.alignment = align;
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start = rh_alloc_fixed(&cpm_dpmem_info, (void *)offset, size, "commproc");
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spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
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return (uint)start;
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}
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EXPORT_SYMBOL(cpm_dpalloc_fixed);
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void cpm_dpdump(void)
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{
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rh_dump(&cpm_dpmem_info);
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}
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EXPORT_SYMBOL(cpm_dpdump);
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void *cpm_dpram_addr(uint offset)
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{
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return (void *)&cpm2_immr->im_dprambase[offset];
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}
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EXPORT_SYMBOL(cpm_dpram_addr);
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@ -0,0 +1,256 @@
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/*
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* Platform information definitions.
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*
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* Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates
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* to make in work in arch/powerpc/. Original (c) belongs to Dan Malek.
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*
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* Author: Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
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* 2006 (c) MontaVista Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/* The CPM2 internal interrupt controller. It is usually
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* the only interrupt controller.
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* There are two 32-bit registers (high/low) for up to 64
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* possible interrupts.
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*
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* Now, the fun starts.....Interrupt Numbers DO NOT MAP
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* in a simple arithmetic fashion to mask or pending registers.
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* That is, interrupt 4 does not map to bit position 4.
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* We create two tables, indexed by vector number, to indicate
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* which register to use and which bit in the register to use.
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*/
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/irq.h>
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#include <asm/immap_cpm2.h>
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#include <asm/mpc8260.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include "cpm2_pic.h"
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static struct device_node *cpm2_pic_node;
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static struct irq_host *cpm2_pic_host;
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
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static const u_char irq_to_siureg[] = {
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0
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};
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/* bit numbers do not match the docs, these are precomputed so the bit for
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* a given irq is (1 << irq_to_siubit[irq]) */
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static const u_char irq_to_siubit[] = {
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0, 15, 14, 13, 12, 11, 10, 9,
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8, 7, 6, 5, 4, 3, 2, 1,
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2, 1, 0, 14, 13, 12, 11, 10,
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9, 8, 7, 6, 5, 4, 3, 0,
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31, 30, 29, 28, 27, 26, 25, 24,
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23, 22, 21, 20, 19, 18, 17, 16,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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};
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static void cpm2_mask_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] &= ~(1 << bit);
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void cpm2_unmask_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] |= 1 << bit;
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void cpm2_mask_and_ack(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr, *sipnr;
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
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ppc_cached_irq_mask[word] &= ~(1 << bit);
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simr[word] = ppc_cached_irq_mask[word];
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sipnr[word] = 1 << bit;
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}
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static void cpm2_end_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq_nr].action) {
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] |= 1 << bit;
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simr[word] = ppc_cached_irq_mask[word];
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/*
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* Work around large numbers of spurious IRQs on PowerPC 82xx
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* systems.
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*/
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mb();
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}
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}
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static struct irq_chip cpm2_pic = {
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.typename = " CPM2 SIU ",
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.enable = cpm2_unmask_irq,
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.disable = cpm2_mask_irq,
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.unmask = cpm2_unmask_irq,
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.mask_ack = cpm2_mask_and_ack,
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.end = cpm2_end_irq,
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};
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int cpm2_get_irq(struct pt_regs *regs)
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{
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int irq;
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unsigned long bits;
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/* For CPM2, read the SIVEC register and shift the bits down
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* to get the irq number.*/
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bits = cpm2_immr->im_intctl.ic_sivec;
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irq = bits >> 26;
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if (irq == 0)
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return(-1);
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return irq+CPM_IRQ_OFFSET;
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}
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static int cpm2_pic_host_match(struct irq_host *h, struct device_node *node)
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{
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return cpm2_pic_node == NULL || cpm2_pic_node == node;
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}
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static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
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get_irq_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
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return 0;
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}
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static void cpm2_host_unmap(struct irq_host *h, unsigned int virq)
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{
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/* Make sure irq is masked in hardware */
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cpm2_mask_irq(virq);
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/* remove chip and handler */
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set_irq_chip_and_handler(virq, NULL, NULL);
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}
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static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
|
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{
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static const unsigned char map_cpm2_senses[4] = {
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IRQ_TYPE_LEVEL_LOW,
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IRQ_TYPE_LEVEL_HIGH,
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_EDGE_RISING,
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};
|
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|
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*out_hwirq = intspec[0];
|
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if (intsize > 1 && intspec[1] < 4)
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*out_flags = map_cpm2_senses[intspec[1]];
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else
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*out_flags = IRQ_TYPE_NONE;
|
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return 0;
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}
|
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|
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static struct irq_host_ops cpm2_pic_host_ops = {
|
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.match = cpm2_pic_host_match,
|
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.map = cpm2_pic_host_map,
|
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.unmap = cpm2_host_unmap,
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.xlate = cpm2_pic_host_xlate,
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};
|
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void cpm2_pic_init(struct device_node *node)
|
||||
{
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int i;
|
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|
||||
/* Clear the CPM IRQ controller, in case it has any bits set
|
||||
* from the bootloader
|
||||
*/
|
||||
|
||||
/* Mask out everything */
|
||||
|
||||
cpm2_immr->im_intctl.ic_simrh = 0x00000000;
|
||||
cpm2_immr->im_intctl.ic_simrl = 0x00000000;
|
||||
|
||||
wmb();
|
||||
|
||||
/* Ack everything */
|
||||
cpm2_immr->im_intctl.ic_sipnrh = 0xffffffff;
|
||||
cpm2_immr->im_intctl.ic_sipnrl = 0xffffffff;
|
||||
wmb();
|
||||
|
||||
/* Dummy read of the vector */
|
||||
i = cpm2_immr->im_intctl.ic_sivec;
|
||||
rmb();
|
||||
|
||||
/* Initialize the default interrupt mapping priorities,
|
||||
* in case the boot rom changed something on us.
|
||||
*/
|
||||
cpm2_immr->im_intctl.ic_sicr = 0;
|
||||
cpm2_immr->im_intctl.ic_scprrh = 0x05309770;
|
||||
cpm2_immr->im_intctl.ic_scprrl = 0x05309770;
|
||||
|
||||
/* create a legacy host */
|
||||
if (node)
|
||||
cpm2_pic_node = of_node_get(node);
|
||||
|
||||
cpm2_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm2_pic_host_ops, 64);
|
||||
if (cpm2_pic_host == NULL) {
|
||||
printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef _PPC_KERNEL_CPM2_H
|
||||
#define _PPC_KERNEL_CPM2_H
|
||||
|
||||
extern int cpm2_get_irq(struct pt_regs *regs);
|
||||
|
||||
extern void cpm2_pic_init(struct device_node*);
|
||||
|
||||
#endif /* _PPC_KERNEL_CPM2_H */
|
||||
|
|
@ -42,6 +42,8 @@
|
|||
#define CPM_CR_IDMA4_SBLOCK (0x17)
|
||||
#define CPM_CR_MCC1_SBLOCK (0x1c)
|
||||
|
||||
#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
|
||||
|
||||
#define CPM_CR_SCC1_PAGE (0x00)
|
||||
#define CPM_CR_SCC2_PAGE (0x01)
|
||||
#define CPM_CR_SCC3_PAGE (0x02)
|
||||
|
|
@ -62,6 +64,8 @@
|
|||
#define CPM_CR_MCC1_PAGE (0x07)
|
||||
#define CPM_CR_MCC2_PAGE (0x08)
|
||||
|
||||
#define CPM_CR_FCC_PAGE(x) (x + 0x04)
|
||||
|
||||
/* Some opcodes (there are more...later)
|
||||
*/
|
||||
#define CPM_CR_INIT_TRX ((ushort)0x0000)
|
||||
|
|
@ -1186,7 +1190,7 @@ typedef struct im_idma {
|
|||
#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
|
||||
#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
|
||||
#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
|
||||
#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(2)
|
||||
#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
|
||||
|
||||
#endif /* __CPM2__ */
|
||||
#endif /* __KERNEL__ */
|
||||
|
|
|
|||
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