irq_remapping/vt-d: Enhance Intel IR driver to support hierarchical irqdomains
Enhance Intel interrupt remapping driver to support hierarchical irqdomains. Implement intel_ir_chip to support stacked irq_chip. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Acked-by: Joerg Roedel <jroedel@suse.de> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: iommu@lists.linux-foundation.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: David Woodhouse <dwmw2@infradead.org> Link: http://lkml.kernel.org/r/1428905519-23704-11-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Jiang Liu
Thomas Gleixner
Родитель
8dedf4cf5a
Коммит
b106ee63ab
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@ -8,6 +8,7 @@
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#include <linux/irq.h>
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#include <linux/intel-iommu.h>
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#include <linux/acpi.h>
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#include <linux/irqdomain.h>
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#include <asm/io_apic.h>
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#include <asm/smp.h>
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#include <asm/cpu.h>
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@ -31,6 +32,14 @@ struct hpet_scope {
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unsigned int devfn;
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};
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struct intel_ir_data {
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struct irq_2_iommu irq_2_iommu;
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struct irte irte_entry;
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union {
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struct msi_msg msi_entry;
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};
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};
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#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
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#define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
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@ -50,6 +59,7 @@ static struct hpet_scope ir_hpet[MAX_HPET_TBS];
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* the dmar_global_lock.
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*/
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static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
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static struct irq_domain_ops intel_ir_domain_ops;
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static int __init parse_ioapics_under_ir(void);
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@ -263,7 +273,7 @@ static int free_irte(int irq)
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unsigned long flags;
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int rc;
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if (!irq_iommu)
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if (!irq_iommu || irq_iommu->iommu == NULL)
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return -1;
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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@ -488,7 +498,6 @@ static int intel_setup_irq_remapping(struct intel_iommu *iommu)
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pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
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INTR_REMAP_PAGE_ORDER);
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if (!pages) {
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pr_err("IR%d: failed to allocate pages of order %d\n",
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iommu->seq_id, INTR_REMAP_PAGE_ORDER);
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@ -502,11 +511,23 @@ static int intel_setup_irq_remapping(struct intel_iommu *iommu)
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goto out_free_pages;
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}
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iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(),
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0, INTR_REMAP_TABLE_ENTRIES,
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NULL, &intel_ir_domain_ops,
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iommu);
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if (!iommu->ir_domain) {
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pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
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goto out_free_bitmap;
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}
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iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
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ir_table->base = page_address(pages);
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ir_table->bitmap = bitmap;
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iommu->ir_table = ir_table;
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return 0;
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out_free_bitmap:
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kfree(bitmap);
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out_free_pages:
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__free_pages(pages, INTR_REMAP_PAGE_ORDER);
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out_free_table:
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@ -517,6 +538,14 @@ out_free_table:
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static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
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{
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if (iommu && iommu->ir_table) {
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if (iommu->ir_msi_domain) {
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irq_domain_remove(iommu->ir_msi_domain);
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iommu->ir_msi_domain = NULL;
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}
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if (iommu->ir_domain) {
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irq_domain_remove(iommu->ir_domain);
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iommu->ir_domain = NULL;
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}
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free_pages((unsigned long)iommu->ir_table->base,
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INTR_REMAP_PAGE_ORDER);
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kfree(iommu->ir_table->bitmap);
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@ -1062,12 +1091,6 @@ intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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struct irte irte;
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int err;
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if (!config_enabled(CONFIG_SMP))
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return -EINVAL;
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if (!cpumask_intersects(mask, cpu_online_mask))
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return -EINVAL;
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if (get_irte(irq, &irte))
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return -EBUSY;
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@ -1100,6 +1123,7 @@ intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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send_cleanup_vector(cfg);
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cpumask_copy(data->affinity, mask);
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return 0;
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}
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@ -1205,6 +1229,53 @@ static int intel_alloc_hpet_msi(unsigned int irq, unsigned int id)
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return ret;
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}
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static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
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{
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struct intel_iommu *iommu = NULL;
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if (!info)
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return NULL;
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switch (info->type) {
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case X86_IRQ_ALLOC_TYPE_IOAPIC:
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iommu = map_ioapic_to_ir(info->ioapic_id);
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break;
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case X86_IRQ_ALLOC_TYPE_HPET:
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iommu = map_hpet_to_ir(info->hpet_id);
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break;
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case X86_IRQ_ALLOC_TYPE_MSI:
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case X86_IRQ_ALLOC_TYPE_MSIX:
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iommu = map_dev_to_ir(info->msi_dev);
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break;
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default:
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BUG_ON(1);
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break;
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}
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return iommu ? iommu->ir_domain : NULL;
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}
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static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
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{
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struct intel_iommu *iommu;
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if (!info)
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return NULL;
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switch (info->type) {
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case X86_IRQ_ALLOC_TYPE_MSI:
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case X86_IRQ_ALLOC_TYPE_MSIX:
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iommu = map_dev_to_ir(info->msi_dev);
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if (iommu)
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return iommu->ir_msi_domain;
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break;
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default:
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break;
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}
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return NULL;
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}
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struct irq_remap_ops intel_irq_remap_ops = {
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.prepare = intel_prepare_irq_remapping,
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.enable = intel_enable_irq_remapping,
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@ -1218,6 +1289,256 @@ struct irq_remap_ops intel_irq_remap_ops = {
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.msi_alloc_irq = intel_msi_alloc_irq,
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.msi_setup_irq = intel_msi_setup_irq,
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.alloc_hpet_msi = intel_alloc_hpet_msi,
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.get_ir_irq_domain = intel_get_ir_irq_domain,
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.get_irq_domain = intel_get_irq_domain,
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};
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/*
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* Migrate the IO-APIC irq in the presence of intr-remapping.
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*
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* For both level and edge triggered, irq migration is a simple atomic
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* update(of vector and cpu destination) of IRTE and flush the hardware cache.
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*
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* For level triggered, we eliminate the io-apic RTE modification (with the
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* updated vector information), by using a virtual vector (io-apic pin number).
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* Real vector that is used for interrupting cpu will be coming from
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* the interrupt-remapping table entry.
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*
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* As the migration is a simple atomic update of IRTE, the same mechanism
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* is used to migrate MSI irq's in the presence of interrupt-remapping.
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*/
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static int
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intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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struct intel_ir_data *ir_data = data->chip_data;
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struct irte *irte = &ir_data->irte_entry;
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struct irq_cfg *cfg = irqd_cfg(data);
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struct irq_data *parent = data->parent_data;
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int ret;
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
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return ret;
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/*
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* Atomically updates the IRTE with the new destination, vector
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* and flushes the interrupt entry cache.
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*/
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irte->vector = cfg->vector;
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irte->dest_id = IRTE_DEST(cfg->dest_apicid);
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modify_irte(&ir_data->irq_2_iommu, irte);
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/*
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* After this point, all the interrupts will start arriving
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* at the new destination. So, time to cleanup the previous
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* vector allocation.
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*/
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return IRQ_SET_MASK_OK_DONE;
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}
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static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
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struct msi_msg *msg)
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{
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struct intel_ir_data *ir_data = irq_data->chip_data;
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*msg = ir_data->msi_entry;
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}
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static struct irq_chip intel_ir_chip = {
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.irq_ack = ir_ack_apic_edge,
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.irq_set_affinity = intel_ir_set_affinity,
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.irq_compose_msi_msg = intel_ir_compose_msi_msg,
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};
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static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
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struct irq_cfg *irq_cfg,
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struct irq_alloc_info *info,
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int index, int sub_handle)
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{
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struct IR_IO_APIC_route_entry *entry;
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struct irte *irte = &data->irte_entry;
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struct msi_msg *msg = &data->msi_entry;
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prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
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switch (info->type) {
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case X86_IRQ_ALLOC_TYPE_IOAPIC:
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/* Set source-id of interrupt request */
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set_ioapic_sid(irte, info->ioapic_id);
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apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
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info->ioapic_id, irte->present, irte->fpd,
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irte->dst_mode, irte->redir_hint,
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irte->trigger_mode, irte->dlvry_mode,
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irte->avail, irte->vector, irte->dest_id,
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irte->sid, irte->sq, irte->svt);
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entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
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info->ioapic_entry = NULL;
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memset(entry, 0, sizeof(*entry));
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entry->index2 = (index >> 15) & 0x1;
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entry->zero = 0;
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entry->format = 1;
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entry->index = (index & 0x7fff);
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/*
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* IO-APIC RTE will be configured with virtual vector.
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* irq handler will do the explicit EOI to the io-apic.
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*/
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entry->vector = info->ioapic_pin;
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entry->mask = 0; /* enable IRQ */
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entry->trigger = info->ioapic_trigger;
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entry->polarity = info->ioapic_polarity;
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if (info->ioapic_trigger)
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entry->mask = 1; /* Mask level triggered irqs. */
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break;
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case X86_IRQ_ALLOC_TYPE_HPET:
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case X86_IRQ_ALLOC_TYPE_MSI:
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case X86_IRQ_ALLOC_TYPE_MSIX:
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if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
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set_hpet_sid(irte, info->hpet_id);
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else
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set_msi_sid(irte, info->msi_dev);
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msg->address_hi = MSI_ADDR_BASE_HI;
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msg->data = sub_handle;
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msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
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MSI_ADDR_IR_SHV |
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MSI_ADDR_IR_INDEX1(index) |
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MSI_ADDR_IR_INDEX2(index);
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break;
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default:
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BUG_ON(1);
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break;
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}
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}
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static void intel_free_irq_resources(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *irq_data;
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struct intel_ir_data *data;
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struct irq_2_iommu *irq_iommu;
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unsigned long flags;
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int i;
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for (i = 0; i < nr_irqs; i++) {
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irq_data = irq_domain_get_irq_data(domain, virq + i);
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if (irq_data && irq_data->chip_data) {
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data = irq_data->chip_data;
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irq_iommu = &data->irq_2_iommu;
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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clear_entries(irq_iommu);
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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irq_domain_reset_irq_data(irq_data);
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kfree(data);
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}
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}
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}
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static int intel_irq_remapping_alloc(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs,
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void *arg)
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{
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struct intel_iommu *iommu = domain->host_data;
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struct irq_alloc_info *info = arg;
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struct intel_ir_data *data;
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struct irq_data *irq_data;
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struct irq_cfg *irq_cfg;
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int i, ret, index;
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if (!info || !iommu)
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return -EINVAL;
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if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
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info->type != X86_IRQ_ALLOC_TYPE_MSIX)
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return -EINVAL;
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/*
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* With IRQ remapping enabled, don't need contiguous CPU vectors
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* to support multiple MSI interrupts.
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*/
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if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
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info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
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ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
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if (ret < 0)
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return ret;
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ret = -ENOMEM;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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goto out_free_parent;
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down_read(&dmar_global_lock);
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index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs);
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up_read(&dmar_global_lock);
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if (index < 0) {
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pr_warn("Failed to allocate IRTE\n");
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kfree(data);
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goto out_free_parent;
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}
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for (i = 0; i < nr_irqs; i++) {
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irq_data = irq_domain_get_irq_data(domain, virq + i);
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irq_cfg = irqd_cfg(irq_data);
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if (!irq_data || !irq_cfg) {
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ret = -EINVAL;
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goto out_free_data;
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}
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if (i > 0) {
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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goto out_free_data;
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}
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irq_data->hwirq = (index << 16) + i;
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irq_data->chip_data = data;
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irq_data->chip = &intel_ir_chip;
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intel_irq_remapping_prepare_irte(data, irq_cfg, info, index, i);
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irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
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}
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return 0;
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out_free_data:
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intel_free_irq_resources(domain, virq, i);
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out_free_parent:
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irq_domain_free_irqs_common(domain, virq, nr_irqs);
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return ret;
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}
|
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|
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static void intel_irq_remapping_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
|
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{
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intel_free_irq_resources(domain, virq, nr_irqs);
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irq_domain_free_irqs_common(domain, virq, nr_irqs);
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}
|
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|
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static void intel_irq_remapping_activate(struct irq_domain *domain,
|
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struct irq_data *irq_data)
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{
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struct intel_ir_data *data = irq_data->chip_data;
|
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|
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modify_irte(&data->irq_2_iommu, &data->irte_entry);
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}
|
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|
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static void intel_irq_remapping_deactivate(struct irq_domain *domain,
|
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struct irq_data *irq_data)
|
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{
|
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struct intel_ir_data *data = irq_data->chip_data;
|
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struct irte entry;
|
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|
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memset(&entry, 0, sizeof(entry));
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modify_irte(&data->irq_2_iommu, &entry);
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}
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|
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static struct irq_domain_ops intel_ir_domain_ops = {
|
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.alloc = intel_irq_remapping_alloc,
|
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.free = intel_irq_remapping_free,
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.activate = intel_irq_remapping_activate,
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.deactivate = intel_irq_remapping_deactivate,
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};
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/*
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|
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@ -286,6 +286,8 @@ struct q_inval {
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|||
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||||
#define INTR_REMAP_TABLE_ENTRIES 65536
|
||||
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||||
struct irq_domain;
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||||
|
||||
struct ir_table {
|
||||
struct irte *base;
|
||||
unsigned long *bitmap;
|
||||
|
|
@ -335,6 +337,8 @@ struct intel_iommu {
|
|||
|
||||
#ifdef CONFIG_IRQ_REMAP
|
||||
struct ir_table *ir_table; /* Interrupt remapping info */
|
||||
struct irq_domain *ir_domain;
|
||||
struct irq_domain *ir_msi_domain;
|
||||
#endif
|
||||
struct device *iommu_dev; /* IOMMU-sysfs device */
|
||||
int node;
|
||||
|
|
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|||
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