mtd: rawnand: au1550nd: Get rid of the legacy interface implementation
Now that exec_op() is implemented we can get rid of all other hooks. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200419193037.1544035-4-boris.brezillon@collabora.com
This commit is contained in:
Boris Brezillon
Miquel Raynal
Родитель
a67537ef37
Коммит
b1593f8a43
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@ -21,7 +21,6 @@ struct au1550nd_ctx {
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int cs;
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void __iomem *base;
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void (*write_byte)(struct nand_chip *, u_char);
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};
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static struct au1550nd_ctx *chip_to_au_ctx(struct nand_chip *this)
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@ -29,58 +28,6 @@ static struct au1550nd_ctx *chip_to_au_ctx(struct nand_chip *this)
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return container_of(this, struct au1550nd_ctx, chip);
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}
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/**
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* au_read_byte - read one byte from the chip
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* @this: NAND chip object
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*
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* read function for 8bit buswidth
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*/
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static u_char au_read_byte(struct nand_chip *this)
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{
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u_char ret = readb(this->legacy.IO_ADDR_R);
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wmb(); /* drain writebuffer */
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return ret;
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}
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/**
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* au_write_byte - write one byte to the chip
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* @this: NAND chip object
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* @byte: pointer to data byte to write
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*
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* write function for 8it buswidth
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*/
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static void au_write_byte(struct nand_chip *this, u_char byte)
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{
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writeb(byte, this->legacy.IO_ADDR_W);
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wmb(); /* drain writebuffer */
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}
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/**
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* au_read_byte16 - read one byte endianness aware from the chip
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* @this: NAND chip object
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*
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* read function for 16bit buswidth with endianness conversion
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*/
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static u_char au_read_byte16(struct nand_chip *this)
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{
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u_char ret = (u_char) cpu_to_le16(readw(this->legacy.IO_ADDR_R));
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wmb(); /* drain writebuffer */
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return ret;
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}
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/**
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* au_write_byte16 - write one byte endianness aware to the chip
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* @this: NAND chip object
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* @byte: pointer to data byte to write
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*
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* write function for 16bit buswidth with endianness conversion
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*/
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static void au_write_byte16(struct nand_chip *this, u_char byte)
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{
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writew(le16_to_cpu((u16) byte), this->legacy.IO_ADDR_W);
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wmb(); /* drain writebuffer */
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}
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/**
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* au_write_buf - write buffer to chip
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* @this: NAND chip object
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@ -162,206 +109,6 @@ static void au_read_buf16(struct nand_chip *this, u_char *buf, int len)
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}
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}
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/* Select the chip by setting nCE to low */
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#define NAND_CTL_SETNCE 1
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/* Deselect the chip by setting nCE to high */
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#define NAND_CTL_CLRNCE 2
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/* Select the command latch by setting CLE to high */
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#define NAND_CTL_SETCLE 3
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/* Deselect the command latch by setting CLE to low */
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#define NAND_CTL_CLRCLE 4
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/* Select the address latch by setting ALE to high */
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#define NAND_CTL_SETALE 5
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/* Deselect the address latch by setting ALE to low */
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#define NAND_CTL_CLRALE 6
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static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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struct nand_chip *this = mtd_to_nand(mtd);
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struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
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chip);
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switch (cmd) {
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case NAND_CTL_SETCLE:
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this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
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break;
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case NAND_CTL_CLRCLE:
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this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
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break;
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case NAND_CTL_SETALE:
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this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
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break;
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case NAND_CTL_CLRALE:
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this->legacy.IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
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/* FIXME: Nobody knows why this is necessary,
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* but it works only that way */
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udelay(1);
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break;
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case NAND_CTL_SETNCE:
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/* assert (force assert) chip enable */
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alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
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break;
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case NAND_CTL_CLRNCE:
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/* deassert chip enable */
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alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
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break;
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}
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this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W;
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wmb(); /* Drain the writebuffer */
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}
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int au1550_device_ready(struct nand_chip *this)
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{
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return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
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}
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/**
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* au1550_select_chip - control -CE line
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* Forbid driving -CE manually permitting the NAND controller to do this.
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* Keeping -CE asserted during the whole sector reads interferes with the
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* NOR flash and PCMCIA drivers as it causes contention on the static bus.
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* We only have to hold -CE low for the NAND read commands since the flash
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* chip needs it to be asserted during chip not ready time but the NAND
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* controller keeps it released.
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*
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* @this: NAND chip object
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* @chip: chipnumber to select, -1 for deselect
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*/
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static void au1550_select_chip(struct nand_chip *this, int chip)
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{
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}
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/**
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* au1550_command - Send command to NAND device
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* @this: NAND chip object
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* @command: the command to be sent
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* @column: the column address for this command, -1 if none
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* @page_addr: the page address for this command, -1 if none
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*/
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static void au1550_command(struct nand_chip *this, unsigned command,
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int column, int page_addr)
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{
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struct mtd_info *mtd = nand_to_mtd(this);
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struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
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chip);
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int ce_override = 0, i;
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unsigned long flags = 0;
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/* Begin command latch cycle */
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au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
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/*
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* Write out the command to the device.
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*/
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if (command == NAND_CMD_SEQIN) {
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int readcmd;
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if (column >= mtd->writesize) {
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/* OOB area */
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column -= mtd->writesize;
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readcmd = NAND_CMD_READOOB;
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} else if (column < 256) {
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/* First 256 bytes --> READ0 */
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readcmd = NAND_CMD_READ0;
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} else {
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column -= 256;
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readcmd = NAND_CMD_READ1;
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}
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ctx->write_byte(this, readcmd);
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}
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ctx->write_byte(this, command);
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/* Set ALE and clear CLE to start address cycle */
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au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
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if (column != -1 || page_addr != -1) {
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au1550_hwcontrol(mtd, NAND_CTL_SETALE);
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/* Serially input address */
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if (column != -1) {
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/* Adjust columns for 16 bit buswidth */
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if (this->options & NAND_BUSWIDTH_16 &&
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!nand_opcode_8bits(command))
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column >>= 1;
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ctx->write_byte(this, column);
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}
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if (page_addr != -1) {
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ctx->write_byte(this, (u8)(page_addr & 0xff));
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if (command == NAND_CMD_READ0 ||
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command == NAND_CMD_READ1 ||
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command == NAND_CMD_READOOB) {
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/*
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* NAND controller will release -CE after
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* the last address byte is written, so we'll
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* have to forcibly assert it. No interrupts
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* are allowed while we do this as we don't
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* want the NOR flash or PCMCIA drivers to
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* steal our precious bytes of data...
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*/
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ce_override = 1;
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local_irq_save(flags);
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au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
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}
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ctx->write_byte(this, (u8)(page_addr >> 8));
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if (this->options & NAND_ROW_ADDR_3)
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ctx->write_byte(this,
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((page_addr >> 16) & 0x0f));
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}
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/* Latch in address */
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au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
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}
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/*
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* Program and erase have their own busy handlers.
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* Status and sequential in need no delay.
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*/
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switch (command) {
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_STATUS:
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return;
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case NAND_CMD_RESET:
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break;
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case NAND_CMD_READ0:
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case NAND_CMD_READ1:
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case NAND_CMD_READOOB:
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/* Check if we're really driving -CE low (just in case) */
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if (unlikely(!ce_override))
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break;
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/* Apply a short delay always to ensure that we do wait tWB. */
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ndelay(100);
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/* Wait for a chip to become ready... */
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for (i = this->legacy.chip_delay;
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!this->legacy.dev_ready(this) && i > 0; --i)
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udelay(1);
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/* Release -CE and re-enable interrupts. */
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au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
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local_irq_restore(flags);
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return;
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}
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/* Apply this short delay always to ensure that we do wait tWB. */
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ndelay(100);
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while(!this->legacy.dev_ready(this));
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}
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static int find_nand_cs(unsigned long nand_base)
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{
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void __iomem *base =
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@ -540,12 +287,6 @@ static int au1550nd_probe(struct platform_device *pdev)
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}
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ctx->cs = cs;
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this->legacy.dev_ready = au1550_device_ready;
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this->legacy.select_chip = au1550_select_chip;
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this->legacy.cmdfunc = au1550_command;
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/* 30 us command delay time */
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this->legacy.chip_delay = 30;
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nand_controller_init(&ctx->controller);
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ctx->controller.ops = &au1550nd_ops;
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this->controller = &ctx->controller;
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@ -555,11 +296,6 @@ static int au1550nd_probe(struct platform_device *pdev)
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if (pd->devwidth)
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this->options |= NAND_BUSWIDTH_16;
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this->legacy.read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
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ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
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this->legacy.write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
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this->legacy.read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
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ret = nand_scan(this, 1);
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if (ret) {
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dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
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