Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: PCI hotplug: Change link order of pciehp & acpiphp PCI hotplug: fakephp: Allocate PCI resources before adding the device PCI MSI: Fix undefined shift by 32 PCI PM: Do not wait for buses in B2 or B3 during resume PCI PM: Power up devices before restoring their state PCI PM: Fix hibernation breakage on EeePC 701 PCI: irq and pci_ids patch for Intel Tigerpoint DeviceIDs PCI PM: Fix suspend error paths and testing facility breakage
This commit is contained in:
Коммит
b1792e3670
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@ -572,6 +572,7 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
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case PCI_DEVICE_ID_INTEL_ICH7_1:
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case PCI_DEVICE_ID_INTEL_ICH7_30:
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case PCI_DEVICE_ID_INTEL_ICH7_31:
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case PCI_DEVICE_ID_INTEL_TGP_LPC:
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case PCI_DEVICE_ID_INTEL_ESB2_0:
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case PCI_DEVICE_ID_INTEL_ICH8_0:
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case PCI_DEVICE_ID_INTEL_ICH8_1:
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@ -5,11 +5,15 @@
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obj-$(CONFIG_HOTPLUG_PCI) += pci_hotplug.o
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obj-$(CONFIG_HOTPLUG_PCI_COMPAQ) += cpqphp.o
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obj-$(CONFIG_HOTPLUG_PCI_IBM) += ibmphp.o
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# pciehp should be linked before acpiphp in order to allow the native driver
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# to attempt to bind first. We can then fall back to generic support.
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obj-$(CONFIG_HOTPLUG_PCI_PCIE) += pciehp.o
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obj-$(CONFIG_HOTPLUG_PCI_ACPI) += acpiphp.o
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obj-$(CONFIG_HOTPLUG_PCI_ACPI_IBM) += acpiphp_ibm.o
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obj-$(CONFIG_HOTPLUG_PCI_CPCI_ZT5550) += cpcihp_zt5550.o
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obj-$(CONFIG_HOTPLUG_PCI_CPCI_GENERIC) += cpcihp_generic.o
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obj-$(CONFIG_HOTPLUG_PCI_PCIE) += pciehp.o
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obj-$(CONFIG_HOTPLUG_PCI_SHPC) += shpchp.o
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obj-$(CONFIG_HOTPLUG_PCI_RPA) += rpaphp.o
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obj-$(CONFIG_HOTPLUG_PCI_RPA_DLPAR) += rpadlpar_io.o
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@ -195,13 +195,13 @@ static void remove_slot_worker(struct work_struct *work)
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* Tries hard not to re-enable already existing devices;
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* also handles scanning of subfunctions.
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*/
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static void pci_rescan_slot(struct pci_dev *temp)
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static int pci_rescan_slot(struct pci_dev *temp)
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{
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struct pci_bus *bus = temp->bus;
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struct pci_dev *dev;
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int func;
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int retval;
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u8 hdr_type;
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int count = 0;
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if (!pci_read_config_byte(temp, PCI_HEADER_TYPE, &hdr_type)) {
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temp->hdr_type = hdr_type & 0x7f;
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@ -213,17 +213,12 @@ static void pci_rescan_slot(struct pci_dev *temp)
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dbg("New device on %s function %x:%x\n",
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bus->name, temp->devfn >> 3,
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temp->devfn & 7);
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retval = pci_bus_add_device(dev);
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if (retval)
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dev_err(&dev->dev, "error adding "
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"device, continuing.\n");
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else
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add_slot(dev);
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count++;
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}
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}
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/* multifunction device? */
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if (!(hdr_type & 0x80))
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return;
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return count;
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/* continue scanning for other functions */
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for (func = 1, temp->devfn++; func < 8; func++, temp->devfn++) {
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@ -239,16 +234,13 @@ static void pci_rescan_slot(struct pci_dev *temp)
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dbg("New device on %s function %x:%x\n",
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bus->name, temp->devfn >> 3,
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temp->devfn & 7);
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retval = pci_bus_add_device(dev);
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if (retval)
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dev_err(&dev->dev, "error adding "
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"device, continuing.\n");
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else
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add_slot(dev);
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count++;
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}
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}
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}
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}
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return count;
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}
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@ -262,6 +254,8 @@ static void pci_rescan_bus(const struct pci_bus *bus)
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{
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unsigned int devfn;
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struct pci_dev *dev;
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int retval;
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int found = 0;
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dev = alloc_pci_dev();
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if (!dev)
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return;
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@ -270,7 +264,23 @@ static void pci_rescan_bus(const struct pci_bus *bus)
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dev->sysdata = bus->sysdata;
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for (devfn = 0; devfn < 0x100; devfn += 8) {
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dev->devfn = devfn;
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pci_rescan_slot(dev);
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found += pci_rescan_slot(dev);
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}
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if (found) {
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pci_bus_assign_resources(bus);
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list_for_each_entry(dev, &bus->devices, bus_list) {
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/* Skip already-added devices */
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if (dev->is_added)
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continue;
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retval = pci_bus_add_device(dev);
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if (retval)
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dev_err(&dev->dev,
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"Error adding device, continuing\n");
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else
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add_slot(dev);
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}
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pci_bus_add_devices(bus);
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}
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kfree(dev);
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}
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@ -103,6 +103,16 @@ static void msix_set_enable(struct pci_dev *dev, int enable)
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}
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}
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/*
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* Essentially, this is ((1 << (1 << x)) - 1), but without the
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* undefinedness of a << 32.
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*/
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static inline __attribute_const__ u32 msi_mask(unsigned x)
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{
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static const u32 mask[] = { 1, 2, 4, 0xf, 0xff, 0xffff, 0xffffffff };
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return mask[x];
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}
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static void msix_flush_writes(struct irq_desc *desc)
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{
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struct msi_desc *entry;
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@ -407,8 +417,7 @@ static int msi_capability_init(struct pci_dev *dev)
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/* All MSIs are unmasked by default, Mask them all */
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pci_read_config_dword(dev, base, &maskbits);
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temp = (1 << multi_msi_capable(control));
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temp = ((temp - 1) & ~temp);
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temp = msi_mask((control & PCI_MSI_FLAGS_QMASK) >> 1);
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maskbits |= temp;
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pci_write_config_dword(dev, base, maskbits);
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entry->msi_attrib.maskbits_mask = temp;
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@ -370,6 +370,7 @@ static int pci_legacy_suspend(struct device *dev, pm_message_t state)
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}
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pci_save_state(pci_dev);
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pci_dev->state_saved = true;
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/*
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* This is for compatibility with existing code with legacy PM support.
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*/
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@ -419,6 +420,7 @@ static int pci_legacy_resume(struct device *dev)
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static void pci_pm_default_resume_noirq(struct pci_dev *pci_dev)
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{
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pci_restore_standard_config(pci_dev);
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pci_dev->state_saved = false;
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pci_fixup_device(pci_fixup_resume_early, pci_dev);
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}
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@ -555,6 +557,13 @@ static int pci_pm_resume(struct device *dev)
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struct device_driver *drv = dev->driver;
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int error = 0;
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/*
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* This is necessary for the suspend error path in which resume is
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* called without restoring the standard config registers of the device.
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*/
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if (pci_dev->state_saved)
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pci_restore_standard_config(pci_dev);
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if (pci_has_legacy_pm_support(pci_dev))
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return pci_legacy_resume(dev);
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@ -660,7 +669,10 @@ static int pci_pm_poweroff(struct device *dev)
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if (pci_has_legacy_pm_support(pci_dev))
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return pci_legacy_suspend(dev, PMSG_HIBERNATE);
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if (drv && drv->pm && drv->pm->poweroff) {
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if (!drv || !drv->pm)
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return 0;
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if (drv->pm->poweroff) {
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error = drv->pm->poweroff(dev);
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suspend_report_result(drv->pm->poweroff, error);
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}
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@ -710,6 +722,13 @@ static int pci_pm_restore(struct device *dev)
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struct device_driver *drv = dev->driver;
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int error = 0;
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/*
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* This is necessary for the hibernation error path in which restore is
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* called without restoring the standard config registers of the device.
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*/
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if (pci_dev->state_saved)
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pci_restore_standard_config(pci_dev);
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if (pci_has_legacy_pm_support(pci_dev))
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return pci_legacy_resume(dev);
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@ -1393,35 +1393,35 @@ int pci_restore_standard_config(struct pci_dev *dev)
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pci_power_t prev_state;
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int error;
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pci_restore_state(dev);
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pci_update_current_state(dev, PCI_D0);
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prev_state = dev->current_state;
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if (prev_state == PCI_D0)
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return 0;
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goto Restore;
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error = pci_raw_set_power_state(dev, PCI_D0, false);
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if (error)
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return error;
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if (pci_is_bridge(dev)) {
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if (prev_state > PCI_D1)
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mdelay(PCI_PM_BUS_WAIT);
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} else {
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switch(prev_state) {
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case PCI_D3cold:
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case PCI_D3hot:
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mdelay(pci_pm_d3_delay);
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break;
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case PCI_D2:
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udelay(PCI_PM_D2_DELAY);
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break;
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}
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/*
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* This assumes that we won't get a bus in B2 or B3 from the BIOS, but
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* we've made this assumption forever and it appears to be universally
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* satisfied.
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*/
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switch(prev_state) {
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case PCI_D3cold:
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case PCI_D3hot:
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mdelay(pci_pm_d3_delay);
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break;
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case PCI_D2:
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udelay(PCI_PM_D2_DELAY);
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break;
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}
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dev->current_state = PCI_D0;
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return 0;
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Restore:
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return pci_restore_state(dev);
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}
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/**
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@ -2425,6 +2425,7 @@
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#define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8
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#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9
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#define PCI_DEVICE_ID_INTEL_ICH7_30 0x27b0
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#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc
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#define PCI_DEVICE_ID_INTEL_ICH7_31 0x27bd
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#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
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#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd
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