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@ -24,48 +24,25 @@
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#include "iommu_common.h"
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/* These should be allocated on an SMP_CACHE_BYTES
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* aligned boundary for optimal performance.
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*
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* On SYSIO, using an 8K page size we have 1GB of SBUS
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* DMA space mapped. We divide this space into equally
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* sized clusters. We allocate a DMA mapping from the
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* cluster that matches the order of the allocation, or
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* if the order is greater than the number of clusters,
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* we try to allocate from the last cluster.
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*/
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#define NCLUSTERS 8UL
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#define ONE_GIG (1UL * 1024UL * 1024UL * 1024UL)
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#define CLUSTER_SIZE (ONE_GIG / NCLUSTERS)
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#define CLUSTER_MASK (CLUSTER_SIZE - 1)
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#define CLUSTER_NPAGES (CLUSTER_SIZE >> IO_PAGE_SHIFT)
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#define MAP_BASE ((u32)0xc0000000)
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struct sbus_iommu_arena {
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unsigned long *map;
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unsigned int hint;
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unsigned int limit;
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};
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struct sbus_iommu {
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/*0x00*/spinlock_t lock;
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spinlock_t lock;
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/*0x08*/iopte_t *page_table;
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/*0x10*/unsigned long strbuf_regs;
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/*0x18*/unsigned long iommu_regs;
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/*0x20*/unsigned long sbus_control_reg;
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struct sbus_iommu_arena arena;
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/*0x28*/volatile unsigned long strbuf_flushflag;
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iopte_t *page_table;
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unsigned long strbuf_regs;
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unsigned long iommu_regs;
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unsigned long sbus_control_reg;
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/* If NCLUSTERS is ever decresed to 4 or lower,
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* you must increase the size of the type of
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* these counters. You have been duly warned. -DaveM
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*/
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/*0x30*/struct {
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u16 next;
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u16 flush;
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} alloc_info[NCLUSTERS];
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/* The lowest used consistent mapping entry. Since
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* we allocate consistent maps out of cluster 0 this
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* is relative to the beginning of closter 0.
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*/
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/*0x50*/u32 lowest_consistent_map;
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volatile unsigned long strbuf_flushflag;
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};
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/* Offsets from iommu_regs */
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@ -91,19 +68,6 @@ static void __iommu_flushall(struct sbus_iommu *iommu)
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tag += 8UL;
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}
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upa_readq(iommu->sbus_control_reg);
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for (entry = 0; entry < NCLUSTERS; entry++) {
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iommu->alloc_info[entry].flush =
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iommu->alloc_info[entry].next;
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}
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}
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static void iommu_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages)
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{
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while (npages--)
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upa_writeq(base + (npages << IO_PAGE_SHIFT),
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iommu->iommu_regs + IOMMU_FLUSH);
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upa_readq(iommu->sbus_control_reg);
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}
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/* Offsets from strbuf_regs */
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@ -156,178 +120,115 @@ static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long
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base, npages);
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}
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static iopte_t *alloc_streaming_cluster(struct sbus_iommu *iommu, unsigned long npages)
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/* Based largely upon the ppc64 iommu allocator. */
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static long sbus_arena_alloc(struct sbus_iommu *iommu, unsigned long npages)
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{
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iopte_t *iopte, *limit, *first, *cluster;
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unsigned long cnum, ent, nent, flush_point, found;
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struct sbus_iommu_arena *arena = &iommu->arena;
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unsigned long n, i, start, end, limit;
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int pass;
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cnum = 0;
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nent = 1;
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while ((1UL << cnum) < npages)
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cnum++;
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if(cnum >= NCLUSTERS) {
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nent = 1UL << (cnum - NCLUSTERS);
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cnum = NCLUSTERS - 1;
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}
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iopte = iommu->page_table + (cnum * CLUSTER_NPAGES);
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limit = arena->limit;
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start = arena->hint;
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pass = 0;
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if (cnum == 0)
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limit = (iommu->page_table +
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iommu->lowest_consistent_map);
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else
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limit = (iopte + CLUSTER_NPAGES);
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iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
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flush_point = iommu->alloc_info[cnum].flush;
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first = iopte;
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cluster = NULL;
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found = 0;
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for (;;) {
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if (iopte_val(*iopte) == 0UL) {
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found++;
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if (!cluster)
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cluster = iopte;
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} else {
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/* Used cluster in the way */
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cluster = NULL;
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found = 0;
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}
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if (found == nent)
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break;
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iopte += (1 << cnum);
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ent++;
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if (iopte >= limit) {
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iopte = (iommu->page_table + (cnum * CLUSTER_NPAGES));
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ent = 0;
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/* Multiple cluster allocations must not wrap */
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cluster = NULL;
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found = 0;
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}
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if (ent == flush_point)
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again:
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n = find_next_zero_bit(arena->map, limit, start);
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end = n + npages;
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if (unlikely(end >= limit)) {
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if (likely(pass < 1)) {
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limit = start;
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start = 0;
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__iommu_flushall(iommu);
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if (iopte == first)
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goto bad;
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}
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/* ent/iopte points to the last cluster entry we're going to use,
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* so save our place for the next allocation.
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*/
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if ((iopte + (1 << cnum)) >= limit)
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ent = 0;
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else
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ent = ent + 1;
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iommu->alloc_info[cnum].next = ent;
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if (ent == flush_point)
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__iommu_flushall(iommu);
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/* I've got your streaming cluster right here buddy boy... */
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return cluster;
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bad:
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printk(KERN_EMERG "sbus: alloc_streaming_cluster of npages(%ld) failed!\n",
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npages);
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return NULL;
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}
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static void free_streaming_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
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{
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unsigned long cnum, ent, nent;
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iopte_t *iopte;
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cnum = 0;
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nent = 1;
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while ((1UL << cnum) < npages)
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cnum++;
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if(cnum >= NCLUSTERS) {
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nent = 1UL << (cnum - NCLUSTERS);
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cnum = NCLUSTERS - 1;
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}
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ent = (base & CLUSTER_MASK) >> (IO_PAGE_SHIFT + cnum);
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iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
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do {
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iopte_val(*iopte) = 0UL;
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iopte += 1 << cnum;
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} while(--nent);
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/* If the global flush might not have caught this entry,
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* adjust the flush point such that we will flush before
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* ever trying to reuse it.
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*/
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#define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
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if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
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iommu->alloc_info[cnum].flush = ent;
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#undef between
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}
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/* We allocate consistent mappings from the end of cluster zero. */
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static iopte_t *alloc_consistent_cluster(struct sbus_iommu *iommu, unsigned long npages)
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{
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iopte_t *iopte;
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iopte = iommu->page_table + (1 * CLUSTER_NPAGES);
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while (iopte > iommu->page_table) {
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iopte--;
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if (!(iopte_val(*iopte) & IOPTE_VALID)) {
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unsigned long tmp = npages;
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while (--tmp) {
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iopte--;
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if (iopte_val(*iopte) & IOPTE_VALID)
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break;
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}
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if (tmp == 0) {
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u32 entry = (iopte - iommu->page_table);
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if (entry < iommu->lowest_consistent_map)
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iommu->lowest_consistent_map = entry;
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return iopte;
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}
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pass++;
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goto again;
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} else {
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/* Scanned the whole thing, give up. */
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return -1;
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}
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}
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return NULL;
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}
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static void free_consistent_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
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{
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iopte_t *iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
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if ((iopte - iommu->page_table) == iommu->lowest_consistent_map) {
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iopte_t *walk = iopte + npages;
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iopte_t *limit;
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limit = iommu->page_table + CLUSTER_NPAGES;
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while (walk < limit) {
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if (iopte_val(*walk) != 0UL)
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break;
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walk++;
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for (i = n; i < end; i++) {
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if (test_bit(i, arena->map)) {
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start = i + 1;
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goto again;
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}
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iommu->lowest_consistent_map =
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(walk - iommu->page_table);
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}
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while (npages--)
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*iopte++ = __iopte(0UL);
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for (i = n; i < end; i++)
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__set_bit(i, arena->map);
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arena->hint = end;
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return n;
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}
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static void sbus_arena_free(struct sbus_iommu_arena *arena, unsigned long base, unsigned long npages)
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{
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unsigned long i;
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for (i = base; i < (base + npages); i++)
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__clear_bit(i, arena->map);
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}
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static void sbus_iommu_table_init(struct sbus_iommu *iommu, unsigned int tsbsize)
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{
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unsigned long tsbbase, order, sz, num_tsb_entries;
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num_tsb_entries = tsbsize / sizeof(iopte_t);
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/* Setup initial software IOMMU state. */
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spin_lock_init(&iommu->lock);
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/* Allocate and initialize the free area map. */
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sz = num_tsb_entries / 8;
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sz = (sz + 7UL) & ~7UL;
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iommu->arena.map = kzalloc(sz, GFP_KERNEL);
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if (!iommu->arena.map) {
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prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
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prom_halt();
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}
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iommu->arena.limit = num_tsb_entries;
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/* Now allocate and setup the IOMMU page table itself. */
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order = get_order(tsbsize);
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tsbbase = __get_free_pages(GFP_KERNEL, order);
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if (!tsbbase) {
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prom_printf("IOMMU: Error, gfp(tsb) failed.\n");
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prom_halt();
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}
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iommu->page_table = (iopte_t *)tsbbase;
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memset(iommu->page_table, 0, tsbsize);
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}
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static inline iopte_t *alloc_npages(struct sbus_iommu *iommu, unsigned long npages)
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{
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long entry;
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entry = sbus_arena_alloc(iommu, npages);
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if (unlikely(entry < 0))
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return NULL;
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return iommu->page_table + entry;
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}
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static inline void free_npages(struct sbus_iommu *iommu, dma_addr_t base, unsigned long npages)
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{
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sbus_arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
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}
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void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma_addr)
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{
|
|
|
|
|
unsigned long order, first_page, flags;
|
|
|
|
|
struct sbus_iommu *iommu;
|
|
|
|
|
iopte_t *iopte;
|
|
|
|
|
unsigned long flags, order, first_page;
|
|
|
|
|
void *ret;
|
|
|
|
|
int npages;
|
|
|
|
|
|
|
|
|
|
if (size <= 0 || sdev == NULL || dvma_addr == NULL)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
size = IO_PAGE_ALIGN(size);
|
|
|
|
|
order = get_order(size);
|
|
|
|
|
if (order >= 10)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
first_page = __get_free_pages(GFP_KERNEL|__GFP_COMP, order);
|
|
|
|
|
if (first_page == 0UL)
|
|
|
|
|
return NULL;
|
|
|
|
@ -336,108 +237,121 @@ void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma
|
|
|
|
|
iommu = sdev->bus->iommu;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
|
iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
|
|
|
|
|
if (iopte == NULL) {
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
|
|
|
|
|
if (unlikely(iopte == NULL)) {
|
|
|
|
|
free_pages(first_page, order);
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Ok, we're committed at this point. */
|
|
|
|
|
*dvma_addr = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
|
|
|
|
|
*dvma_addr = (MAP_BASE +
|
|
|
|
|
((iopte - iommu->page_table) << IO_PAGE_SHIFT));
|
|
|
|
|
ret = (void *) first_page;
|
|
|
|
|
npages = size >> IO_PAGE_SHIFT;
|
|
|
|
|
first_page = __pa(first_page);
|
|
|
|
|
while (npages--) {
|
|
|
|
|
*iopte++ = __iopte(IOPTE_VALID | IOPTE_CACHE | IOPTE_WRITE |
|
|
|
|
|
(__pa(first_page) & IOPTE_PAGE));
|
|
|
|
|
iopte_val(*iopte) = (IOPTE_VALID | IOPTE_CACHE |
|
|
|
|
|
IOPTE_WRITE |
|
|
|
|
|
(first_page & IOPTE_PAGE));
|
|
|
|
|
iopte++;
|
|
|
|
|
first_page += IO_PAGE_SIZE;
|
|
|
|
|
}
|
|
|
|
|
iommu_flush(iommu, *dvma_addr, size >> IO_PAGE_SHIFT);
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void sbus_free_consistent(struct sbus_dev *sdev, size_t size, void *cpu, dma_addr_t dvma)
|
|
|
|
|
{
|
|
|
|
|
unsigned long order, npages;
|
|
|
|
|
struct sbus_iommu *iommu;
|
|
|
|
|
|
|
|
|
|
if (size <= 0 || sdev == NULL || cpu == NULL)
|
|
|
|
|
return;
|
|
|
|
|
iopte_t *iopte;
|
|
|
|
|
unsigned long flags, order, npages;
|
|
|
|
|
|
|
|
|
|
npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
|
|
|
|
|
iommu = sdev->bus->iommu;
|
|
|
|
|
iopte = iommu->page_table +
|
|
|
|
|
((dvma - MAP_BASE) >> IO_PAGE_SHIFT);
|
|
|
|
|
|
|
|
|
|
spin_lock_irq(&iommu->lock);
|
|
|
|
|
free_consistent_cluster(iommu, dvma, npages);
|
|
|
|
|
iommu_flush(iommu, dvma, npages);
|
|
|
|
|
spin_unlock_irq(&iommu->lock);
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
|
|
|
|
|
|
free_npages(iommu, dvma - MAP_BASE, npages);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
|
|
|
|
|
order = get_order(size);
|
|
|
|
|
if (order < 10)
|
|
|
|
|
free_pages((unsigned long)cpu, order);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t size, int dir)
|
|
|
|
|
dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t sz, int direction)
|
|
|
|
|
{
|
|
|
|
|
struct sbus_iommu *iommu = sdev->bus->iommu;
|
|
|
|
|
unsigned long npages, pbase, flags;
|
|
|
|
|
iopte_t *iopte;
|
|
|
|
|
u32 dma_base, offset;
|
|
|
|
|
unsigned long iopte_bits;
|
|
|
|
|
struct sbus_iommu *iommu;
|
|
|
|
|
iopte_t *base;
|
|
|
|
|
unsigned long flags, npages, oaddr;
|
|
|
|
|
unsigned long i, base_paddr;
|
|
|
|
|
u32 bus_addr, ret;
|
|
|
|
|
unsigned long iopte_protection;
|
|
|
|
|
|
|
|
|
|
if (dir == SBUS_DMA_NONE)
|
|
|
|
|
iommu = sdev->bus->iommu;
|
|
|
|
|
|
|
|
|
|
if (unlikely(direction == SBUS_DMA_NONE))
|
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
|
|
pbase = (unsigned long) ptr;
|
|
|
|
|
offset = (u32) (pbase & ~IO_PAGE_MASK);
|
|
|
|
|
size = (IO_PAGE_ALIGN(pbase + size) - (pbase & IO_PAGE_MASK));
|
|
|
|
|
pbase = (unsigned long) __pa(pbase & IO_PAGE_MASK);
|
|
|
|
|
oaddr = (unsigned long)ptr;
|
|
|
|
|
npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
|
|
|
|
|
npages >>= IO_PAGE_SHIFT;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
|
npages = size >> IO_PAGE_SHIFT;
|
|
|
|
|
iopte = alloc_streaming_cluster(iommu, npages);
|
|
|
|
|
if (iopte == NULL)
|
|
|
|
|
goto bad;
|
|
|
|
|
dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
|
|
|
|
|
npages = size >> IO_PAGE_SHIFT;
|
|
|
|
|
iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
|
|
|
|
|
if (dir != SBUS_DMA_TODEVICE)
|
|
|
|
|
iopte_bits |= IOPTE_WRITE;
|
|
|
|
|
while (npages--) {
|
|
|
|
|
*iopte++ = __iopte(iopte_bits | (pbase & IOPTE_PAGE));
|
|
|
|
|
pbase += IO_PAGE_SIZE;
|
|
|
|
|
}
|
|
|
|
|
npages = size >> IO_PAGE_SHIFT;
|
|
|
|
|
base = alloc_npages(iommu, npages);
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
|
|
|
|
|
return (dma_base | offset);
|
|
|
|
|
if (unlikely(!base))
|
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
|
|
bad:
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
BUG();
|
|
|
|
|
return 0;
|
|
|
|
|
bus_addr = (MAP_BASE +
|
|
|
|
|
((base - iommu->page_table) << IO_PAGE_SHIFT));
|
|
|
|
|
ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
|
|
|
|
|
base_paddr = __pa(oaddr & IO_PAGE_MASK);
|
|
|
|
|
|
|
|
|
|
iopte_protection = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
|
|
|
|
|
if (direction != SBUS_DMA_TODEVICE)
|
|
|
|
|
iopte_protection |= IOPTE_WRITE;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
|
|
|
|
|
iopte_val(*base) = iopte_protection | base_paddr;
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t dma_addr, size_t size, int direction)
|
|
|
|
|
void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t bus_addr, size_t sz, int direction)
|
|
|
|
|
{
|
|
|
|
|
struct sbus_iommu *iommu = sdev->bus->iommu;
|
|
|
|
|
u32 dma_base = dma_addr & IO_PAGE_MASK;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
iopte_t *base;
|
|
|
|
|
unsigned long flags, npages, i;
|
|
|
|
|
|
|
|
|
|
size = (IO_PAGE_ALIGN(dma_addr + size) - dma_base);
|
|
|
|
|
if (unlikely(direction == SBUS_DMA_NONE))
|
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
|
|
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
|
|
|
|
|
npages >>= IO_PAGE_SHIFT;
|
|
|
|
|
base = iommu->page_table +
|
|
|
|
|
((bus_addr - MAP_BASE) >> IO_PAGE_SHIFT);
|
|
|
|
|
|
|
|
|
|
bus_addr &= IO_PAGE_MASK;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
|
free_streaming_cluster(iommu, dma_base, size >> IO_PAGE_SHIFT);
|
|
|
|
|
sbus_strbuf_flush(iommu, dma_base, size >> IO_PAGE_SHIFT, direction);
|
|
|
|
|
sbus_strbuf_flush(iommu, bus_addr, npages, direction);
|
|
|
|
|
for (i = 0; i < npages; i++)
|
|
|
|
|
iopte_val(base[i]) = 0UL;
|
|
|
|
|
free_npages(iommu, bus_addr - MAP_BASE, npages);
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define SG_ENT_PHYS_ADDRESS(SG) \
|
|
|
|
|
(__pa(page_address((SG)->page)) + (SG)->offset)
|
|
|
|
|
|
|
|
|
|
static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, int nelems, unsigned long iopte_bits)
|
|
|
|
|
static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
|
|
|
|
|
int nused, int nelems, unsigned long iopte_protection)
|
|
|
|
|
{
|
|
|
|
|
struct scatterlist *dma_sg = sg;
|
|
|
|
|
struct scatterlist *sg_end = sg + nelems;
|
|
|
|
@ -462,7 +376,7 @@ static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, in
|
|
|
|
|
for (;;) {
|
|
|
|
|
unsigned long tmp;
|
|
|
|
|
|
|
|
|
|
tmp = (unsigned long) SG_ENT_PHYS_ADDRESS(sg);
|
|
|
|
|
tmp = SG_ENT_PHYS_ADDRESS(sg);
|
|
|
|
|
len = sg->length;
|
|
|
|
|
if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
|
|
|
|
|
pteval = tmp & IO_PAGE_MASK;
|
|
|
|
@ -478,7 +392,7 @@ static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, in
|
|
|
|
|
sg++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
pteval = ((pteval & IOPTE_PAGE) | iopte_bits);
|
|
|
|
|
pteval = iopte_protection | (pteval & IOPTE_PAGE);
|
|
|
|
|
while (len > 0) {
|
|
|
|
|
*iopte++ = __iopte(pteval);
|
|
|
|
|
pteval += IO_PAGE_SIZE;
|
|
|
|
@ -509,103 +423,111 @@ static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, in
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int dir)
|
|
|
|
|
int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, int direction)
|
|
|
|
|
{
|
|
|
|
|
struct sbus_iommu *iommu = sdev->bus->iommu;
|
|
|
|
|
unsigned long flags, npages;
|
|
|
|
|
iopte_t *iopte;
|
|
|
|
|
struct sbus_iommu *iommu;
|
|
|
|
|
unsigned long flags, npages, iopte_protection;
|
|
|
|
|
iopte_t *base;
|
|
|
|
|
u32 dma_base;
|
|
|
|
|
struct scatterlist *sgtmp;
|
|
|
|
|
int used;
|
|
|
|
|
unsigned long iopte_bits;
|
|
|
|
|
|
|
|
|
|
if (dir == SBUS_DMA_NONE)
|
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
|
|
/* Fast path single entry scatterlists. */
|
|
|
|
|
if (nents == 1) {
|
|
|
|
|
sg->dma_address =
|
|
|
|
|
if (nelems == 1) {
|
|
|
|
|
sglist->dma_address =
|
|
|
|
|
sbus_map_single(sdev,
|
|
|
|
|
(page_address(sg->page) + sg->offset),
|
|
|
|
|
sg->length, dir);
|
|
|
|
|
sg->dma_length = sg->length;
|
|
|
|
|
(page_address(sglist->page) + sglist->offset),
|
|
|
|
|
sglist->length, direction);
|
|
|
|
|
sglist->dma_length = sglist->length;
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
npages = prepare_sg(sg, nents);
|
|
|
|
|
iommu = sdev->bus->iommu;
|
|
|
|
|
|
|
|
|
|
if (unlikely(direction == SBUS_DMA_NONE))
|
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
|
|
npages = prepare_sg(sglist, nelems);
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
|
iopte = alloc_streaming_cluster(iommu, npages);
|
|
|
|
|
if (iopte == NULL)
|
|
|
|
|
goto bad;
|
|
|
|
|
dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
|
|
|
|
|
base = alloc_npages(iommu, npages);
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
|
|
|
|
|
if (unlikely(base == NULL))
|
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
|
|
dma_base = MAP_BASE +
|
|
|
|
|
((base - iommu->page_table) << IO_PAGE_SHIFT);
|
|
|
|
|
|
|
|
|
|
/* Normalize DVMA addresses. */
|
|
|
|
|
sgtmp = sg;
|
|
|
|
|
used = nents;
|
|
|
|
|
used = nelems;
|
|
|
|
|
|
|
|
|
|
sgtmp = sglist;
|
|
|
|
|
while (used && sgtmp->dma_length) {
|
|
|
|
|
sgtmp->dma_address += dma_base;
|
|
|
|
|
sgtmp++;
|
|
|
|
|
used--;
|
|
|
|
|
}
|
|
|
|
|
used = nents - used;
|
|
|
|
|
used = nelems - used;
|
|
|
|
|
|
|
|
|
|
iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
|
|
|
|
|
if (dir != SBUS_DMA_TODEVICE)
|
|
|
|
|
iopte_bits |= IOPTE_WRITE;
|
|
|
|
|
iopte_protection = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
|
|
|
|
|
if (direction != SBUS_DMA_TODEVICE)
|
|
|
|
|
iopte_protection |= IOPTE_WRITE;
|
|
|
|
|
|
|
|
|
|
fill_sg(base, sglist, used, nelems, iopte_protection);
|
|
|
|
|
|
|
|
|
|
fill_sg(iopte, sg, used, nents, iopte_bits);
|
|
|
|
|
#ifdef VERIFY_SG
|
|
|
|
|
verify_sglist(sg, nents, iopte, npages);
|
|
|
|
|
verify_sglist(sglist, nelems, base, npages);
|
|
|
|
|
#endif
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
|
|
|
|
|
return used;
|
|
|
|
|
|
|
|
|
|
bad:
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
BUG();
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
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void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
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void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, int direction)
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{
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unsigned long size, flags;
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struct sbus_iommu *iommu;
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u32 dvma_base;
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int i;
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iopte_t *base;
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unsigned long flags, i, npages;
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u32 bus_addr;
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/* Fast path single entry scatterlists. */
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if (nents == 1) {
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sbus_unmap_single(sdev, sg->dma_address, sg->dma_length, direction);
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return;
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}
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dvma_base = sg[0].dma_address & IO_PAGE_MASK;
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for (i = 0; i < nents; i++) {
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if (sg[i].dma_length == 0)
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break;
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}
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i--;
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size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - dvma_base;
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if (unlikely(direction == SBUS_DMA_NONE))
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BUG();
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iommu = sdev->bus->iommu;
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bus_addr = sglist->dma_address & IO_PAGE_MASK;
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for (i = 1; i < nelems; i++)
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if (sglist[i].dma_length == 0)
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break;
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i--;
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npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
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bus_addr) >> IO_PAGE_SHIFT;
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base = iommu->page_table +
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((bus_addr - MAP_BASE) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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free_streaming_cluster(iommu, dvma_base, size >> IO_PAGE_SHIFT);
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sbus_strbuf_flush(iommu, dvma_base, size >> IO_PAGE_SHIFT, direction);
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sbus_strbuf_flush(iommu, bus_addr, npages, direction);
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for (i = 0; i < npages; i++)
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iopte_val(base[i]) = 0UL;
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free_npages(iommu, bus_addr - MAP_BASE, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
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void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, dma_addr_t bus_addr, size_t sz, int direction)
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{
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struct sbus_iommu *iommu = sdev->bus->iommu;
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unsigned long flags;
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struct sbus_iommu *iommu;
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unsigned long flags, npages;
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size = (IO_PAGE_ALIGN(base + size) - (base & IO_PAGE_MASK));
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iommu = sdev->bus->iommu;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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sbus_strbuf_flush(iommu, base & IO_PAGE_MASK, size >> IO_PAGE_SHIFT, direction);
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sbus_strbuf_flush(iommu, bus_addr, npages, direction);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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@ -613,23 +535,25 @@ void sbus_dma_sync_single_for_device(struct sbus_dev *sdev, dma_addr_t base, siz
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{
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}
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void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
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void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sglist, int nelems, int direction)
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{
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struct sbus_iommu *iommu = sdev->bus->iommu;
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|
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unsigned long flags, size;
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|
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u32 base;
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|
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int i;
|
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|
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struct sbus_iommu *iommu;
|
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|
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unsigned long flags, npages, i;
|
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|
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u32 bus_addr;
|
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|
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|
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base = sg[0].dma_address & IO_PAGE_MASK;
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|
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for (i = 0; i < nents; i++) {
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|
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if (sg[i].dma_length == 0)
|
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|
|
iommu = sdev->bus->iommu;
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bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
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|
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for (i = 0; i < nelems; i++) {
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|
|
if (!sglist[i].dma_length)
|
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|
|
break;
|
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|
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}
|
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i--;
|
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|
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size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - base;
|
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|
|
npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length)
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|
|
- bus_addr) >> IO_PAGE_SHIFT;
|
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|
|
spin_lock_irqsave(&iommu->lock, flags);
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|
|
sbus_strbuf_flush(iommu, base, size >> IO_PAGE_SHIFT, direction);
|
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|
|
sbus_strbuf_flush(iommu, bus_addr, npages, direction);
|
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@ -1104,7 +1028,7 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
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|
struct linux_prom64_registers *pr;
|
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|
|
struct device_node *dp;
|
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|
|
|
struct sbus_iommu *iommu;
|
|
|
|
|
unsigned long regs, tsb_base;
|
|
|
|
|
unsigned long regs;
|
|
|
|
|
u64 control;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
@ -1132,14 +1056,6 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
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|
|
|
|
|
|
|
|
memset(iommu, 0, sizeof(*iommu));
|
|
|
|
|
|
|
|
|
|
/* We start with no consistent mappings. */
|
|
|
|
|
iommu->lowest_consistent_map = CLUSTER_NPAGES;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < NCLUSTERS; i++) {
|
|
|
|
|
iommu->alloc_info[i].flush = 0;
|
|
|
|
|
iommu->alloc_info[i].next = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Setup spinlock. */
|
|
|
|
|
spin_lock_init(&iommu->lock);
|
|
|
|
|
|
|
|
|
@ -1159,25 +1075,13 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
|
|
|
|
|
sbus->portid, regs);
|
|
|
|
|
|
|
|
|
|
/* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
|
|
|
|
|
sbus_iommu_table_init(iommu, IO_TSB_SIZE);
|
|
|
|
|
|
|
|
|
|
control = upa_readq(iommu->iommu_regs + IOMMU_CONTROL);
|
|
|
|
|
control = ((7UL << 16UL) |
|
|
|
|
|
(0UL << 2UL) |
|
|
|
|
|
(1UL << 1UL) |
|
|
|
|
|
(1UL << 0UL));
|
|
|
|
|
|
|
|
|
|
/* Using the above configuration we need 1MB iommu page
|
|
|
|
|
* table (128K ioptes * 8 bytes per iopte). This is
|
|
|
|
|
* page order 7 on UltraSparc.
|
|
|
|
|
*/
|
|
|
|
|
tsb_base = __get_free_pages(GFP_ATOMIC, get_order(IO_TSB_SIZE));
|
|
|
|
|
if (tsb_base == 0UL) {
|
|
|
|
|
prom_printf("sbus_iommu_init: Fatal error, cannot alloc TSB table.\n");
|
|
|
|
|
prom_halt();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
iommu->page_table = (iopte_t *) tsb_base;
|
|
|
|
|
memset(iommu->page_table, 0, IO_TSB_SIZE);
|
|
|
|
|
|
|
|
|
|
upa_writeq(control, iommu->iommu_regs + IOMMU_CONTROL);
|
|
|
|
|
|
|
|
|
|
/* Clean out any cruft in the IOMMU using
|
|
|
|
@ -1195,7 +1099,7 @@ static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
|
|
|
|
|
upa_readq(iommu->sbus_control_reg);
|
|
|
|
|
|
|
|
|
|
/* Give the TSB to SYSIO. */
|
|
|
|
|
upa_writeq(__pa(tsb_base), iommu->iommu_regs + IOMMU_TSBBASE);
|
|
|
|
|
upa_writeq(__pa(iommu->page_table), iommu->iommu_regs + IOMMU_TSBBASE);
|
|
|
|
|
|
|
|
|
|
/* Setup streaming buffer, DE=1 SB_EN=1 */
|
|
|
|
|
control = (1UL << 1UL) | (1UL << 0UL);
|
|
|
|
|