[media] v4l2-dv-timings: add new helper module
This module makes it easy to filter valid timings from the full list of CEA and DMT timings based on the timings capabilities. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Acked-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Hans Verkuil
Mauro Carvalho Chehab
Родитель
299878fa3c
Коммит
b18787ed1c
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@ -17,6 +17,7 @@ endif
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obj-$(CONFIG_VIDEO_V4L2) += videodev.o
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obj-$(CONFIG_VIDEO_V4L2_INT_DEVICE) += v4l2-int-device.o
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obj-$(CONFIG_VIDEO_V4L2) += v4l2-common.o
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obj-$(CONFIG_VIDEO_V4L2) += v4l2-dv-timings.o
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obj-$(CONFIG_VIDEO_TUNER) += tuner.o
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@ -0,0 +1,192 @@
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/*
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* v4l2-dv-timings - dv-timings helper functions
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*
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* Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/videodev2.h>
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#include <linux/v4l2-dv-timings.h>
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#include <media/v4l2-common.h>
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#include <media/v4l2-dv-timings.h>
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static const struct v4l2_dv_timings timings[] = {
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V4L2_DV_BT_CEA_640X480P59_94,
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V4L2_DV_BT_CEA_720X480I59_94,
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V4L2_DV_BT_CEA_720X480P59_94,
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V4L2_DV_BT_CEA_720X576I50,
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V4L2_DV_BT_CEA_720X576P50,
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V4L2_DV_BT_CEA_1280X720P24,
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V4L2_DV_BT_CEA_1280X720P25,
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V4L2_DV_BT_CEA_1280X720P30,
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V4L2_DV_BT_CEA_1280X720P50,
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V4L2_DV_BT_CEA_1280X720P60,
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V4L2_DV_BT_CEA_1920X1080P24,
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V4L2_DV_BT_CEA_1920X1080P25,
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V4L2_DV_BT_CEA_1920X1080P30,
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V4L2_DV_BT_CEA_1920X1080I50,
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V4L2_DV_BT_CEA_1920X1080P50,
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V4L2_DV_BT_CEA_1920X1080I60,
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V4L2_DV_BT_CEA_1920X1080P60,
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V4L2_DV_BT_DMT_640X350P85,
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V4L2_DV_BT_DMT_640X400P85,
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V4L2_DV_BT_DMT_720X400P85,
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V4L2_DV_BT_DMT_640X480P72,
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V4L2_DV_BT_DMT_640X480P75,
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V4L2_DV_BT_DMT_640X480P85,
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V4L2_DV_BT_DMT_800X600P56,
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V4L2_DV_BT_DMT_800X600P60,
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V4L2_DV_BT_DMT_800X600P72,
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V4L2_DV_BT_DMT_800X600P75,
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V4L2_DV_BT_DMT_800X600P85,
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V4L2_DV_BT_DMT_800X600P120_RB,
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V4L2_DV_BT_DMT_848X480P60,
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V4L2_DV_BT_DMT_1024X768I43,
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V4L2_DV_BT_DMT_1024X768P60,
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V4L2_DV_BT_DMT_1024X768P70,
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V4L2_DV_BT_DMT_1024X768P75,
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V4L2_DV_BT_DMT_1024X768P85,
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V4L2_DV_BT_DMT_1024X768P120_RB,
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V4L2_DV_BT_DMT_1152X864P75,
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V4L2_DV_BT_DMT_1280X768P60_RB,
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V4L2_DV_BT_DMT_1280X768P60,
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V4L2_DV_BT_DMT_1280X768P75,
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V4L2_DV_BT_DMT_1280X768P85,
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V4L2_DV_BT_DMT_1280X768P120_RB,
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V4L2_DV_BT_DMT_1280X800P60_RB,
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V4L2_DV_BT_DMT_1280X800P60,
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V4L2_DV_BT_DMT_1280X800P75,
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V4L2_DV_BT_DMT_1280X800P85,
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V4L2_DV_BT_DMT_1280X800P120_RB,
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V4L2_DV_BT_DMT_1280X960P60,
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V4L2_DV_BT_DMT_1280X960P85,
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V4L2_DV_BT_DMT_1280X960P120_RB,
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V4L2_DV_BT_DMT_1280X1024P60,
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V4L2_DV_BT_DMT_1280X1024P75,
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V4L2_DV_BT_DMT_1280X1024P85,
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V4L2_DV_BT_DMT_1280X1024P120_RB,
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V4L2_DV_BT_DMT_1360X768P60,
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V4L2_DV_BT_DMT_1360X768P120_RB,
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V4L2_DV_BT_DMT_1366X768P60,
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V4L2_DV_BT_DMT_1366X768P60_RB,
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V4L2_DV_BT_DMT_1400X1050P60_RB,
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V4L2_DV_BT_DMT_1400X1050P60,
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V4L2_DV_BT_DMT_1400X1050P75,
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V4L2_DV_BT_DMT_1400X1050P85,
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V4L2_DV_BT_DMT_1400X1050P120_RB,
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V4L2_DV_BT_DMT_1440X900P60_RB,
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V4L2_DV_BT_DMT_1440X900P60,
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V4L2_DV_BT_DMT_1440X900P75,
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V4L2_DV_BT_DMT_1440X900P85,
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V4L2_DV_BT_DMT_1440X900P120_RB,
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V4L2_DV_BT_DMT_1600X900P60_RB,
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V4L2_DV_BT_DMT_1600X1200P60,
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V4L2_DV_BT_DMT_1600X1200P65,
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V4L2_DV_BT_DMT_1600X1200P70,
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V4L2_DV_BT_DMT_1600X1200P75,
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V4L2_DV_BT_DMT_1600X1200P85,
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V4L2_DV_BT_DMT_1600X1200P120_RB,
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V4L2_DV_BT_DMT_1680X1050P60_RB,
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V4L2_DV_BT_DMT_1680X1050P60,
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V4L2_DV_BT_DMT_1680X1050P75,
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V4L2_DV_BT_DMT_1680X1050P85,
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V4L2_DV_BT_DMT_1680X1050P120_RB,
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V4L2_DV_BT_DMT_1792X1344P60,
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V4L2_DV_BT_DMT_1792X1344P75,
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V4L2_DV_BT_DMT_1792X1344P120_RB,
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V4L2_DV_BT_DMT_1856X1392P60,
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V4L2_DV_BT_DMT_1856X1392P75,
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V4L2_DV_BT_DMT_1856X1392P120_RB,
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V4L2_DV_BT_DMT_1920X1200P60_RB,
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V4L2_DV_BT_DMT_1920X1200P60,
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V4L2_DV_BT_DMT_1920X1200P75,
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V4L2_DV_BT_DMT_1920X1200P85,
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V4L2_DV_BT_DMT_1920X1200P120_RB,
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V4L2_DV_BT_DMT_1920X1440P60,
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V4L2_DV_BT_DMT_1920X1440P75,
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V4L2_DV_BT_DMT_1920X1440P120_RB,
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V4L2_DV_BT_DMT_2048X1152P60_RB,
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V4L2_DV_BT_DMT_2560X1600P60_RB,
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V4L2_DV_BT_DMT_2560X1600P60,
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V4L2_DV_BT_DMT_2560X1600P75,
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V4L2_DV_BT_DMT_2560X1600P85,
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V4L2_DV_BT_DMT_2560X1600P120_RB,
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};
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bool v4l2_dv_valid_timings(const struct v4l2_dv_timings *t,
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const struct v4l2_dv_timings_cap *dvcap)
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{
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const struct v4l2_bt_timings *bt = &t->bt;
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const struct v4l2_bt_timings_cap *cap = &dvcap->bt;
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u32 caps = cap->capabilities;
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if (t->type != V4L2_DV_BT_656_1120)
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return false;
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if (t->type != dvcap->type ||
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bt->height < cap->min_height ||
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bt->height > cap->max_height ||
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bt->width < cap->min_width ||
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bt->width > cap->max_width ||
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bt->pixelclock < cap->min_pixelclock ||
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bt->pixelclock > cap->max_pixelclock ||
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(cap->standards && !(bt->standards & cap->standards)) ||
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(bt->interlaced && !(caps & V4L2_DV_BT_CAP_INTERLACED)) ||
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(!bt->interlaced && !(caps & V4L2_DV_BT_CAP_PROGRESSIVE)))
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return false;
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return true;
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}
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EXPORT_SYMBOL_GPL(v4l2_dv_valid_timings);
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int v4l2_enum_dv_timings_cap(struct v4l2_enum_dv_timings *t,
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const struct v4l2_dv_timings_cap *cap)
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{
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u32 i, idx;
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memset(t->reserved, 0, sizeof(t->reserved));
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for (i = idx = 0; i < ARRAY_SIZE(timings); i++) {
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if (v4l2_dv_valid_timings(timings + i, cap) &&
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idx++ == t->index) {
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t->timings = timings[i];
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return 0;
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}
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}
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(v4l2_enum_dv_timings_cap);
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bool v4l2_find_dv_timings_cap(struct v4l2_dv_timings *t,
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const struct v4l2_dv_timings_cap *cap,
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unsigned pclock_delta)
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{
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int i;
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if (!v4l2_dv_valid_timings(t, cap))
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return false;
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for (i = 0; i < ARRAY_SIZE(timings); i++) {
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if (v4l2_dv_valid_timings(timings + i, cap) &&
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v4l_match_dv_timings(t, timings + i, pclock_delta)) {
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*t = timings[i];
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return true;
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}
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}
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return false;
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}
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EXPORT_SYMBOL_GPL(v4l2_find_dv_timings_cap);
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@ -0,0 +1,67 @@
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/*
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* v4l2-dv-timings - Internal header with dv-timings helper functions
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*
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* Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef __V4L2_DV_TIMINGS_H
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#define __V4L2_DV_TIMINGS_H
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#include <linux/videodev2.h>
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/** v4l2_dv_valid_timings() - are these timings valid?
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* @t: the v4l2_dv_timings struct.
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* @cap: the v4l2_dv_timings_cap capabilities.
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*
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* Returns true if the given dv_timings struct is supported by the
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* hardware capabilities, returns false otherwise.
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*/
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bool v4l2_dv_valid_timings(const struct v4l2_dv_timings *t,
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const struct v4l2_dv_timings_cap *cap);
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/** v4l2_enum_dv_timings_cap() - Helper function to enumerate possible DV timings based on capabilities
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* @t: the v4l2_enum_dv_timings struct.
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* @cap: the v4l2_dv_timings_cap capabilities.
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*
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* This enumerates dv_timings using the full list of possible CEA-861 and DMT
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* timings, filtering out any timings that are not supported based on the
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* hardware capabilities.
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*
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* If a valid timing for the given index is found, it will fill in @t and
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* return 0, otherwise it returns -EINVAL.
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*/
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int v4l2_enum_dv_timings_cap(struct v4l2_enum_dv_timings *t,
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const struct v4l2_dv_timings_cap *cap);
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/** v4l2_find_dv_timings_cap() - Find the closest timings struct
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* @t: the v4l2_enum_dv_timings struct.
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* @cap: the v4l2_dv_timings_cap capabilities.
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* @pclock_delta: maximum delta between t->pixelclock and the timing struct
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* under consideration.
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*
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* This function tries to map the given timings to an entry in the
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* full list of possible CEA-861 and DMT timings, filtering out any timings
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* that are not supported based on the hardware capabilities.
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*
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* On success it will fill in @t with the found timings and it returns true.
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* On failure it will return false.
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*/
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bool v4l2_find_dv_timings_cap(struct v4l2_dv_timings *t,
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const struct v4l2_dv_timings_cap *cap,
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unsigned pclock_delta);
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#endif
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