crypto: caam/qi - add ablkcipher and authenc algorithms
Add support to submit ablkcipher and authenc algorithms
via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede}))
authenc(hmac(sha*),cbc({aes,des,des3_ede}))
caam/qi being a new driver, let's wait some time to settle down without
interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are
marked to be of lower priority than caam/jr ones (caamalg module).
Signed-off-by: Vakul Garg <vakul.garg@nxp.com>
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Horia Geantă
Herbert Xu
Родитель
67c2315def
Коммит
b189817cf7
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@ -87,6 +87,23 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
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To compile this as a module, choose M here: the module
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will be called caamalg.
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config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
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tristate "Queue Interface as Crypto API backend"
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depends on CRYPTO_DEV_FSL_CAAM_JR && FSL_DPAA && NET
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default y
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select CRYPTO_AUTHENC
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select CRYPTO_BLKCIPHER
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help
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Selecting this will use CAAM Queue Interface (QI) for sending
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& receiving crypto jobs to/from CAAM. This gives better performance
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than job ring interface when the number of cores are more than the
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number of job rings assigned to the kernel. The number of portals
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assigned to the kernel should also be more than the number of
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job rings.
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To compile this as a module, choose M here: the module
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will be called caamalg_qi.
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config CRYPTO_DEV_FSL_CAAM_AHASH_API
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tristate "Register hash algorithm implementations with Crypto API"
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depends on CRYPTO_DEV_FSL_CAAM_JR
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@ -136,4 +153,5 @@ config CRYPTO_DEV_FSL_CAAM_DEBUG
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information in the CAAM driver.
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config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC
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def_tristate CRYPTO_DEV_FSL_CAAM_CRYPTO_API
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def_tristate (CRYPTO_DEV_FSL_CAAM_CRYPTO_API || \
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CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI)
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@ -8,6 +8,7 @@ endif
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obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o
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obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o
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obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
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obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o
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obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o
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obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
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obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
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@ -266,8 +266,9 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
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/* aead_encrypt shared descriptor */
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desc = ctx->sh_desc_enc;
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cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ctx->authsize,
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is_rfc3686, nonce, ctx1_iv_off);
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cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize,
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ctx->authsize, is_rfc3686, nonce, ctx1_iv_off,
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false);
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dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
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desc_bytes(desc), DMA_TO_DEVICE);
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@ -299,7 +300,7 @@ skip_enc:
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desc = ctx->sh_desc_dec;
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cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,
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ctx->authsize, alg->caam.geniv, is_rfc3686,
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nonce, ctx1_iv_off);
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nonce, ctx1_iv_off, false);
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dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
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desc_bytes(desc), DMA_TO_DEVICE);
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@ -333,7 +334,7 @@ skip_enc:
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desc = ctx->sh_desc_enc;
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cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,
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ctx->authsize, is_rfc3686, nonce,
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ctx1_iv_off);
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ctx1_iv_off, false);
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dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
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desc_bytes(desc), DMA_TO_DEVICE);
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@ -265,17 +265,19 @@ static void init_sh_desc_key_aead(u32 * const desc,
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* split key is to be used, the size of the split key itself is
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* specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1,
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* SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP.
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* @ivsize: initialization vector size
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* @icvsize: integrity check value (ICV) size (truncated or full)
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* @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
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* @nonce: pointer to rfc3686 nonce
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* @ctx1_iv_off: IV offset in CONTEXT1 register
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* @is_qi: true when called from caam/qi
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*
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* Note: Requires an MDHA split key.
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*/
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void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
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struct alginfo *adata, unsigned int icvsize,
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const bool is_rfc3686, u32 *nonce,
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const u32 ctx1_iv_off)
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struct alginfo *adata, unsigned int ivsize,
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unsigned int icvsize, const bool is_rfc3686,
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u32 *nonce, const u32 ctx1_iv_off, const bool is_qi)
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{
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/* Note: Context registers are saved. */
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init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
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@ -284,6 +286,25 @@ void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
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append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
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OP_ALG_ENCRYPT);
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if (is_qi) {
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u32 *wait_load_cmd;
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/* REG3 = assoclen */
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append_seq_load(desc, 4, LDST_CLASS_DECO |
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LDST_SRCDST_WORD_DECO_MATH3 |
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(4 << LDST_OFFSET_SHIFT));
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wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
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JUMP_COND_CALM | JUMP_COND_NCP |
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JUMP_COND_NOP | JUMP_COND_NIP |
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JUMP_COND_NIFP);
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set_jump_tgt_here(desc, wait_load_cmd);
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append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
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LDST_SRCDST_BYTE_CONTEXT |
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(ctx1_iv_off << LDST_OFFSET_SHIFT));
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}
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/* Read and write assoclen bytes */
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append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
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append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
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@ -338,6 +359,7 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_encap);
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* @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
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* @nonce: pointer to rfc3686 nonce
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* @ctx1_iv_off: IV offset in CONTEXT1 register
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* @is_qi: true when called from caam/qi
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*
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* Note: Requires an MDHA split key.
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*/
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@ -345,7 +367,7 @@ void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
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struct alginfo *adata, unsigned int ivsize,
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unsigned int icvsize, const bool geniv,
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const bool is_rfc3686, u32 *nonce,
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const u32 ctx1_iv_off)
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const u32 ctx1_iv_off, const bool is_qi)
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{
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/* Note: Context registers are saved. */
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init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
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@ -354,6 +376,26 @@ void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
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append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
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OP_ALG_DECRYPT | OP_ALG_ICV_ON);
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if (is_qi) {
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u32 *wait_load_cmd;
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/* REG3 = assoclen */
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append_seq_load(desc, 4, LDST_CLASS_DECO |
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LDST_SRCDST_WORD_DECO_MATH3 |
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(4 << LDST_OFFSET_SHIFT));
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wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
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JUMP_COND_CALM | JUMP_COND_NCP |
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JUMP_COND_NOP | JUMP_COND_NIP |
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JUMP_COND_NIFP);
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set_jump_tgt_here(desc, wait_load_cmd);
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if (!geniv)
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append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
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LDST_SRCDST_BYTE_CONTEXT |
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(ctx1_iv_off << LDST_OFFSET_SHIFT));
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}
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/* Read and write assoclen bytes */
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append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
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if (geniv)
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@ -423,21 +465,44 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_decap);
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* @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
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* @nonce: pointer to rfc3686 nonce
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* @ctx1_iv_off: IV offset in CONTEXT1 register
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* @is_qi: true when called from caam/qi
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*
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* Note: Requires an MDHA split key.
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*/
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void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
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struct alginfo *adata, unsigned int ivsize,
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unsigned int icvsize, const bool is_rfc3686,
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u32 *nonce, const u32 ctx1_iv_off)
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u32 *nonce, const u32 ctx1_iv_off,
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const bool is_qi)
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{
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u32 geniv, moveiv;
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/* Note: Context registers are saved. */
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init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
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if (is_rfc3686)
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if (is_qi) {
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u32 *wait_load_cmd;
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/* REG3 = assoclen */
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append_seq_load(desc, 4, LDST_CLASS_DECO |
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LDST_SRCDST_WORD_DECO_MATH3 |
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(4 << LDST_OFFSET_SHIFT));
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wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
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JUMP_COND_CALM | JUMP_COND_NCP |
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JUMP_COND_NOP | JUMP_COND_NIP |
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JUMP_COND_NIFP);
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set_jump_tgt_here(desc, wait_load_cmd);
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}
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if (is_rfc3686) {
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if (is_qi)
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append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
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LDST_SRCDST_BYTE_CONTEXT |
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(ctx1_iv_off << LDST_OFFSET_SHIFT));
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goto copy_iv;
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}
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/* Generate IV */
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geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
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@ -12,6 +12,9 @@
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#define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 11 * CAAM_CMD_SZ)
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#define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 15 * CAAM_CMD_SZ)
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#define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
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#define DESC_QI_AEAD_ENC_LEN (DESC_AEAD_ENC_LEN + 3 * CAAM_CMD_SZ)
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#define DESC_QI_AEAD_DEC_LEN (DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ)
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#define DESC_QI_AEAD_GIVENC_LEN (DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ)
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/* Note: Nonce is counted in cdata.keylen */
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#define DESC_AEAD_CTR_RFC3686_LEN (4 * CAAM_CMD_SZ)
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@ -45,20 +48,22 @@ void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata,
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unsigned int icvsize);
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void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
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struct alginfo *adata, unsigned int icvsize,
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const bool is_rfc3686, u32 *nonce,
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const u32 ctx1_iv_off);
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struct alginfo *adata, unsigned int ivsize,
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unsigned int icvsize, const bool is_rfc3686,
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u32 *nonce, const u32 ctx1_iv_off,
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const bool is_qi);
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void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
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struct alginfo *adata, unsigned int ivsize,
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unsigned int icvsize, const bool geniv,
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const bool is_rfc3686, u32 *nonce,
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const u32 ctx1_iv_off);
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const u32 ctx1_iv_off, const bool is_qi);
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void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
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struct alginfo *adata, unsigned int ivsize,
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unsigned int icvsize, const bool is_rfc3686,
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u32 *nonce, const u32 ctx1_iv_off);
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u32 *nonce, const u32 ctx1_iv_off,
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const bool is_qi);
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void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,
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unsigned int icvsize);
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Загрузить разницу
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@ -0,0 +1,108 @@
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/*
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* Copyright 2013-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
|
||||
*
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||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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||||
|
||||
#ifndef __SG_SW_QM_H
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#define __SG_SW_QM_H
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#include <soc/fsl/qman.h>
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#include "regs.h"
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static inline void __dma_to_qm_sg(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma,
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u16 offset)
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{
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qm_sg_entry_set64(qm_sg_ptr, dma);
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qm_sg_ptr->__reserved2 = 0;
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qm_sg_ptr->bpid = 0;
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qm_sg_ptr->offset = cpu_to_be16(offset & QM_SG_OFF_MASK);
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}
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static inline void dma_to_qm_sg_one(struct qm_sg_entry *qm_sg_ptr,
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dma_addr_t dma, u32 len, u16 offset)
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{
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__dma_to_qm_sg(qm_sg_ptr, dma, offset);
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qm_sg_entry_set_len(qm_sg_ptr, len);
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}
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static inline void dma_to_qm_sg_one_last(struct qm_sg_entry *qm_sg_ptr,
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dma_addr_t dma, u32 len, u16 offset)
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{
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__dma_to_qm_sg(qm_sg_ptr, dma, offset);
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qm_sg_entry_set_f(qm_sg_ptr, len);
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}
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static inline void dma_to_qm_sg_one_ext(struct qm_sg_entry *qm_sg_ptr,
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dma_addr_t dma, u32 len, u16 offset)
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{
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__dma_to_qm_sg(qm_sg_ptr, dma, offset);
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qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | (len & QM_SG_LEN_MASK));
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}
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static inline void dma_to_qm_sg_one_last_ext(struct qm_sg_entry *qm_sg_ptr,
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dma_addr_t dma, u32 len,
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u16 offset)
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{
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__dma_to_qm_sg(qm_sg_ptr, dma, offset);
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qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | QM_SG_FIN |
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(len & QM_SG_LEN_MASK));
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}
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/*
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||||
* convert scatterlist to h/w link table format
|
||||
* but does not have final bit; instead, returns last entry
|
||||
*/
|
||||
static inline struct qm_sg_entry *
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sg_to_qm_sg(struct scatterlist *sg, int sg_count,
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struct qm_sg_entry *qm_sg_ptr, u16 offset)
|
||||
{
|
||||
while (sg_count && sg) {
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||||
dma_to_qm_sg_one(qm_sg_ptr, sg_dma_address(sg),
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sg_dma_len(sg), offset);
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qm_sg_ptr++;
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sg = sg_next(sg);
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sg_count--;
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||||
}
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return qm_sg_ptr - 1;
|
||||
}
|
||||
|
||||
/*
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||||
* convert scatterlist to h/w link table format
|
||||
* scatterlist must have been previously dma mapped
|
||||
*/
|
||||
static inline void sg_to_qm_sg_last(struct scatterlist *sg, int sg_count,
|
||||
struct qm_sg_entry *qm_sg_ptr, u16 offset)
|
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{
|
||||
qm_sg_ptr = sg_to_qm_sg(sg, sg_count, qm_sg_ptr, offset);
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qm_sg_entry_set_f(qm_sg_ptr, qm_sg_entry_get_len(qm_sg_ptr));
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}
|
||||
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#endif /* __SG_SW_QM_H */
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Ссылка в новой задаче