Merge series "soundwire/ASoC: abstract platform-dependent bases" from Bard Liao <yung-chuan.liao@linux.intel.com>:
shim base and alh base are platform-dependent. This series suggests to use variables for those bases. It allows us to use different bases for new platforms. v2: - Update the commit message of "soundwire: move intel sdw register definitions to sdw_intel.h" Bard Liao (6): soundwire: move intel sdw register definitions to sdw_intel.h ASoC: SOF: intel: add sdw_shim/alh_base to sof_intel_dsp_desc ASoC: SOF: intel: hda: remove HDA_DSP_REG_SNDW_WAKE_STS definition ASoC: SOF: intel: move sof_intel_dsp_desc() forward ASoC: SOF: intel: add snd_sof_dsp_check_sdw_irq ops soundwire: intel: introduce shim and alh base drivers/soundwire/intel.c | 74 ------------------------ drivers/soundwire/intel_init.c | 14 ++--- include/linux/soundwire/sdw_intel.h | 87 +++++++++++++++++++++++++++++ sound/soc/sof/intel/cnl.c | 6 ++ sound/soc/sof/intel/hda.c | 39 ++++++++----- sound/soc/sof/intel/hda.h | 8 ++- sound/soc/sof/intel/icl.c | 3 + sound/soc/sof/intel/shim.h | 3 + sound/soc/sof/intel/tgl.c | 12 ++++ 9 files changed, 149 insertions(+), 97 deletions(-) -- 2.17.1
This commit is contained in:
Mark Brown
Коммит
b189dde9d3
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@ -40,80 +40,6 @@ static int md_flags;
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module_param_named(sdw_md_flags, md_flags, int, 0444);
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MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
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/* Intel SHIM Registers Definition */
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#define SDW_SHIM_LCAP 0x0
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#define SDW_SHIM_LCTL 0x4
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#define SDW_SHIM_IPPTR 0x8
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#define SDW_SHIM_SYNC 0xC
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#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
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#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
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#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
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#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
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#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
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#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
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#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
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#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
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#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
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#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
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#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
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#define SDW_SHIM_WAKEEN 0x190
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#define SDW_SHIM_WAKESTS 0x192
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#define SDW_SHIM_LCTL_SPA BIT(0)
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#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
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#define SDW_SHIM_LCTL_CPA BIT(8)
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#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
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#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
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#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
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#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
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#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
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#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
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#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
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#define SDW_SHIM_SYNC_SYNCGO BIT(24)
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#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
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#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
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#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
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#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
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#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
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#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
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#define SDW_SHIM_PCMSYCM_DIR BIT(15)
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#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
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#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
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#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
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#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
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#define SDW_SHIM_IOCTL_MIF BIT(0)
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#define SDW_SHIM_IOCTL_CO BIT(1)
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#define SDW_SHIM_IOCTL_COE BIT(2)
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#define SDW_SHIM_IOCTL_DO BIT(3)
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#define SDW_SHIM_IOCTL_DOE BIT(4)
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#define SDW_SHIM_IOCTL_BKE BIT(5)
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#define SDW_SHIM_IOCTL_WPDD BIT(6)
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#define SDW_SHIM_IOCTL_CIBD BIT(8)
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#define SDW_SHIM_IOCTL_DIBD BIT(9)
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#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
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#define SDW_SHIM_CTMCTL_DODS BIT(1)
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#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
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#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
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#define SDW_SHIM_WAKESTS_STATUS BIT(0)
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/* Intel ALH Register definitions */
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#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
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#define SDW_ALH_NUM_STREAMS 64
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#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
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#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
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#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
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enum intel_pdi_type {
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INTEL_PDI_IN = 0,
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INTEL_PDI_OUT = 1,
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@ -18,12 +18,6 @@
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#include "cadence_master.h"
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#include "intel.h"
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#define SDW_SHIM_LCAP 0x0
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#define SDW_SHIM_BASE 0x2C000
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#define SDW_ALH_BASE 0x2C800
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#define SDW_LINK_BASE 0x30000
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#define SDW_LINK_SIZE 0x10000
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static void intel_link_dev_release(struct device *dev)
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{
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struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
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@ -69,8 +63,8 @@ static struct sdw_intel_link_dev *intel_link_dev_register(struct sdw_intel_res *
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link->mmio_base = res->mmio_base;
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link->registers = res->mmio_base + SDW_LINK_BASE
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+ (SDW_LINK_SIZE * link_id);
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link->shim = res->mmio_base + SDW_SHIM_BASE;
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link->alh = res->mmio_base + SDW_ALH_BASE;
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link->shim = res->mmio_base + res->shim_base;
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link->alh = res->mmio_base + res->alh_base;
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link->ops = res->ops;
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link->dev = res->dev;
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@ -220,6 +214,8 @@ static struct sdw_intel_ctx
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}
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ctx->mmio_base = res->mmio_base;
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ctx->shim_base = res->shim_base;
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ctx->alh_base = res->alh_base;
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ctx->link_mask = res->link_mask;
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ctx->handle = res->handle;
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mutex_init(&ctx->shim_lock);
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@ -308,7 +304,7 @@ sdw_intel_startup_controller(struct sdw_intel_ctx *ctx)
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return -EINVAL;
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/* Check SNDWLCAP.LCOUNT */
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caps = ioread32(ctx->mmio_base + SDW_SHIM_BASE + SDW_SHIM_LCAP);
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caps = ioread32(ctx->mmio_base + ctx->shim_base + SDW_SHIM_LCAP);
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caps &= GENMASK(2, 0);
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/* Check HW supported vs property value */
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@ -7,6 +7,85 @@
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#include <linux/irqreturn.h>
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#include <linux/soundwire/sdw.h>
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#define SDW_SHIM_BASE 0x2C000
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#define SDW_ALH_BASE 0x2C800
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#define SDW_LINK_BASE 0x30000
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#define SDW_LINK_SIZE 0x10000
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/* Intel SHIM Registers Definition */
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#define SDW_SHIM_LCAP 0x0
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#define SDW_SHIM_LCTL 0x4
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#define SDW_SHIM_IPPTR 0x8
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#define SDW_SHIM_SYNC 0xC
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#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
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#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
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#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
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#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
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#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
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#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
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#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
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#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
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#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
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#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
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#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
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#define SDW_SHIM_WAKEEN 0x190
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#define SDW_SHIM_WAKESTS 0x192
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#define SDW_SHIM_LCTL_SPA BIT(0)
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#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
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#define SDW_SHIM_LCTL_CPA BIT(8)
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#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
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#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
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#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
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#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
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#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
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#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
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#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
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#define SDW_SHIM_SYNC_SYNCGO BIT(24)
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#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
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#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
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#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
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#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
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#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
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#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
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#define SDW_SHIM_PCMSYCM_DIR BIT(15)
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#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
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#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
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#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
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#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
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#define SDW_SHIM_IOCTL_MIF BIT(0)
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#define SDW_SHIM_IOCTL_CO BIT(1)
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#define SDW_SHIM_IOCTL_COE BIT(2)
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#define SDW_SHIM_IOCTL_DO BIT(3)
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#define SDW_SHIM_IOCTL_DOE BIT(4)
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#define SDW_SHIM_IOCTL_BKE BIT(5)
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#define SDW_SHIM_IOCTL_WPDD BIT(6)
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#define SDW_SHIM_IOCTL_CIBD BIT(8)
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#define SDW_SHIM_IOCTL_DIBD BIT(9)
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#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
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#define SDW_SHIM_CTMCTL_DODS BIT(1)
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#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
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#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
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#define SDW_SHIM_WAKESTS_STATUS BIT(0)
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/* Intel ALH Register definitions */
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#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
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#define SDW_ALH_NUM_STREAMS 64
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#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
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#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
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#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
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/**
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* struct sdw_intel_stream_params_data: configuration passed during
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* the @params_stream callback, e.g. for interaction with DSP
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@ -116,6 +195,8 @@ struct sdw_intel_slave_id {
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* @link_list: list to handle interrupts across all links
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* @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
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* @shim_mask: flags to track initialization of SHIM shared registers
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* @shim_base: sdw shim base.
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* @alh_base: sdw alh base.
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*/
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struct sdw_intel_ctx {
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int count;
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@ -128,6 +209,8 @@ struct sdw_intel_ctx {
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struct list_head link_list;
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struct mutex shim_lock; /* lock for access to shared SHIM registers */
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u32 shim_mask;
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u32 shim_base;
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u32 alh_base;
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};
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/**
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@ -146,6 +229,8 @@ struct sdw_intel_ctx {
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* machine-specific quirks are handled in the DSP driver.
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* @clock_stop_quirks: mask array of possible behaviors requested by the
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* DSP driver. The quirks are common for all links for now.
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* @shim_base: sdw shim base.
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* @alh_base: sdw alh base.
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*/
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struct sdw_intel_res {
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int count;
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@ -157,6 +242,8 @@ struct sdw_intel_res {
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struct device *dev;
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u32 link_mask;
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u32 clock_stop_quirks;
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u32 shim_base;
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u32 alh_base;
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};
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/*
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@ -347,6 +347,9 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
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.rom_init_timeout = 300,
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.ssp_count = CNL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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.sdw_shim_base = SDW_SHIM_BASE,
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.sdw_alh_base = SDW_ALH_BASE,
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.check_sdw_irq = hda_common_check_sdw_irq,
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};
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EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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@ -363,5 +366,8 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
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.rom_init_timeout = 300,
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.ssp_count = ICL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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.sdw_shim_base = SDW_SHIM_BASE,
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.sdw_alh_base = SDW_ALH_BASE,
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.check_sdw_irq = hda_common_check_sdw_irq,
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};
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EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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@ -41,6 +41,17 @@
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#define EXCEPT_MAX_HDR_SIZE 0x400
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#define HDA_EXT_ROM_STATUS_SIZE 8
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static const struct sof_intel_dsp_desc
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*get_chip_info(struct snd_sof_pdata *pdata)
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{
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const struct sof_dev_desc *desc = pdata->desc;
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const struct sof_intel_dsp_desc *chip_info;
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chip_info = desc->chip_info;
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return chip_info;
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}
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
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/*
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@ -155,6 +166,8 @@ static int hda_sdw_probe(struct snd_sof_dev *sdev)
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memset(&res, 0, sizeof(res));
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res.mmio_base = sdev->bar[HDA_DSP_BAR];
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res.shim_base = hdev->desc->sdw_shim_base;
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res.alh_base = hdev->desc->sdw_alh_base;
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res.irq = sdev->ipc_irq;
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res.handle = hdev->info.handle;
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res.parent = sdev->dev;
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@ -211,7 +224,7 @@ static int hda_sdw_exit(struct snd_sof_dev *sdev)
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return 0;
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}
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static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
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bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
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{
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struct sof_intel_hda_dev *hdev;
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bool ret = false;
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@ -237,6 +250,17 @@ out:
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return ret;
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}
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static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
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{
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const struct sof_intel_dsp_desc *chip;
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chip = get_chip_info(sdev->pdata);
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if (chip && chip->check_sdw_irq)
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return chip->check_sdw_irq(sdev);
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return false;
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}
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static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
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{
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return sdw_intel_thread(irq, context);
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@ -249,7 +273,7 @@ static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
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hdev = sdev->pdata->hw_pdata;
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if (hdev->sdw &&
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snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_SNDW_WAKE_STS))
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hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS))
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return true;
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return false;
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@ -668,17 +692,6 @@ skip_soundwire:
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return 0;
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}
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static const struct sof_intel_dsp_desc
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*get_chip_info(struct snd_sof_pdata *pdata)
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{
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const struct sof_dev_desc *desc = pdata->desc;
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const struct sof_intel_dsp_desc *chip_info;
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chip_info = desc->chip_info;
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return chip_info;
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}
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static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context)
|
||||
{
|
||||
struct snd_sof_dev *sdev = context;
|
||||
|
|
|
|||
|
|
@ -233,7 +233,6 @@
|
|||
#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
|
||||
|
||||
#define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
|
||||
#define HDA_DSP_REG_SNDW_WAKE_STS 0x2C192
|
||||
|
||||
/* Intel HD Audio Inter-Processor Communication Registers */
|
||||
#define HDA_DSP_IPC_BASE 0x40
|
||||
|
|
@ -692,6 +691,7 @@ int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
|
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int hda_sdw_startup(struct snd_sof_dev *sdev);
|
||||
void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
|
||||
void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
|
||||
bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
|
||||
|
||||
#else
|
||||
|
||||
|
|
@ -737,6 +737,12 @@ static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
|
|||
static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
|
||||
{
|
||||
}
|
||||
|
||||
static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* common dai driver */
|
||||
|
|
|
|||
|
|
@ -142,5 +142,8 @@ const struct sof_intel_dsp_desc icl_chip_info = {
|
|||
.rom_init_timeout = 300,
|
||||
.ssp_count = ICL_SSP_COUNT,
|
||||
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
|
||||
.sdw_shim_base = SDW_SHIM_BASE,
|
||||
.sdw_alh_base = SDW_ALH_BASE,
|
||||
.check_sdw_irq = hda_common_check_sdw_irq,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
|
|
|
|||
|
|
@ -164,6 +164,9 @@ struct sof_intel_dsp_desc {
|
|||
int rom_init_timeout;
|
||||
int ssp_count; /* ssp count of the platform */
|
||||
int ssp_base_offset; /* base address of the SSPs */
|
||||
u32 sdw_shim_base;
|
||||
u32 sdw_alh_base;
|
||||
bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
|
||||
};
|
||||
|
||||
extern const struct snd_sof_dsp_ops sof_tng_ops;
|
||||
|
|
|
|||
|
|
@ -137,6 +137,9 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
|
|||
.rom_init_timeout = 300,
|
||||
.ssp_count = ICL_SSP_COUNT,
|
||||
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
|
||||
.sdw_shim_base = SDW_SHIM_BASE,
|
||||
.sdw_alh_base = SDW_ALH_BASE,
|
||||
.check_sdw_irq = hda_common_check_sdw_irq,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
|
||||
|
|
@ -153,6 +156,9 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
|
|||
.rom_init_timeout = 300,
|
||||
.ssp_count = ICL_SSP_COUNT,
|
||||
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
|
||||
.sdw_shim_base = SDW_SHIM_BASE,
|
||||
.sdw_alh_base = SDW_ALH_BASE,
|
||||
.check_sdw_irq = hda_common_check_sdw_irq,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
|
||||
|
|
@ -169,6 +175,9 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
|
|||
.rom_init_timeout = 300,
|
||||
.ssp_count = ICL_SSP_COUNT,
|
||||
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
|
||||
.sdw_shim_base = SDW_SHIM_BASE,
|
||||
.sdw_alh_base = SDW_ALH_BASE,
|
||||
.check_sdw_irq = hda_common_check_sdw_irq,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
|
||||
|
|
@ -185,5 +194,8 @@ const struct sof_intel_dsp_desc adls_chip_info = {
|
|||
.rom_init_timeout = 300,
|
||||
.ssp_count = ICL_SSP_COUNT,
|
||||
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
|
||||
.sdw_shim_base = SDW_SHIM_BASE,
|
||||
.sdw_alh_base = SDW_ALH_BASE,
|
||||
.check_sdw_irq = hda_common_check_sdw_irq,
|
||||
};
|
||||
EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
|
||||
|
|
|
|||
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