KVM: arm/arm64: vgic-new: Add data structure definitions
Add a new header file for the new and improved GIC implementation. The big change is that we now have a struct vgic_irq per IRQ instead of spreading all the information over various bitmaps. We include this new header conditionally from within the old header file for the time being to avoid touching all the users. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Christoffer Dall
Родитель
44bfc42e94
Коммит
b18b57787f
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@ -19,6 +19,10 @@
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#ifndef __ASM_ARM_KVM_VGIC_H
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#define __ASM_ARM_KVM_VGIC_H
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#ifdef CONFIG_KVM_NEW_VGIC
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#include <kvm/vgic/vgic.h>
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#else
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#include <linux/kernel.h>
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#include <linux/kvm.h>
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#include <linux/irqreturn.h>
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@ -367,4 +371,5 @@ static inline int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info,
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}
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#endif
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#endif /* old VGIC include */
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#endif
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@ -0,0 +1,201 @@
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/*
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* Copyright (C) 2015, 2016 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARM_KVM_VGIC_VGIC_H
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#define __ASM_ARM_KVM_VGIC_VGIC_H
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#include <linux/kernel.h>
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#include <linux/kvm.h>
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#include <linux/irqreturn.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <kvm/iodev.h>
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#define VGIC_V3_MAX_CPUS 255
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#define VGIC_V2_MAX_CPUS 8
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#define VGIC_NR_IRQS_LEGACY 256
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#define VGIC_NR_SGIS 16
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#define VGIC_NR_PPIS 16
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#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
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#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1)
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#define VGIC_MAX_SPI 1019
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#define VGIC_MAX_RESERVED 1023
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#define VGIC_MIN_LPI 8192
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enum vgic_type {
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VGIC_V2, /* Good ol' GICv2 */
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VGIC_V3, /* New fancy GICv3 */
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};
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/* same for all guests, as depending only on the _host's_ GIC model */
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struct vgic_global {
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/* type of the host GIC */
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enum vgic_type type;
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/* Physical address of vgic virtual cpu interface */
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phys_addr_t vcpu_base;
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/* virtual control interface mapping */
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void __iomem *vctrl_base;
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/* Number of implemented list registers */
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int nr_lr;
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/* Maintenance IRQ number */
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unsigned int maint_irq;
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/* maximum number of VCPUs allowed (GICv2 limits us to 8) */
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int max_gic_vcpus;
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/* Only needed for the legacy KVM_CREATE_IRQCHIP */
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bool can_emulate_gicv2;
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};
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extern struct vgic_global kvm_vgic_global_state;
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#define VGIC_V2_MAX_LRS (1 << 6)
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#define VGIC_V3_MAX_LRS 16
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#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr)
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enum vgic_irq_config {
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VGIC_CONFIG_EDGE = 0,
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VGIC_CONFIG_LEVEL
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};
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struct vgic_irq {
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spinlock_t irq_lock; /* Protects the content of the struct */
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struct list_head ap_list;
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struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
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* SPIs and LPIs: The VCPU whose ap_list
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* this is queued on.
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*/
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struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should
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* be sent to, as a result of the
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* targets reg (v2) or the
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* affinity reg (v3).
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*/
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u32 intid; /* Guest visible INTID */
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bool pending;
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bool line_level; /* Level only */
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bool soft_pending; /* Level only */
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bool active; /* not used for LPIs */
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bool enabled;
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bool hw; /* Tied to HW IRQ */
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u32 hwintid; /* HW INTID number */
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union {
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u8 targets; /* GICv2 target VCPUs mask */
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u32 mpidr; /* GICv3 target VCPU */
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};
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u8 source; /* GICv2 SGIs only */
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u8 priority;
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enum vgic_irq_config config; /* Level or edge */
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};
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struct vgic_dist {
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bool in_kernel;
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bool ready;
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/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
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u32 vgic_model;
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int nr_spis;
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/* TODO: Consider moving to global state */
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/* Virtual control interface mapping */
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void __iomem *vctrl_base;
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/* base addresses in guest physical address space: */
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gpa_t vgic_dist_base; /* distributor */
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union {
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/* either a GICv2 CPU interface */
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gpa_t vgic_cpu_base;
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/* or a number of GICv3 redistributor regions */
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gpa_t vgic_redist_base;
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};
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/* distributor enabled */
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bool enabled;
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struct vgic_irq *spis;
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};
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struct vgic_v2_cpu_if {
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u32 vgic_hcr;
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u32 vgic_vmcr;
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u32 vgic_misr; /* Saved only */
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u64 vgic_eisr; /* Saved only */
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u64 vgic_elrsr; /* Saved only */
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u32 vgic_apr;
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u32 vgic_lr[VGIC_V2_MAX_LRS];
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};
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struct vgic_v3_cpu_if {
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#ifdef CONFIG_KVM_ARM_VGIC_V3
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u32 vgic_hcr;
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u32 vgic_vmcr;
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u32 vgic_sre; /* Restored only, change ignored */
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u32 vgic_misr; /* Saved only */
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u32 vgic_eisr; /* Saved only */
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u32 vgic_elrsr; /* Saved only */
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u32 vgic_ap0r[4];
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u32 vgic_ap1r[4];
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u64 vgic_lr[VGIC_V3_MAX_LRS];
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#endif
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};
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struct vgic_cpu {
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/* CPU vif control registers for world switch */
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union {
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struct vgic_v2_cpu_if vgic_v2;
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struct vgic_v3_cpu_if vgic_v3;
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};
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unsigned int used_lrs;
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struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS];
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spinlock_t ap_list_lock; /* Protects the ap_list */
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/*
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* List of IRQs that this VCPU should consider because they are either
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* Active or Pending (hence the name; AP list), or because they recently
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* were one of the two and need to be migrated off this list to another
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* VCPU.
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*/
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struct list_head ap_list_head;
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u64 live_lrs;
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};
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#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
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#define vgic_initialized(k) (false)
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#define vgic_ready(k) ((k)->arch.vgic.ready)
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#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \
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((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
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/**
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* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
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*
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* The host's GIC naturally limits the maximum amount of VCPUs a guest
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* can use.
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*/
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static inline int kvm_vgic_get_max_vcpus(void)
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{
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return kvm_vgic_global_state.max_gic_vcpus;
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}
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#endif /* __ASM_ARM_KVM_VGIC_VGIC_H */
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