ARM: GIC: remove direct use of gic_raise_softirq
In preparation of moving gic code to drivers/irqchip, remove the direct platform dependencies on gic_raise_softirq. Move the setup of smp_cross_call into the gic code and use arch_send_wakeup_ipi_mask function to trigger wake-up IPIs. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Stephen Warren <swarren@nvidia.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net>
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@ -617,6 +617,27 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
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}
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#endif
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#ifdef CONFIG_SMP
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void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
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{
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int cpu;
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unsigned long map = 0;
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/* Convert our logical CPU mask into a physical one. */
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for_each_cpu(cpu, mask)
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map |= 1 << cpu_logical_map(cpu);
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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dsb();
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/* this always happens on GIC0 */
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writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
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}
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#endif
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static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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@ -743,6 +764,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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if (WARN_ON(!gic->domain))
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return;
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#ifdef CONFIG_SMP
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set_smp_cross_call(gic_raise_softirq);
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#endif
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gic_chip.flags |= gic_arch_extn.flags;
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gic_dist_init(gic);
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gic_cpu_init(gic);
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@ -756,27 +780,6 @@ void __cpuinit gic_secondary_init(unsigned int gic_nr)
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gic_cpu_init(&gic_data[gic_nr]);
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}
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#ifdef CONFIG_SMP
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void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
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{
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int cpu;
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unsigned long map = 0;
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/* Convert our logical CPU mask into a physical one. */
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for_each_cpu(cpu, mask)
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map |= gic_cpu_map[cpu];
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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dsb();
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/* this always happens on GIC0 */
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writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
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}
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#endif
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#ifdef CONFIG_OF
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static int gic_cnt __initdata = 0;
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@ -40,7 +40,6 @@ int gic_of_init(struct device_node *node, struct device_node *parent);
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void gic_secondary_init(unsigned int);
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void gic_handle_irq(struct pt_regs *regs);
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void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
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void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
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static inline void gic_init(unsigned int nr, int start,
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void __iomem *dist , void __iomem *cpu)
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@ -416,7 +416,8 @@ static void (*smp_cross_call)(const struct cpumask *, unsigned int);
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void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
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{
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smp_cross_call = fn;
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if (!smp_cross_call)
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smp_cross_call = fn;
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}
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void arch_send_call_function_ipi_mask(const struct cpumask *mask)
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@ -149,7 +149,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
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__raw_writel(virt_to_phys(exynos4_secondary_startup),
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cpu_boot_reg(phys_cpu));
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gic_raise_softirq(cpumask_of(cpu), 0);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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if (pen_release == -1)
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break;
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@ -190,8 +190,6 @@ static void __init exynos_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
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@ -33,7 +33,7 @@ static void __cpuinit highbank_secondary_init(unsigned int cpu)
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static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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highbank_set_cpu_jump(cpu, secondary_startup);
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gic_raise_softirq(cpumask_of(cpu), 0);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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@ -56,8 +56,6 @@ static void __init highbank_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
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@ -71,8 +71,6 @@ static void __init imx_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void imx_smp_prepare(void)
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@ -115,7 +115,7 @@ static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *id
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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gic_raise_softirq(cpumask_of(cpu), 0);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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@ -153,8 +153,6 @@ static void __init msm_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
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@ -157,7 +157,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
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booted = true;
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}
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gic_raise_softirq(cpumask_of(cpu), 0);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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/*
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* Now the secondary core is starting up let it run its
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@ -231,8 +231,6 @@ static void __init omap4_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
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@ -14,7 +14,6 @@
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <asm/smp_scu.h>
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@ -59,8 +58,6 @@ static void __init realview_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init realview_smp_prepare_cpus(unsigned int max_cpus)
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@ -26,6 +26,4 @@ void __init shmobile_smp_init_cpus(unsigned int ncores)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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@ -100,7 +100,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
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/* Tell ROM loader about our vector (in headsmp.S) */
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emev2_set_boot_vector(__pa(shmobile_secondary_vector));
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gic_raise_softirq(cpumask_of(cpu), 0);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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@ -83,8 +83,6 @@ static void __init socfpga_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
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@ -104,8 +104,6 @@ static void __init spear13xx_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)
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@ -159,8 +159,6 @@ static void __init tegra_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
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@ -91,7 +91,7 @@ static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *
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*/
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write_pen_release(cpu_logical_map(cpu));
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gic_raise_softirq(cpumask_of(cpu), 0);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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@ -155,8 +155,6 @@ static void __init ux500_smp_init_cpus(void)
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
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@ -182,8 +182,6 @@ static void __init ct_ca9x4_init_cpu_map(void)
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for (i = 0; i < ncores; ++i)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
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@ -128,8 +128,6 @@ static void __init vexpress_dt_smp_init_cpus(void)
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for (i = 0; i < ncores; ++i)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
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@ -79,7 +79,7 @@ int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idl
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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gic_raise_softirq(cpumask_of(cpu), 0);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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